Update autofdo configuration and etm4 strobing feature example to use new resource allocation methods.
Signed-off-by: Mike Leach mike.leach@linaro.org --- .../hwtracing/coresight/coresight-cfg-afdo.c | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c b/drivers/hwtracing/coresight/coresight-cfg-afdo.c index 84b31184252b..cae142827d44 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-afdo.c +++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c @@ -30,63 +30,63 @@ static struct cscfg_regval_desc strobe_regs[] = { /* resource selectors */ { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCRSCTLRn(2), + .offset = 2, .hw_info = ETM4_CFG_RES_SEL, .val32 = 0x20001, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCRSCTLRn(3), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 3, + .hw_info = ETM4_CFG_RES_SEL, .val32 = 0x20002, }, /* strobe window counter 0 - reload from param 0 */ { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, - .offset = TRCCNTVRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_VAL, }, { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, - .offset = TRCCNTRLDVRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_RLD, .val32 = 0, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCCNTCTLRn(0), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 0, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_CTRL, .val32 = 0x10001, }, /* strobe period counter 1 - reload from param 1 */ { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE, - .offset = TRCCNTVRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_VAL, }, { .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM, - .offset = TRCCNTRLDVRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_RLD, .val32 = 1, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCCNTCTLRn(1), - .hw_info = ETM4_CFG_RES_CTR, + .offset = 1, + .hw_info = ETM4_CFG_RES_CTR | ETM4_CTR_CTRL, .val32 = 0x8102, }, /* sequencer */ { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCSEQEVRn(0), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 0, + .hw_info = ETM4_CFG_RES_SEQ | ETM4_SEQ_STATE_R, .val32 = 0x0081, }, { .type = CS_CFG_REG_TYPE_RESOURCE, - .offset = TRCSEQEVRn(1), - .hw_info = ETM4_CFG_RES_SEQ, + .offset = 1, + .hw_info = ETM4_CFG_RES_SEQ | ETM4_SEQ_STATE_R, .val32 = 0x0000, }, /* view-inst */