it is actually the code in the function cs_trace_enable() in cs_trace_source.c from CSAL that does this, so I assumed that this was correct. https://github.com/ARM- software/CSAL/blob/790f714544b2329d657619d7cc0f063c3c9e5e78/source/cs _trace_source.c#L136
The Coresight documentation says, about the ETMEN bit: This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM so I assume it should be set. Also I noticed, that there is no trace output to the buffer when I remove the line that sets it, so I think it has to be enabled.
We added the setting of ETMEN in 2013. I recollect we did that because we had a platform where we weren't getting trace until we set it. The ETM architecture says "you must not use the ETMEN signal to gate the ETM clock or any other functionality required for basic operation. The ETMEN signal can be used to control functionality that is only required for off-chip tracing..." But it's possible some designs do use ETMEN to gate on-chip functionality.
As Mike says, it would be more correct to set ETMEN while programming is still enabled (as you've tried), so we'd probably want to make that change. But it would be good if we could find out why your example still isn't capturing trace at the start of the address range.
Are you able to run the Python tool csscan.py from the CSAL repo? If you could run
python csscan.py --status 0x500DC000
immediately after starting tracedemo, that will hopefully list out how the ETM is configured.
Al
For the sake of testing I put the _cs_set(d, CS_ETMCR, CS_ETMCR_ETMEN); before _cs_etm_disable_programming(d);
This results in the access sequence: ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000C60 ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000C60 ** csaccess: 500DD000: write 000 (off) = 00000860 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
but this did not change the buffer content.
Best regards, Finn _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org