Hi,
sorry for bothering you but I hope this is the right place for my questions, as I am kind of stuck right now. I am an undergrad student and currently experimenting with on-device Coresight Tracing. As a board I use the STM32MP157A-DK1, which has some Coresight devices, especially ETM v3.5 for the two A7 cores (32 Bit) and an ETF as a sink. I’d like to use CSAL for trace capturing and OpenCSD for trace decoding, but I’m facing some issues that I don’t understand. For tracing I use the “tracedemo” application from CSAL. As I want to trace userspace-code, I removed the kernel dump part from cs_util_create_snapshot. Except from this, I left everything unchanged, although I have already played around with some configurations. To avoid problems that may be caused by cpuidle, I pass the kernel parameter nohlt on boot, as suggested here in another thread. I also disabled ASLR. For the board configuration I added this function
```c static int do_registration_stm32(struct cs_devices_t *devices) { enum { A7_0, A7_1 };
cs_device_t funnel, etf, cti, etm, timestamp_gen, tpiu, cscti;
//register the rom tables cs_register_romtable(0x50080000); cs_register_romtable(0x50090000);
//CPU affinities /* ETM */ cs_device_set_affinity(cs_device_register(0x500DC000), A7_0); cs_device_set_affinity(cs_device_register(0x500DD000), A7_1); /* CTIs */ cs_device_set_affinity(cs_device_register(0x500D8000), A7_0); cs_device_set_affinity(cs_device_register(0x500D9000), A7_1);
//register other devices timestamp_gen = cs_device_register(0x50082000);
// funnels funnel = cs_device_get(0x50091000);
cs_atb_register(cs_cpu_get_device(A7_0, CS_DEVCLASS_SOURCE), 0, funnel, 0);
cs_atb_register(cs_cpu_get_device(A7_1, CS_DEVCLASS_SOURCE), 0, funnel, 1);
//get the TPIU tpiu = cs_device_get(0x50093000);
//get the ETF devices->etb = cs_device_get(0x50092000); /* It's ETF, not ETB actually */ cs_atb_register(funnel, 0, devices->etb, 0); cs_atb_register(devices->etb, 0, tpiu, 0);
cscti = cs_device_register(0x50094000);
/* the linux board probe does not set up CPUIDs correctly for stm32 - hardcode here for both linux and BAREMETAL. */ devices->cpu_id[0] = 0xC07; devices->cpu_id[1] = 0xC07;
return 0; } ```
My Test-target application is as simple as this:
```c int main() { int a[20]; for (int i=0; i<10;i++) { a[i] = 1+i; }
for (int i=0; i<13;i++) { a[i] = i; }
return 0; } ```
The objdump of my target program looks like this:
```c 000103a0 <main>: 103a0: b480 push {r7} 103a2: b097 sub sp, #92 ; 0x5c 103a4: af00 add r7, sp, #0 103a6: 2300 movs r3, #0 103a8: 657b str r3, [r7, #84] ; 0x54 103aa: e00b b.n 103c4 <main+0x24> 103ac: 6d7b ldr r3, [r7, #84] ; 0x54 103ae: 1c5a adds r2, r3, #1 103b0: 6d7b ldr r3, [r7, #84] ; 0x54 103b2: 009b lsls r3, r3, #2 103b4: f107 0158 add.w r1, r7, #88 ; 0x58 103b8: 440b add r3, r1 103ba: f843 2c58 str.w r2, [r3, #-88] 103be: 6d7b ldr r3, [r7, #84] ; 0x54 103c0: 3301 adds r3, #1 103c2: 657b str r3, [r7, #84] ; 0x54 103c4: 6d7b ldr r3, [r7, #84] ; 0x54 103c6: 2b09 cmp r3, #9 103c8: ddf0 ble.n 103ac <main+0xc> 103ca: 2300 movs r3, #0 103cc: 653b str r3, [r7, #80] ; 0x50 103ce: e00a b.n 103e6 <main+0x46> 103d0: 6d3b ldr r3, [r7, #80] ; 0x50 103d2: 009b lsls r3, r3, #2 103d4: f107 0258 add.w r2, r7, #88 ; 0x58 103d8: 4413 add r3, r2 103da: 6d3a ldr r2, [r7, #80] ; 0x50 103dc: f843 2c58 str.w r2, [r3, #-88] 103e0: 6d3b ldr r3, [r7, #80] ; 0x50 103e2: 3301 adds r3, #1 103e4: 653b str r3, [r7, #80] ; 0x50 103e6: 6d3b ldr r3, [r7, #80] ; 0x50 103e8: 2b0c cmp r3, #12 103ea: ddf1 ble.n 103d0 <main+0x30> 103ec: 2300 movs r3, #0 103ee: 4618 mov r0, r3 103f0: 375c adds r7, #92 ; 0x5c 103f2: 46bd mov sp, r7 103f4: f85d 7b04 ldr.w r7, [sp], #4 103f8: 4770 bx lr ```
I start the trace capture with the command
./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name STM32
so that I only trace my main function. Then I start my target program and after this I stop the tracing. I try to look at the raw trace with OpenCSD, but I only get the following output:
```c $ ~/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister: CS Decode library testing -----------------------------------------------
** Library Version : 1.3.1
Test Command Line:- /home/finn/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked
Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 bc bc bc b8 bc bc b8 bc Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 16; ID_DATA[0x10]; bc d4 bc bc bc bc bc bc bc bc bc bc ec 94 Idx:16; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 32; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 48 bytes. ```
So the trace stream seems to be not synchronized, but I have no idea why.
I played around with the sync frequency, and set it to something low like 8.
```c cs_device_write(dev, CS_ETMSYNCFR, 8); ```
Then I get some readable trace, but of course the overhead is absurd.
Also the trace only starts from 0x000103a8, while I would expect the first packet to be an i-sync for 0x000103a0, as this is the first address of my filter condition.
```c Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 00 00 00 00 00 80 90 08 Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Idx:6; ID:10; A_SYNC : Alignment Synchronisation. Idx:12; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 16; ID_DATA[0x10]; 09 a9 03 01 00 00 00 00 00 00 80 88 08 09 c5 Idx:13; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103a8; NS; ISA=Thumb2; Idx:21; ID:10; A_SYNC : Alignment Synchronisation. Idx:27; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 32; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 ad 03 01 Idx:28; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:35; ID:10; A_SYNC : Alignment Synchronisation. Idx:41; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 48; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 b3 03 01 00 00 Idx:42; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:49; ID:10; A_SYNC : Alignment Synchronisation. Idx:55; ID:10; P_HDR : Atom P-header.; EEE Idx:56; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 64; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 bb 03 01 00 00 00 00 Idx:62; ID:10; A_SYNC : Alignment Synchronisation. Idx:69; ID:10; P_HDR : Atom P-header.; EEE Idx:70; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 80; ID_DATA[0x10]; 00 00 80 8c 08 09 c3 03 01 00 00 00 00 00 00 Idx:76; ID:10; A_SYNC : Alignment Synchronisation. Idx:83; ID:10; P_HDR : Atom P-header.; EEE Idx:84; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 96; ID_DATA[0x10]; 80 88 08 09 c7 03 01 00 00 00 00 00 00 80 88 Idx:90; ID:10; A_SYNC : Alignment Synchronisation. Idx:97; ID:10; P_HDR : Atom P-header.; EE Idx:98; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:104; ID:10; A_SYNC : Alignment Synchronisation. Idx:110; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 112; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:112; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:118; ID:10; A_SYNC : Alignment Synchronisation. Idx:124; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 128; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb Idx:125; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:132; ID:10; A_SYNC : Alignment Synchronisation. Idx:138; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 144; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 Idx:139; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:147; ID:10; A_SYNC : Alignment Synchronisation. Idx:153; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 160; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 Idx:154; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:161; ID:10; A_SYNC : Alignment Synchronisation. Idx:167; ID:10; P_HDR : Atom P-header.; EE Idx:168; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 176; ID_DATA[0x10]; 00 00 00 00 80 88 08 09 ad 03 01 00 00 00 00 Idx:174; ID:10; A_SYNC : Alignment Synchronisation. Idx:181; ID:10; P_HDR : Atom P-header.; EE Idx:182; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Frame Data; Index 192; ID_DATA[0x10]; 00 00 80 8c 08 09 b3 03 01 00 00 00 00 00 00 Idx:188; ID:10; A_SYNC : Alignment Synchronisation. Idx:195; ID:10; P_HDR : Atom P-header.; EEE Idx:196; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 208; ID_DATA[0x10]; 80 8c 08 09 bb 03 01 00 00 00 00 00 00 80 8c Idx:202; ID:10; A_SYNC : Alignment Synchronisation. Idx:209; ID:10; P_HDR : Atom P-header.; EEE Idx:210; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:216; ID:10; A_SYNC : Alignment Synchronisation. Idx:222; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 224; ID_DATA[0x10]; 08 09 c3 03 01 00 00 00 00 00 00 80 88 08 09 Idx:224; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:230; ID:10; A_SYNC : Alignment Synchronisation. Idx:236; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 240; ID_DATA[0x10]; c7 03 01 00 00 00 00 00 00 80 88 08 09 ad 03 Idx:237; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:244; ID:10; A_SYNC : Alignment Synchronisation. Idx:250; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 256; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 b3 03 01 Idx:251; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:258; ID:10; A_SYNC : Alignment Synchronisation. Idx:264; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 272; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 00 Idx:265; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:273; ID:10; A_SYNC : Alignment Synchronisation. Idx:279; ID:10; P_HDR : Atom P-header.; EEE Idx:280; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 288; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 00 Idx:286; ID:10; A_SYNC : Alignment Synchronisation. Idx:293; ID:10; P_HDR : Atom P-header.; EEE Idx:294; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 304; ID_DATA[0x10]; 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 00 Idx:300; ID:10; A_SYNC : Alignment Synchronisation. Idx:307; ID:10; P_HDR : Atom P-header.; EE Idx:308; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 320; ID_DATA[0x10]; 80 88 08 09 ad 03 01 00 00 00 00 00 00 80 8c Idx:314; ID:10; A_SYNC : Alignment Synchronisation. Idx:321; ID:10; P_HDR : Atom P-header.; EE Idx:322; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:328; ID:10; A_SYNC : Alignment Synchronisation. Idx:334; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 336; ID_DATA[0x10]; 08 09 b3 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:336; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:342; ID:10; A_SYNC : Alignment Synchronisation. Idx:348; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 352; ID_DATA[0x10]; bb 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 Idx:349; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:356; ID:10; A_SYNC : Alignment Synchronisation. Idx:362; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 368; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 Idx:363; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:370; ID:10; A_SYNC : Alignment Synchronisation. Idx:376; ID:10; P_HDR : Atom P-header.; EE Idx:377; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 384; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 b1 03 01 00 00 Idx:384; ID:10; A_SYNC : Alignment Synchronisation. Idx:390; ID:10; P_HDR : Atom P-header.; EEEE Idx:391; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 400; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 b9 03 01 00 00 00 00 Idx:397; ID:10; A_SYNC : Alignment Synchronisation. Idx:405; ID:10; P_HDR : Atom P-header.; EEE Idx:406; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 416; ID_DATA[0x10]; 00 00 80 88 08 09 bf 03 01 00 00 00 00 00 00 Idx:412; ID:10; A_SYNC : Alignment Synchronisation. Idx:419; ID:10; P_HDR : Atom P-header.; EE Idx:420; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Frame Data; Index 432; ID_DATA[0x10]; 80 8c 08 09 c5 03 01 00 00 00 00 00 00 80 8c Idx:426; ID:10; A_SYNC : Alignment Synchronisation. Idx:433; ID:10; P_HDR : Atom P-header.; EEE Idx:434; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:440; ID:10; A_SYNC : Alignment Synchronisation. Idx:446; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 448; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:448; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:454; ID:10; A_SYNC : Alignment Synchronisation. Idx:460; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 464; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb 03 Idx:461; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:468; ID:10; A_SYNC : Alignment Synchronisation. Idx:474; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 480; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 00 Idx:475; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:482; ID:10; A_SYNC : Alignment Synchronisation. Idx:488; ID:10; P_HDR : Atom P-header.; EEE Idx:489; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 496; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 00 Idx:496; ID:10; A_SYNC : Alignment Synchronisation. Idx:502; ID:10; P_HDR : Atom P-header.; EE Idx:503; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 512; ID_DATA[0x10]; 00 00 00 80 90 08 09 b1 03 01 00 00 00 00 Idx:509; ID:10; A_SYNC : Alignment Synchronisation. Idx:516; ID:10; P_HDR : Atom P-header.; EEEE Idx:517; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 528; ID_DATA[0x10]; 00 00 80 8c 08 09 b9 03 01 00 00 00 00 00 00 Idx:523; ID:10; A_SYNC : Alignment Synchronisation. Idx:531; ID:10; P_HDR : Atom P-header.; EEE Idx:532; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 544; ID_DATA[0x10]; 80 88 08 09 bf 03 01 00 00 00 00 00 00 80 8c Idx:538; ID:10; A_SYNC : Alignment Synchronisation. Idx:545; ID:10; P_HDR : Atom P-header.; EE Idx:546; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:552; ID:10; A_SYNC : Alignment Synchronisation. Idx:558; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 560; ID_DATA[0x10]; 08 09 c5 03 01 00 00 00 00 00 00 80 90 08 09 Idx:560; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:566; ID:10; A_SYNC : Alignment Synchronisation. Idx:572; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 576; ID_DATA[0x10]; af 03 01 00 00 00 00 00 00 80 88 08 09 b3 03 Idx:573; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ae; NS; ISA=Thumb2; Idx:580; ID:10; A_SYNC : Alignment Synchronisation. Idx:586; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 592; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 Idx:587; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:594; ID:10; A_SYNC : Alignment Synchronisation. Idx:600; ID:10; P_HDR : Atom P-header.; EEE Idx:601; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 608; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 Idx:608; ID:10; A_SYNC : Alignment Synchronisation. Idx:614; ID:10; P_HDR : Atom P-header.; EEE Idx:615; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 624; ID_DATA[0x10]; 00 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 Idx:621; ID:10; A_SYNC : Alignment Synchronisation. Idx:628; ID:10; P_HDR : Atom P-header.; EE Idx:629; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 640; ID_DATA[0x10]; 00 80 90 08 09 b1 03 01 00 00 00 00 00 00 Idx:635; ID:10; A_SYNC : Alignment Synchronisation. Idx:642; ID:10; P_HDR : Atom P-header.; EEEE Idx:643; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 656; ID_DATA[0x10]; 80 8c 08 09 b9 03 01 00 00 00 00 00 00 80 88 Idx:649; ID:10; A_SYNC : Alignment Synchronisation. Idx:657; ID:10; P_HDR : Atom P-header.; EEE Idx:658; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Idx:664; ID:10; A_SYNC : Alignment Synchronisation. Idx:670; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 672; ID_DATA[0x10]; 08 09 bf 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:672; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:678; ID:10; A_SYNC : Alignment Synchronisation. Idx:684; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 688; ID_DATA[0x10]; c5 03 01 00 c8 00 00 00 00 00 80 08 09 cb 03 Idx:685; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:692; ID:10; P_HDR : Atom P-header.; EEN Idx:693; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 704; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e7 03 01 00 Idx:699; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ca; NS; ISA=Thumb2; Idx:706; ID:10; A_SYNC : Alignment Synchronisation. Idx:712; ID:10; P_HDR : Atom P-header.; EEE Idx:713; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e6; NS; ISA=Thumb2; Frame Data; Index 720; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 d1 03 01 00 00 00 Idx:720; ID:10; A_SYNC : Alignment Synchronisation. Idx:726; ID:10; P_HDR : Atom P-header.; EEE Idx:727; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 736; ID_DATA[0x10]; 00 00 00 80 88 08 09 d5 03 01 00 00 00 00 00 Idx:733; ID:10; A_SYNC : Alignment Synchronisation. Idx:740; ID:10; P_HDR : Atom P-header.; EE Idx:741; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 752; ID_DATA[0x10]; 00 80 8c 08 09 dd 03 01 00 00 00 00 00 00 80 Idx:747; ID:10; A_SYNC : Alignment Synchronisation. Idx:754; ID:10; P_HDR : Atom P-header.; EEE Idx:755; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:761; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 768; ID_DATA[0x10]; 8c 08 09 e5 03 01 00 00 00 00 00 00 80 88 Idx:768; ID:10; P_HDR : Atom P-header.; EEE Idx:769; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:775; ID:10; A_SYNC : Alignment Synchronisation. Idx:781; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 784; ID_DATA[0x10]; 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:784; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:790; ID:10; A_SYNC : Alignment Synchronisation. Idx:796; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 800; ID_DATA[0x10]; d3 03 01 00 00 00 00 00 00 80 90 08 09 dd 03 Idx:797; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:804; ID:10; A_SYNC : Alignment Synchronisation. Idx:810; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 816; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 00 Idx:811; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:818; ID:10; A_SYNC : Alignment Synchronisation. Idx:824; ID:10; P_HDR : Atom P-header.; EEE Idx:825; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 832; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 00 Idx:832; ID:10; A_SYNC : Alignment Synchronisation. Idx:838; ID:10; P_HDR : Atom P-header.; EE Idx:839; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 848; ID_DATA[0x10]; 00 00 00 80 88 08 09 d1 03 01 00 00 00 00 00 Idx:845; ID:10; A_SYNC : Alignment Synchronisation. Idx:852; ID:10; P_HDR : Atom P-header.; EE Idx:853; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 864; ID_DATA[0x10]; 00 80 88 08 09 d5 03 01 00 00 00 00 00 00 80 Idx:859; ID:10; A_SYNC : Alignment Synchronisation. Idx:866; ID:10; P_HDR : Atom P-header.; EE Idx:867; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:873; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 880; ID_DATA[0x10]; 8c 08 09 dd 03 01 00 00 00 00 00 00 80 8c 08 Idx:880; ID:10; P_HDR : Atom P-header.; EEE Idx:881; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:887; ID:10; A_SYNC : Alignment Synchronisation. Idx:893; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 896; ID_DATA[0x10]; 09 e5 03 01 00 00 00 00 00 00 80 88 08 09 e9 Idx:894; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:901; ID:10; A_SYNC : Alignment Synchronisation. Idx:907; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 912; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 d1 03 Idx:908; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:915; ID:10; A_SYNC : Alignment Synchronisation. Idx:921; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 928; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 d5 03 01 00 Idx:922; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:930; ID:10; A_SYNC : Alignment Synchronisation. Idx:936; ID:10; P_HDR : Atom P-header.; EE Idx:937; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 944; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 dd 03 01 00 00 00 Idx:944; ID:10; A_SYNC : Alignment Synchronisation. Idx:950; ID:10; P_HDR : Atom P-header.; EEE Idx:951; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 960; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:957; ID:10; A_SYNC : Alignment Synchronisation. Idx:964; ID:10; P_HDR : Atom P-header.; EEE Idx:965; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 976; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:971; ID:10; A_SYNC : Alignment Synchronisation. Idx:978; ID:10; P_HDR : Atom P-header.; EE Idx:979; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:985; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 992; ID_DATA[0x10]; 8c 08 09 d3 03 01 00 00 00 00 00 00 80 90 08 Idx:992; ID:10; P_HDR : Atom P-header.; EEE Idx:993; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:999; ID:10; A_SYNC : Alignment Synchronisation. Idx:1005; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1008; ID_DATA[0x10]; 09 dd 03 01 00 00 00 00 00 00 80 8c 08 09 e5 Idx:1006; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1013; ID:10; A_SYNC : Alignment Synchronisation. Idx:1019; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1024; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 e9 03 01 Idx:1020; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1027; ID:10; A_SYNC : Alignment Synchronisation. Idx:1033; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1040; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 d3 03 01 00 Idx:1034; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1041; ID:10; A_SYNC : Alignment Synchronisation. Idx:1047; ID:10; P_HDR : Atom P-header.; EEE Idx:1048; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1056; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 dd 03 01 00 00 00 Idx:1056; ID:10; A_SYNC : Alignment Synchronisation. Idx:1062; ID:10; P_HDR : Atom P-header.; EEEE Idx:1063; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1072; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:1069; ID:10; A_SYNC : Alignment Synchronisation. Idx:1076; ID:10; P_HDR : Atom P-header.; EEE Idx:1077; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 1088; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:1083; ID:10; A_SYNC : Alignment Synchronisation. Idx:1090; ID:10; P_HDR : Atom P-header.; EE Idx:1091; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1097; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1104; ID_DATA[0x10]; 88 08 09 d1 03 01 00 00 00 00 00 00 80 88 08 Idx:1104; ID:10; P_HDR : Atom P-header.; EE Idx:1105; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:1111; ID:10; A_SYNC : Alignment Synchronisation. Idx:1117; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1120; ID_DATA[0x10]; 09 d5 03 01 00 00 00 00 00 00 80 8c 08 09 dd Idx:1118; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:1125; ID:10; A_SYNC : Alignment Synchronisation. Idx:1131; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1136; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1132; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1139; ID:10; A_SYNC : Alignment Synchronisation. Idx:1145; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1152; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1146; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1153; ID:10; A_SYNC : Alignment Synchronisation. Idx:1159; ID:10; P_HDR : Atom P-header.; EE Idx:1160; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1168; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 Idx:1166; ID:10; A_SYNC : Alignment Synchronisation. Idx:1173; ID:10; P_HDR : Atom P-header.; EEE Idx:1174; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1184; ID_DATA[0x10]; 00 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1180; ID:10; A_SYNC : Alignment Synchronisation. Idx:1188; ID:10; P_HDR : Atom P-header.; EEEE Idx:1189; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1200; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1195; ID:10; A_SYNC : Alignment Synchronisation. Idx:1202; ID:10; P_HDR : Atom P-header.; EEE Idx:1203; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1209; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1216; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1216; ID:10; P_HDR : Atom P-header.; EE Idx:1217; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1223; ID:10; A_SYNC : Alignment Synchronisation. Idx:1229; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1232; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1230; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1237; ID:10; A_SYNC : Alignment Synchronisation. Idx:1243; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1248; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1244; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1251; ID:10; A_SYNC : Alignment Synchronisation. Idx:1257; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1264; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1258; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1265; ID:10; A_SYNC : Alignment Synchronisation. Idx:1271; ID:10; P_HDR : Atom P-header.; EE Idx:1272; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1280; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1278; ID:10; A_SYNC : Alignment Synchronisation. Idx:1285; ID:10; P_HDR : Atom P-header.; EEE Idx:1286; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1296; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1292; ID:10; A_SYNC : Alignment Synchronisation. Idx:1299; ID:10; P_HDR : Atom P-header.; EEEE Idx:1300; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1312; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1306; ID:10; A_SYNC : Alignment Synchronisation. Idx:1314; ID:10; P_HDR : Atom P-header.; EEE Idx:1315; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1321; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1328; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1328; ID:10; P_HDR : Atom P-header.; EE Idx:1329; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1335; ID:10; A_SYNC : Alignment Synchronisation. Idx:1341; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1344; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1342; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1349; ID:10; A_SYNC : Alignment Synchronisation. Idx:1355; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1360; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1356; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1363; ID:10; A_SYNC : Alignment Synchronisation. Idx:1369; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1376; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1370; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1377; ID:10; A_SYNC : Alignment Synchronisation. Idx:1383; ID:10; P_HDR : Atom P-header.; EE Idx:1384; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1392; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1390; ID:10; A_SYNC : Alignment Synchronisation. Idx:1397; ID:10; P_HDR : Atom P-header.; EEE Idx:1398; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1408; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 00 Idx:1404; ID:10; A_SYNC : Alignment Synchronisation. Idx:1411; ID:10; P_HDR : Atom P-header.; EEEE Idx:1412; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1424; ID_DATA[0x10]; 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1418; ID:10; A_SYNC : Alignment Synchronisation. Idx:1425; ID:10; P_HDR : Atom P-header.; EEE Idx:1426; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1432; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1440; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1440; ID:10; P_HDR : Atom P-header.; EE Idx:1441; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1447; ID:10; A_SYNC : Alignment Synchronisation. Idx:1453; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1456; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1454; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1461; ID:10; A_SYNC : Alignment Synchronisation. Idx:1467; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1472; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1468; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1475; ID:10; A_SYNC : Alignment Synchronisation. Idx:1481; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1488; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 c4 Idx:1482; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1489; ID:10; A_SYNC : Alignment Synchronisation. Idx:1495; ID:10; P_HDR : Atom P-header.; EE Idx:1496; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1502; ID:10; P_HDR : Atom P-header.; EN Frame Data; Index 1504; ID_DATA[0x10]; 00 00 00 00 00 80 08 09 ed 03 01 00 00 00 00 Idx:1504; ID:10; A_SYNC : Alignment Synchronisation. Idx:1510; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ec; NS; ISA=Thumb2; Frame Data; Index 1520; ID_DATA[0x10]; 00 00 80 90 08 09 f5 03 01 00 84 Idx:1516; ID:10; A_SYNC : Alignment Synchronisation. Idx:1523; ID:10; P_HDR : Atom P-header.; EEEE Idx:1524; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103f4; NS; ISA=Thumb2; Idx:1530; ID:10; P_HDR : Atom P-header.; E Frame Data; Index 1530; ID_DATA[0x00]; 00 00 00 Frame Data; Index 1536; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 1552 bytes. ```
As far as I understand the ETM should emit an i-sync packet when the address-range-filter triggers, so the first packet I should see in the trace should be that i-sync packet with the first address of my function. And then I would expect some atoms or other trace.
It should be possible to accurately trace also small portions of code (starting from the instruction that triggers the enabling of the ETM), right?
I would be very happy if you could tell me if I have understood or done something wrong and would be glad about any hints for successfully obtaining and reading traces on my device.
Best regards, Finn
Hi,
In both trace runs you are missing the first ASYNC + ISYNC packet.
If you look at the ISYNCs from your second trace run, you will see they all have the "periodic" reason code. The initial ISYNC would have a "tracing enabled" code.
Both runs have the same initial data: ID_DATA[0x10]; 08 29 a1 03 01 00
This is an ISYNC packet with the address 000103a0, thumb mode, with "tracing enabled" ISYNC reason.
This would suggest a few possibilies: 1) The trace sink is not being enabled before the trace sources, missing the initial ASYNC packet. Due to your filter the ISYNC occurs only when valid trace starts to be generated. 2) the data extraction from the sink is missing a frame of coresight data (16 bytes). Check the ETF memory pointer value to see how much data has been collected. Look at the flow from the extraction from the hardware to the writing of the file to be passed into OpenCSD to see if there is an errors here.
Regards
Mike
On Sat, 18 Jun 2022 at 11:43, finn.burmester@student.uni-luebeck.de wrote:
Hi,
sorry for bothering you but I hope this is the right place for my questions, as I am kind of stuck right now. I am an undergrad student and currently experimenting with on-device Coresight Tracing. As a board I use the STM32MP157A-DK1, which has some Coresight devices, especially ETM v3.5 for the two A7 cores (32 Bit) and an ETF as a sink. I’d like to use CSAL for trace capturing and OpenCSD for trace decoding, but I’m facing some issues that I don’t understand. For tracing I use the “tracedemo” application from CSAL. As I want to trace userspace-code, I removed the kernel dump part from cs_util_create_snapshot. Except from this, I left everything unchanged, although I have already played around with some configurations. To avoid problems that may be caused by cpuidle, I pass the kernel parameter nohlt on boot, as suggested here in another thread. I also disabled ASLR. For the board configuration I added this function
static int do_registration_stm32(struct cs_devices_t *devices) { enum { A7_0, A7_1 }; cs_device_t funnel, etf, cti, etm, timestamp_gen, tpiu, cscti; //register the rom tables cs_register_romtable(0x50080000); cs_register_romtable(0x50090000); //CPU affinities /* ETM */ cs_device_set_affinity(cs_device_register(0x500DC000), A7_0); cs_device_set_affinity(cs_device_register(0x500DD000), A7_1); /* CTIs */ cs_device_set_affinity(cs_device_register(0x500D8000), A7_0); cs_device_set_affinity(cs_device_register(0x500D9000), A7_1); //register other devices timestamp_gen = cs_device_register(0x50082000); // funnels funnel = cs_device_get(0x50091000); cs_atb_register(cs_cpu_get_device(A7_0, CS_DEVCLASS_SOURCE), 0, funnel, 0); cs_atb_register(cs_cpu_get_device(A7_1, CS_DEVCLASS_SOURCE), 0, funnel, 1); //get the TPIU tpiu = cs_device_get(0x50093000); //get the ETF devices->etb = cs_device_get(0x50092000); /* It's ETF, not ETB actually */ cs_atb_register(funnel, 0, devices->etb, 0); cs_atb_register(devices->etb, 0, tpiu, 0); cscti = cs_device_register(0x50094000); /* the linux board probe does not set up CPUIDs correctly for stm32 - hardcode here for both linux and BAREMETAL. */ devices->cpu_id[0] = 0xC07; devices->cpu_id[1] = 0xC07; return 0; }My Test-target application is as simple as this:
int main() { int a[20]; for (int i=0; i<10;i++) { a[i] = 1+i; } for (int i=0; i<13;i++) { a[i] = i; } return 0; }The objdump of my target program looks like this:
000103a0 <main>: 103a0: b480 push {r7} 103a2: b097 sub sp, #92 ; 0x5c 103a4: af00 add r7, sp, #0 103a6: 2300 movs r3, #0 103a8: 657b str r3, [r7, #84] ; 0x54 103aa: e00b b.n 103c4 <main+0x24> 103ac: 6d7b ldr r3, [r7, #84] ; 0x54 103ae: 1c5a adds r2, r3, #1 103b0: 6d7b ldr r3, [r7, #84] ; 0x54 103b2: 009b lsls r3, r3, #2 103b4: f107 0158 add.w r1, r7, #88 ; 0x58 103b8: 440b add r3, r1 103ba: f843 2c58 str.w r2, [r3, #-88] 103be: 6d7b ldr r3, [r7, #84] ; 0x54 103c0: 3301 adds r3, #1 103c2: 657b str r3, [r7, #84] ; 0x54 103c4: 6d7b ldr r3, [r7, #84] ; 0x54 103c6: 2b09 cmp r3, #9 103c8: ddf0 ble.n 103ac <main+0xc> 103ca: 2300 movs r3, #0 103cc: 653b str r3, [r7, #80] ; 0x50 103ce: e00a b.n 103e6 <main+0x46> 103d0: 6d3b ldr r3, [r7, #80] ; 0x50 103d2: 009b lsls r3, r3, #2 103d4: f107 0258 add.w r2, r7, #88 ; 0x58 103d8: 4413 add r3, r2 103da: 6d3a ldr r2, [r7, #80] ; 0x50 103dc: f843 2c58 str.w r2, [r3, #-88] 103e0: 6d3b ldr r3, [r7, #80] ; 0x50 103e2: 3301 adds r3, #1 103e4: 653b str r3, [r7, #80] ; 0x50 103e6: 6d3b ldr r3, [r7, #80] ; 0x50 103e8: 2b0c cmp r3, #12 103ea: ddf1 ble.n 103d0 <main+0x30> 103ec: 2300 movs r3, #0 103ee: 4618 mov r0, r3 103f0: 375c adds r7, #92 ; 0x5c 103f2: 46bd mov sp, r7 103f4: f85d 7b04 ldr.w r7, [sp], #4 103f8: 4770 bx lrI start the trace capture with the command
./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name STM32
so that I only trace my main function. Then I start my target program and after this I stop the tracing. I try to look at the raw trace with OpenCSD, but I only get the following output:
$ ~/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister: CS Decode library testing ----------------------------------------------- ** Library Version : 1.3.1 Test Command Line:- /home/finn/OpenCSD/decoder/tests/bin/builddir/trc_pkt_lister -o_raw_unpacked Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 bc bc bc b8 bc bc b8 bc Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 16; ID_DATA[0x10]; bc d4 bc bc bc bc bc bc bc bc bc bc ec 94 Idx:16; ID:10; NOTSYNC : Trace Stream not synchronised Frame Data; Index 32; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 48 bytes.So the trace stream seems to be not synchronized, but I have no idea why.
I played around with the sync frequency, and set it to something low like 8.
cs_device_write(dev, CS_ETMSYNCFR, 8);Then I get some readable trace, but of course the overhead is absurd.
Also the trace only starts from 0x000103a8, while I would expect the first packet to be an i-sync for 0x000103a0, as this is the first address of my filter condition.
Trace Packet Lister : reading snapshot from path ./ Using ETB_0 as trace source Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x10 Trace Packet Lister : Protocol printer ETMV3 on Trace ID 0x11 Frame Data; Index 0; ID_DATA[0x10]; 08 29 a1 03 01 00 00 00 00 00 00 80 90 08 Idx:0; ID:10; NOTSYNC : Trace Stream not synchronised Idx:5; ID:10; NOTSYNC : Trace Stream not synchronised Idx:6; ID:10; A_SYNC : Alignment Synchronisation. Idx:12; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 16; ID_DATA[0x10]; 09 a9 03 01 00 00 00 00 00 00 80 88 08 09 c5 Idx:13; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103a8; NS; ISA=Thumb2; Idx:21; ID:10; A_SYNC : Alignment Synchronisation. Idx:27; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 32; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 ad 03 01 Idx:28; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:35; ID:10; A_SYNC : Alignment Synchronisation. Idx:41; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 48; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 b3 03 01 00 00 Idx:42; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:49; ID:10; A_SYNC : Alignment Synchronisation. Idx:55; ID:10; P_HDR : Atom P-header.; EEE Idx:56; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 64; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 bb 03 01 00 00 00 00 Idx:62; ID:10; A_SYNC : Alignment Synchronisation. Idx:69; ID:10; P_HDR : Atom P-header.; EEE Idx:70; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 80; ID_DATA[0x10]; 00 00 80 8c 08 09 c3 03 01 00 00 00 00 00 00 Idx:76; ID:10; A_SYNC : Alignment Synchronisation. Idx:83; ID:10; P_HDR : Atom P-header.; EEE Idx:84; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 96; ID_DATA[0x10]; 80 88 08 09 c7 03 01 00 00 00 00 00 00 80 88 Idx:90; ID:10; A_SYNC : Alignment Synchronisation. Idx:97; ID:10; P_HDR : Atom P-header.; EE Idx:98; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:104; ID:10; A_SYNC : Alignment Synchronisation. Idx:110; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 112; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:112; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:118; ID:10; A_SYNC : Alignment Synchronisation. Idx:124; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 128; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb Idx:125; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:132; ID:10; A_SYNC : Alignment Synchronisation. Idx:138; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 144; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 Idx:139; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:147; ID:10; A_SYNC : Alignment Synchronisation. Idx:153; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 160; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 Idx:154; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:161; ID:10; A_SYNC : Alignment Synchronisation. Idx:167; ID:10; P_HDR : Atom P-header.; EE Idx:168; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 176; ID_DATA[0x10]; 00 00 00 00 80 88 08 09 ad 03 01 00 00 00 00 Idx:174; ID:10; A_SYNC : Alignment Synchronisation. Idx:181; ID:10; P_HDR : Atom P-header.; EE Idx:182; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Frame Data; Index 192; ID_DATA[0x10]; 00 00 80 8c 08 09 b3 03 01 00 00 00 00 00 00 Idx:188; ID:10; A_SYNC : Alignment Synchronisation. Idx:195; ID:10; P_HDR : Atom P-header.; EEE Idx:196; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Frame Data; Index 208; ID_DATA[0x10]; 80 8c 08 09 bb 03 01 00 00 00 00 00 00 80 8c Idx:202; ID:10; A_SYNC : Alignment Synchronisation. Idx:209; ID:10; P_HDR : Atom P-header.; EEE Idx:210; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:216; ID:10; A_SYNC : Alignment Synchronisation. Idx:222; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 224; ID_DATA[0x10]; 08 09 c3 03 01 00 00 00 00 00 00 80 88 08 09 Idx:224; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:230; ID:10; A_SYNC : Alignment Synchronisation. Idx:236; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 240; ID_DATA[0x10]; c7 03 01 00 00 00 00 00 00 80 88 08 09 ad 03 Idx:237; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Idx:244; ID:10; A_SYNC : Alignment Synchronisation. Idx:250; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 256; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 b3 03 01 Idx:251; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:258; ID:10; A_SYNC : Alignment Synchronisation. Idx:264; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 272; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 00 Idx:265; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:273; ID:10; A_SYNC : Alignment Synchronisation. Idx:279; ID:10; P_HDR : Atom P-header.; EEE Idx:280; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 288; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 00 Idx:286; ID:10; A_SYNC : Alignment Synchronisation. Idx:293; ID:10; P_HDR : Atom P-header.; EEE Idx:294; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 304; ID_DATA[0x10]; 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 00 Idx:300; ID:10; A_SYNC : Alignment Synchronisation. Idx:307; ID:10; P_HDR : Atom P-header.; EE Idx:308; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 320; ID_DATA[0x10]; 80 88 08 09 ad 03 01 00 00 00 00 00 00 80 8c Idx:314; ID:10; A_SYNC : Alignment Synchronisation. Idx:321; ID:10; P_HDR : Atom P-header.; EE Idx:322; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:328; ID:10; A_SYNC : Alignment Synchronisation. Idx:334; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 336; ID_DATA[0x10]; 08 09 b3 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:336; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:342; ID:10; A_SYNC : Alignment Synchronisation. Idx:348; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 352; ID_DATA[0x10]; bb 03 01 00 00 00 00 00 00 80 8c 08 09 c3 03 Idx:349; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:356; ID:10; A_SYNC : Alignment Synchronisation. Idx:362; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 368; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 c7 03 01 00 Idx:363; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Idx:370; ID:10; A_SYNC : Alignment Synchronisation. Idx:376; ID:10; P_HDR : Atom P-header.; EE Idx:377; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 384; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 b1 03 01 00 00 Idx:384; ID:10; A_SYNC : Alignment Synchronisation. Idx:390; ID:10; P_HDR : Atom P-header.; EEEE Idx:391; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 400; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 b9 03 01 00 00 00 00 Idx:397; ID:10; A_SYNC : Alignment Synchronisation. Idx:405; ID:10; P_HDR : Atom P-header.; EEE Idx:406; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 416; ID_DATA[0x10]; 00 00 80 88 08 09 bf 03 01 00 00 00 00 00 00 Idx:412; ID:10; A_SYNC : Alignment Synchronisation. Idx:419; ID:10; P_HDR : Atom P-header.; EE Idx:420; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Frame Data; Index 432; ID_DATA[0x10]; 80 8c 08 09 c5 03 01 00 00 00 00 00 00 80 8c Idx:426; ID:10; A_SYNC : Alignment Synchronisation. Idx:433; ID:10; P_HDR : Atom P-header.; EEE Idx:434; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:440; ID:10; A_SYNC : Alignment Synchronisation. Idx:446; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 448; ID_DATA[0x10]; 08 09 ad 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:448; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ac; NS; ISA=Thumb2; Idx:454; ID:10; A_SYNC : Alignment Synchronisation. Idx:460; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 464; ID_DATA[0x10]; b3 03 01 00 00 00 00 00 00 80 8c 08 09 bb 03 Idx:461; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:468; ID:10; A_SYNC : Alignment Synchronisation. Idx:474; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 480; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 c3 03 01 00 Idx:475; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Idx:482; ID:10; A_SYNC : Alignment Synchronisation. Idx:488; ID:10; P_HDR : Atom P-header.; EEE Idx:489; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 496; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 c7 03 01 00 00 00 Idx:496; ID:10; A_SYNC : Alignment Synchronisation. Idx:502; ID:10; P_HDR : Atom P-header.; EE Idx:503; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 512; ID_DATA[0x10]; 00 00 00 80 90 08 09 b1 03 01 00 00 00 00 Idx:509; ID:10; A_SYNC : Alignment Synchronisation. Idx:516; ID:10; P_HDR : Atom P-header.; EEEE Idx:517; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 528; ID_DATA[0x10]; 00 00 80 8c 08 09 b9 03 01 00 00 00 00 00 00 Idx:523; ID:10; A_SYNC : Alignment Synchronisation. Idx:531; ID:10; P_HDR : Atom P-header.; EEE Idx:532; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Frame Data; Index 544; ID_DATA[0x10]; 80 88 08 09 bf 03 01 00 00 00 00 00 00 80 8c Idx:538; ID:10; A_SYNC : Alignment Synchronisation. Idx:545; ID:10; P_HDR : Atom P-header.; EE Idx:546; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:552; ID:10; A_SYNC : Alignment Synchronisation. Idx:558; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 560; ID_DATA[0x10]; 08 09 c5 03 01 00 00 00 00 00 00 80 90 08 09 Idx:560; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:566; ID:10; A_SYNC : Alignment Synchronisation. Idx:572; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 576; ID_DATA[0x10]; af 03 01 00 00 00 00 00 00 80 88 08 09 b3 03 Idx:573; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ae; NS; ISA=Thumb2; Idx:580; ID:10; A_SYNC : Alignment Synchronisation. Idx:586; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 592; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 bb 03 01 00 Idx:587; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b2; NS; ISA=Thumb2; Idx:594; ID:10; A_SYNC : Alignment Synchronisation. Idx:600; ID:10; P_HDR : Atom P-header.; EEE Idx:601; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ba; NS; ISA=Thumb2; Frame Data; Index 608; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 c3 03 01 00 00 00 Idx:608; ID:10; A_SYNC : Alignment Synchronisation. Idx:614; ID:10; P_HDR : Atom P-header.; EEE Idx:615; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c2; NS; ISA=Thumb2; Frame Data; Index 624; ID_DATA[0x10]; 00 00 00 80 88 08 09 c7 03 01 00 00 00 00 00 Idx:621; ID:10; A_SYNC : Alignment Synchronisation. Idx:628; ID:10; P_HDR : Atom P-header.; EE Idx:629; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c6; NS; ISA=Thumb2; Frame Data; Index 640; ID_DATA[0x10]; 00 80 90 08 09 b1 03 01 00 00 00 00 00 00 Idx:635; ID:10; A_SYNC : Alignment Synchronisation. Idx:642; ID:10; P_HDR : Atom P-header.; EEEE Idx:643; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b0; NS; ISA=Thumb2; Frame Data; Index 656; ID_DATA[0x10]; 80 8c 08 09 b9 03 01 00 00 00 00 00 00 80 88 Idx:649; ID:10; A_SYNC : Alignment Synchronisation. Idx:657; ID:10; P_HDR : Atom P-header.; EEE Idx:658; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103b8; NS; ISA=Thumb2; Idx:664; ID:10; A_SYNC : Alignment Synchronisation. Idx:670; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 672; ID_DATA[0x10]; 08 09 bf 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:672; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103be; NS; ISA=Thumb2; Idx:678; ID:10; A_SYNC : Alignment Synchronisation. Idx:684; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 688; ID_DATA[0x10]; c5 03 01 00 c8 00 00 00 00 00 80 08 09 cb 03 Idx:685; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103c4; NS; ISA=Thumb2; Idx:692; ID:10; P_HDR : Atom P-header.; EEN Idx:693; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 704; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e7 03 01 00 Idx:699; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ca; NS; ISA=Thumb2; Idx:706; ID:10; A_SYNC : Alignment Synchronisation. Idx:712; ID:10; P_HDR : Atom P-header.; EEE Idx:713; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e6; NS; ISA=Thumb2; Frame Data; Index 720; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 d1 03 01 00 00 00 Idx:720; ID:10; A_SYNC : Alignment Synchronisation. Idx:726; ID:10; P_HDR : Atom P-header.; EEE Idx:727; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 736; ID_DATA[0x10]; 00 00 00 80 88 08 09 d5 03 01 00 00 00 00 00 Idx:733; ID:10; A_SYNC : Alignment Synchronisation. Idx:740; ID:10; P_HDR : Atom P-header.; EE Idx:741; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 752; ID_DATA[0x10]; 00 80 8c 08 09 dd 03 01 00 00 00 00 00 00 80 Idx:747; ID:10; A_SYNC : Alignment Synchronisation. Idx:754; ID:10; P_HDR : Atom P-header.; EEE Idx:755; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:761; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 768; ID_DATA[0x10]; 8c 08 09 e5 03 01 00 00 00 00 00 00 80 88 Idx:768; ID:10; P_HDR : Atom P-header.; EEE Idx:769; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:775; ID:10; A_SYNC : Alignment Synchronisation. Idx:781; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 784; ID_DATA[0x10]; 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 09 Idx:784; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:790; ID:10; A_SYNC : Alignment Synchronisation. Idx:796; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 800; ID_DATA[0x10]; d3 03 01 00 00 00 00 00 00 80 90 08 09 dd 03 Idx:797; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:804; ID:10; A_SYNC : Alignment Synchronisation. Idx:810; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 816; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 00 Idx:811; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:818; ID:10; A_SYNC : Alignment Synchronisation. Idx:824; ID:10; P_HDR : Atom P-header.; EEE Idx:825; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 832; ID_DATA[0x10]; 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 00 Idx:832; ID:10; A_SYNC : Alignment Synchronisation. Idx:838; ID:10; P_HDR : Atom P-header.; EE Idx:839; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 848; ID_DATA[0x10]; 00 00 00 80 88 08 09 d1 03 01 00 00 00 00 00 Idx:845; ID:10; A_SYNC : Alignment Synchronisation. Idx:852; ID:10; P_HDR : Atom P-header.; EE Idx:853; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Frame Data; Index 864; ID_DATA[0x10]; 00 80 88 08 09 d5 03 01 00 00 00 00 00 00 80 Idx:859; ID:10; A_SYNC : Alignment Synchronisation. Idx:866; ID:10; P_HDR : Atom P-header.; EE Idx:867; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:873; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 880; ID_DATA[0x10]; 8c 08 09 dd 03 01 00 00 00 00 00 00 80 8c 08 Idx:880; ID:10; P_HDR : Atom P-header.; EEE Idx:881; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:887; ID:10; A_SYNC : Alignment Synchronisation. Idx:893; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 896; ID_DATA[0x10]; 09 e5 03 01 00 00 00 00 00 00 80 88 08 09 e9 Idx:894; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:901; ID:10; A_SYNC : Alignment Synchronisation. Idx:907; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 912; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 d1 03 Idx:908; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:915; ID:10; A_SYNC : Alignment Synchronisation. Idx:921; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 928; ID_DATA[0x10]; 01 00 00 00 00 00 00 80 88 08 09 d5 03 01 00 Idx:922; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:930; ID:10; A_SYNC : Alignment Synchronisation. Idx:936; ID:10; P_HDR : Atom P-header.; EE Idx:937; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Frame Data; Index 944; ID_DATA[0x10]; 00 00 00 00 00 80 8c 08 09 dd 03 01 00 00 00 Idx:944; ID:10; A_SYNC : Alignment Synchronisation. Idx:950; ID:10; P_HDR : Atom P-header.; EEE Idx:951; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 960; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:957; ID:10; A_SYNC : Alignment Synchronisation. Idx:964; ID:10; P_HDR : Atom P-header.; EEE Idx:965; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 976; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:971; ID:10; A_SYNC : Alignment Synchronisation. Idx:978; ID:10; P_HDR : Atom P-header.; EE Idx:979; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:985; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 992; ID_DATA[0x10]; 8c 08 09 d3 03 01 00 00 00 00 00 00 80 90 08 Idx:992; ID:10; P_HDR : Atom P-header.; EEE Idx:993; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:999; ID:10; A_SYNC : Alignment Synchronisation. Idx:1005; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1008; ID_DATA[0x10]; 09 dd 03 01 00 00 00 00 00 00 80 8c 08 09 e5 Idx:1006; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1013; ID:10; A_SYNC : Alignment Synchronisation. Idx:1019; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1024; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 88 08 09 e9 03 01 Idx:1020; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1027; ID:10; A_SYNC : Alignment Synchronisation. Idx:1033; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1040; ID_DATA[0x10]; 00 00 00 00 00 00 80 8c 08 09 d3 03 01 00 Idx:1034; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1041; ID:10; A_SYNC : Alignment Synchronisation. Idx:1047; ID:10; P_HDR : Atom P-header.; EEE Idx:1048; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1056; ID_DATA[0x10]; 00 00 00 00 00 80 90 08 09 dd 03 01 00 00 00 Idx:1056; ID:10; A_SYNC : Alignment Synchronisation. Idx:1062; ID:10; P_HDR : Atom P-header.; EEEE Idx:1063; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1072; ID_DATA[0x10]; 00 00 00 80 8c 08 09 e5 03 01 00 00 00 00 00 Idx:1069; ID:10; A_SYNC : Alignment Synchronisation. Idx:1076; ID:10; P_HDR : Atom P-header.; EEE Idx:1077; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Frame Data; Index 1088; ID_DATA[0x10]; 00 80 88 08 09 e9 03 01 00 00 00 00 00 00 80 Idx:1083; ID:10; A_SYNC : Alignment Synchronisation. Idx:1090; ID:10; P_HDR : Atom P-header.; EE Idx:1091; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1097; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1104; ID_DATA[0x10]; 88 08 09 d1 03 01 00 00 00 00 00 00 80 88 08 Idx:1104; ID:10; P_HDR : Atom P-header.; EE Idx:1105; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d0; NS; ISA=Thumb2; Idx:1111; ID:10; A_SYNC : Alignment Synchronisation. Idx:1117; ID:10; P_HDR : Atom P-header.; EE Frame Data; Index 1120; ID_DATA[0x10]; 09 d5 03 01 00 00 00 00 00 00 80 8c 08 09 dd Idx:1118; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d4; NS; ISA=Thumb2; Idx:1125; ID:10; A_SYNC : Alignment Synchronisation. Idx:1131; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1136; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1132; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1139; ID:10; A_SYNC : Alignment Synchronisation. Idx:1145; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1152; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1146; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1153; ID:10; A_SYNC : Alignment Synchronisation. Idx:1159; ID:10; P_HDR : Atom P-header.; EE Idx:1160; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1168; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 Idx:1166; ID:10; A_SYNC : Alignment Synchronisation. Idx:1173; ID:10; P_HDR : Atom P-header.; EEE Idx:1174; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1184; ID_DATA[0x10]; 00 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1180; ID:10; A_SYNC : Alignment Synchronisation. Idx:1188; ID:10; P_HDR : Atom P-header.; EEEE Idx:1189; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1200; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1195; ID:10; A_SYNC : Alignment Synchronisation. Idx:1202; ID:10; P_HDR : Atom P-header.; EEE Idx:1203; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1209; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1216; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1216; ID:10; P_HDR : Atom P-header.; EE Idx:1217; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1223; ID:10; A_SYNC : Alignment Synchronisation. Idx:1229; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1232; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1230; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1237; ID:10; A_SYNC : Alignment Synchronisation. Idx:1243; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1248; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1244; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1251; ID:10; A_SYNC : Alignment Synchronisation. Idx:1257; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1264; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1258; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1265; ID:10; A_SYNC : Alignment Synchronisation. Idx:1271; ID:10; P_HDR : Atom P-header.; EE Idx:1272; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1280; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1278; ID:10; A_SYNC : Alignment Synchronisation. Idx:1285; ID:10; P_HDR : Atom P-header.; EEE Idx:1286; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1296; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 Idx:1292; ID:10; A_SYNC : Alignment Synchronisation. Idx:1299; ID:10; P_HDR : Atom P-header.; EEEE Idx:1300; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1312; ID_DATA[0x10]; 00 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1306; ID:10; A_SYNC : Alignment Synchronisation. Idx:1314; ID:10; P_HDR : Atom P-header.; EEE Idx:1315; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1321; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1328; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1328; ID:10; P_HDR : Atom P-header.; EE Idx:1329; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1335; ID:10; A_SYNC : Alignment Synchronisation. Idx:1341; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1344; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1342; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1349; ID:10; A_SYNC : Alignment Synchronisation. Idx:1355; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1360; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1356; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1363; ID:10; A_SYNC : Alignment Synchronisation. Idx:1369; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1376; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 00 Idx:1370; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1377; ID:10; A_SYNC : Alignment Synchronisation. Idx:1383; ID:10; P_HDR : Atom P-header.; EE Idx:1384; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Frame Data; Index 1392; ID_DATA[0x10]; 00 00 00 00 80 8c 08 09 d3 03 01 00 00 00 00 Idx:1390; ID:10; A_SYNC : Alignment Synchronisation. Idx:1397; ID:10; P_HDR : Atom P-header.; EEE Idx:1398; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Frame Data; Index 1408; ID_DATA[0x10]; 00 00 80 90 08 09 dd 03 01 00 00 00 00 00 00 Idx:1404; ID:10; A_SYNC : Alignment Synchronisation. Idx:1411; ID:10; P_HDR : Atom P-header.; EEEE Idx:1412; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Frame Data; Index 1424; ID_DATA[0x10]; 80 8c 08 09 e5 03 01 00 00 00 00 00 00 80 Idx:1418; ID:10; A_SYNC : Alignment Synchronisation. Idx:1425; ID:10; P_HDR : Atom P-header.; EEE Idx:1426; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1432; ID:10; A_SYNC : Alignment Synchronisation. Frame Data; Index 1440; ID_DATA[0x10]; 88 08 09 e9 03 01 00 00 00 00 00 00 80 8c 08 Idx:1440; ID:10; P_HDR : Atom P-header.; EE Idx:1441; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1447; ID:10; A_SYNC : Alignment Synchronisation. Idx:1453; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1456; ID_DATA[0x10]; 09 d3 03 01 00 00 00 00 00 00 80 90 08 09 dd Idx:1454; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103d2; NS; ISA=Thumb2; Idx:1461; ID:10; A_SYNC : Alignment Synchronisation. Idx:1467; ID:10; P_HDR : Atom P-header.; EEEE Frame Data; Index 1472; ID_DATA[0x10]; 03 01 00 00 00 00 00 00 80 8c 08 09 e5 03 01 Idx:1468; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103dc; NS; ISA=Thumb2; Idx:1475; ID:10; A_SYNC : Alignment Synchronisation. Idx:1481; ID:10; P_HDR : Atom P-header.; EEE Frame Data; Index 1488; ID_DATA[0x10]; 00 00 00 00 00 00 80 88 08 09 e9 03 01 00 c4 Idx:1482; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e4; NS; ISA=Thumb2; Idx:1489; ID:10; A_SYNC : Alignment Synchronisation. Idx:1495; ID:10; P_HDR : Atom P-header.; EE Idx:1496; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103e8; NS; ISA=Thumb2; Idx:1502; ID:10; P_HDR : Atom P-header.; EN Frame Data; Index 1504; ID_DATA[0x10]; 00 00 00 00 00 80 08 09 ed 03 01 00 00 00 00 Idx:1504; ID:10; A_SYNC : Alignment Synchronisation. Idx:1510; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103ec; NS; ISA=Thumb2; Frame Data; Index 1520; ID_DATA[0x10]; 00 00 80 90 08 09 f5 03 01 00 84 Idx:1516; ID:10; A_SYNC : Alignment Synchronisation. Idx:1523; ID:10; P_HDR : Atom P-header.; EEEE Idx:1524; ID:10; I_SYNC : Instruction Packet synchronisation.; (Periodic); Addr=0x000103f4; NS; ISA=Thumb2; Idx:1530; ID:10; P_HDR : Atom P-header.; E Frame Data; Index 1530; ID_DATA[0x00]; 00 00 00 Frame Data; Index 1536; ID_DATA[0x00]; 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ID:10 END OF TRACE DATA ID:11 END OF TRACE DATA Trace Packet Lister : Trace buffer done, processed 1552 bytes.As far as I understand the ETM should emit an i-sync packet when the address-range-filter triggers, so the first packet I should see in the trace should be that i-sync packet with the first address of my function. And then I would expect some atoms or other trace.
It should be possible to accurately trace also small portions of code (starting from the instruction that triggers the enabling of the ETM), right?
I would be very happy if you could tell me if I have understood or done something wrong and would be glad about any hints for successfully obtaining and reading traces on my device.
Best regards, Finn _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Hi Mike,
thank you very much for your quick answer and your suggestions. From comparing the first trace bytes with the documentation of ETM packet types I had already assumed that this should be a trace-enable-i-sync-packet at the beginning, but I wasn’t sure.
I tried some debugging around your suggestions, but unfortunately I had no success. For your first suggestion:
I am not sure if I have understood you correctly, but from the code it looks like the ETF is enabled before the ETMs (I did not modify this in the tracedemo)
```c static int do_configure_trace(const struct board *board) { int i, r;
printf("CSDEMO: Configuring trace...\n"); /* Ensure TPIU isn't generating back-pressure */ cs_disable_tpiu(); /* While programming, ensure we are not collecting trace */ cs_sink_disable(devices.etb); if (devices.itm_etb != NULL) { cs_sink_disable(devices.itm_etb); } for (i = 0; i < board->n_cpu; ++i) { printf ("CSDEMO: Configuring trace source id for CPU #%d ETM/PTM...\n", i); devices.ptm[i] = cs_cpu_get_device(i, CS_DEVCLASS_SOURCE); if (devices.ptm[i] == CS_ERRDESC) { fprintf(stderr, "** Failed to get trace source for CPU #%d\n", i); return -1; } if (cs_set_trace_source_id(devices.ptm[i], 0x10 + i) < 0) { return -1; } if (do_init_etm(devices.ptm[i]) < 0) { return -1; } } if (itm) { cs_set_trace_source_id(devices.itm, 0x20); } cs_checkpoint();
for (i = 0; i < board->n_cpu; ++i) { if (CS_ETMVERSION_MAJOR(cs_etm_get_version(devices.ptm[i])) >= CS_ETMVERSION_ETMv4) r = do_config_etmv4(i); else r = do_config_etmv3_ptm(i); if (r != 0) return r; }
printf("CSDEMO: Enabling trace...\n"); if (cs_sink_enable(devices.etb) != 0) { printf ("CSDEMO: Could not enable trace buffer - not running demo\n"); return -1; } if (devices.itm_etb != NULL) { if (cs_sink_enable(devices.itm_etb) != 0) { printf("CSDEMO: Could not enable ITM trace buffer\n"); } }
for (i = 0; i < board->n_cpu; ++i) { if (trace_timestamps) cs_trace_enable_timestamps(devices.ptm[i], 1); if (trace_cycle_accurate) cs_trace_enable_cycle_accurate(devices.ptm[i], 1); cs_trace_enable(devices.ptm[i]); } ```
I played around with positioning the enabling of the ETM earlier in the code, but this did not change anything.
About your second suggestion: This is the CSAL Output when reading the trace buffer:
```c CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/ ```
So the Readpointer has the value 0 and Writepointer is at 0x30 I set the readpointer manually to 0xFFFF to see what data is there before what is output, but this does not look interesting either.
```c read 08844988, read ptr now 00001ff0 read 15be9408, read ptr now 00001ff0 read 88c4bcc0, read ptr now 00001ff0 read 44a84a9a, read ptr now 00000000 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020 ```
So I assume the data extraction works correctly, as the a-sync packet is already missing at the extraction of the trace from memory. My Full CSAL Output with debugging enabled looks like this:
CSAL Log
```c root@stm32mp1:~/csal_new/bin/arm/rel# ./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name ST M32 Trace filtering active. CoreSight demonstrator ** Currently affine CPUs: #0 #1 ** csaccess: Registering ROM table at 50080000 ** csaccess: Scanning ROM table at 50080000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50082000 50082000: type=13 O TIMESTAMP ** csaccess: Registering device or ROM table at 50083000 50083000: 1.1 914 00000EA0 00/0F type= 9 - SINK PORT [SWO] ** csaccess: Registering device or ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ff7000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500A0000 500A0000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 64-bit, 128 masters] ** csaccess: Registering device or ROM table at 500D0000 500D0000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D1000 500D1000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D2000 500D2000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D3000 500D3000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D8000 500D8000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500D9000 500D9000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500DC000 500DC000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering device or ROM table at 500DD000 500DD000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI CSREG: Registration complete. CSDEMO: Configuring trace... ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50092000: write 018 (CS_ETB_RAM_WR_PTR) = 00000000 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: 50092000: write 304 (off) = 00001003 ** csaccess: 50092000: write 020 (CS_ETB_CTRL) = 00000001 CSDEMO: Configuring trace source id for CPU #0 ETM/PTM... ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 200 (CS_ETMTRACEIDR) = 00000010 CSDEMO: Initialising ETM/PTM ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DC000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DC000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 CSDEMO: Configuring trace source id for CPU #1 ETM/PTM... ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 200 (CS_ETMTRACEIDR) = 00000011 CSDEMO: Initialising ETM/PTM ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DD000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DD000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSDEMO: Enabling trace... ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DD000: write 000 (off) = 00000860 CSDEMO: CTI settings.... CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CTI at 500D9000 (cpu #1) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 500D8000 (cpu #0) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CSDEMO: Configured and enabled trace. CSDEMO: Trace configured dumping config with No ITM CSUTIL: Created trace configuration export files CSDEMO: trace buffer contents: 0 bytes [press RETURN to stop tracing or q/Q to quit] CSDEMO: Disable trace... ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DC000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000302 ** csaccess: funnel inputs now 00000302 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DD000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000300 ** csaccess: funnel inputs now 00000300 ** csaccess: 50092000: bit 00C.00000004 set after 0 iterations CSDEMO: trace buffer contents: 48 bytes ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00000364 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00000DEC enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 3 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=000016BD enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/arm/rel# ```
Thanks for your input so far, I would be happy about any other suggestions, as I am really out of ideas.
Best regards, Finn
This sequence starts the ETM tracing by clearing the programming bit:
** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations
This is now changing the ETMEN bit after the run has started. Why? No programming should occur with the programming bit at 0. Does the ETMEN signal have any use on the platform you are using?
** csaccess: 500DC000: write 000 (off) = 00000860
On Mon, 20 Jun 2022 at 20:34, finn.burmester@student.uni-luebeck.de wrote:
Hi Mike,
thank you very much for your quick answer and your suggestions.
From comparing the first trace bytes with the documentation of ETM packet types I had already assumed that this should be a trace-enable-i-sync-packet at the beginning, but I wasn’t sure.
I tried some debugging around your suggestions, but unfortunately I had no success. For your first suggestion:
I am not sure if I have understood you correctly, but from the code it looks like the ETF is enabled before the ETMs (I did not modify this in the tracedemo)
static int do_configure_trace(const struct board *board) { int i, r; printf("CSDEMO: Configuring trace...\n"); /* Ensure TPIU isn't generating back-pressure */ cs_disable_tpiu(); /* While programming, ensure we are not collecting trace */ cs_sink_disable(devices.etb); if (devices.itm_etb != NULL) { cs_sink_disable(devices.itm_etb); } for (i = 0; i < board->n_cpu; ++i) { printf ("CSDEMO: Configuring trace source id for CPU #%d ETM/PTM...\n", i); devices.ptm[i] = cs_cpu_get_device(i, CS_DEVCLASS_SOURCE); if (devices.ptm[i] == CS_ERRDESC) { fprintf(stderr, "** Failed to get trace source for CPU #%d\n", i); return -1; } if (cs_set_trace_source_id(devices.ptm[i], 0x10 + i) < 0) { return -1; } if (do_init_etm(devices.ptm[i]) < 0) { return -1; } } if (itm) { cs_set_trace_source_id(devices.itm, 0x20); } cs_checkpoint(); for (i = 0; i < board->n_cpu; ++i) { if (CS_ETMVERSION_MAJOR(cs_etm_get_version(devices.ptm[i])) >= CS_ETMVERSION_ETMv4) r = do_config_etmv4(i); else r = do_config_etmv3_ptm(i); if (r != 0) return r; } printf("CSDEMO: Enabling trace...\n"); if (cs_sink_enable(devices.etb) != 0) { printf ("CSDEMO: Could not enable trace buffer - not running demo\n"); return -1; } if (devices.itm_etb != NULL) { if (cs_sink_enable(devices.itm_etb) != 0) { printf("CSDEMO: Could not enable ITM trace buffer\n"); } } for (i = 0; i < board->n_cpu; ++i) { if (trace_timestamps) cs_trace_enable_timestamps(devices.ptm[i], 1); if (trace_cycle_accurate) cs_trace_enable_cycle_accurate(devices.ptm[i], 1); cs_trace_enable(devices.ptm[i]); }I played around with positioning the enabling of the ETM earlier in the code, but this did not change anything.
About your second suggestion: This is the CSAL Output when reading the trace buffer:
CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/So the Readpointer has the value 0 and Writepointer is at 0x30 I set the readpointer manually to 0xFFFF to see what data is there before what is output, but this does not look interesting either.
read 08844988, read ptr now 00001ff0 read 15be9408, read ptr now 00001ff0 read 88c4bcc0, read ptr now 00001ff0 read 44a84a9a, read ptr now 00000000 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020So I assume the data extraction works correctly, as the a-sync packet is already missing at the extraction of the trace from memory. My Full CSAL Output with debugging enabled looks like this:
CSAL Log
root@stm32mp1:~/csal_new/bin/arm/rel# ./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name ST M32 Trace filtering active. CoreSight demonstrator ** Currently affine CPUs: #0 #1 ** csaccess: Registering ROM table at 50080000 ** csaccess: Scanning ROM table at 50080000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50082000 50082000: type=13 O TIMESTAMP ** csaccess: Registering device or ROM table at 50083000 50083000: 1.1 914 00000EA0 00/0F type= 9 - SINK PORT [SWO] ** csaccess: Registering device or ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ff7000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500A0000 500A0000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 64-bit, 128 masters] ** csaccess: Registering device or ROM table at 500D0000 500D0000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D1000 500D1000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D2000 500D2000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D3000 500D3000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D8000 500D8000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500D9000 500D9000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500DC000 500DC000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering device or ROM table at 500DD000 500DD000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI CSREG: Registration complete. CSDEMO: Configuring trace... ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50092000: write 018 (CS_ETB_RAM_WR_PTR) = 00000000 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: 50092000: write 304 (off) = 00001003 ** csaccess: 50092000: write 020 (CS_ETB_CTRL) = 00000001 CSDEMO: Configuring trace source id for CPU #0 ETM/PTM... ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 200 (CS_ETMTRACEIDR) = 00000010 CSDEMO: Initialising ETM/PTM ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DC000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DC000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 CSDEMO: Configuring trace source id for CPU #1 ETM/PTM... ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 200 (CS_ETMTRACEIDR) = 00000011 CSDEMO: Initialising ETM/PTM ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DD000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DD000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSDEMO: Enabling trace... ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DD000: write 000 (off) = 00000860 CSDEMO: CTI settings.... CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CTI at 500D9000 (cpu #1) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 500D8000 (cpu #0) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CSDEMO: Configured and enabled trace. CSDEMO: Trace configured dumping config with No ITM CSUTIL: Created trace configuration export files CSDEMO: trace buffer contents: 0 bytes [press RETURN to stop tracing or q/Q to quit] CSDEMO: Disable trace... ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DC000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000302 ** csaccess: funnel inputs now 00000302 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DD000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000300 ** csaccess: funnel inputs now 00000300 ** csaccess: 50092000: bit 00C.00000004 set after 0 iterations CSDEMO: trace buffer contents: 48 bytes ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00000364 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00000DEC enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 3 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=000016BD enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/arm/rel#Thanks for your input so far, I would be happy about any other suggestions, as I am really out of ideas.
Best regards, Finn _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org
Hi, it is actually the code in the function cs_trace_enable() in cs_trace_source.c from CSAL that does this, so I assumed that this was correct. https://github.com/ARM-software/CSAL/blob/790f714544b2329d657619d7cc0f063c3c...
The Coresight documentation says, about the ETMEN bit: This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM so I assume it should be set. Also I noticed, that there is no trace output to the buffer when I remove the line that sets it, so I think it has to be enabled.
For the sake of testing I put the _cs_set(d, CS_ETMCR, CS_ETMCR_ETMEN); before _cs_etm_disable_programming(d);
This results in the access sequence: ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000C60 ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000C60 ** csaccess: 500DD000: write 000 (off) = 00000860 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
but this did not change the buffer content.
Best regards, Finn
it is actually the code in the function cs_trace_enable() in cs_trace_source.c from CSAL that does this, so I assumed that this was correct. https://github.com/ARM- software/CSAL/blob/790f714544b2329d657619d7cc0f063c3c9e5e78/source/cs _trace_source.c#L136
The Coresight documentation says, about the ETMEN bit: This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM so I assume it should be set. Also I noticed, that there is no trace output to the buffer when I remove the line that sets it, so I think it has to be enabled.
We added the setting of ETMEN in 2013. I recollect we did that because we had a platform where we weren't getting trace until we set it. The ETM architecture says "you must not use the ETMEN signal to gate the ETM clock or any other functionality required for basic operation. The ETMEN signal can be used to control functionality that is only required for off-chip tracing..." But it's possible some designs do use ETMEN to gate on-chip functionality.
As Mike says, it would be more correct to set ETMEN while programming is still enabled (as you've tried), so we'd probably want to make that change. But it would be good if we could find out why your example still isn't capturing trace at the start of the address range.
Are you able to run the Python tool csscan.py from the CSAL repo? If you could run
python csscan.py --status 0x500DC000
immediately after starting tracedemo, that will hopefully list out how the ETM is configured.
Al
For the sake of testing I put the _cs_set(d, CS_ETMCR, CS_ETMCR_ETMEN); before _cs_etm_disable_programming(d);
This results in the access sequence: ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000C60 ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000C60 ** csaccess: 500DD000: write 000 (off) = 00000860 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations control register of etm is 00000860
but this did not change the buffer content.
Best regards, Finn _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org
Hi Al,
unfortunately I cannot use the csscan tool on my device, as it seems to use a compiler for getting the syscalls, which I do not have on my platform. Is there any other way to get the configuration?
unfortunately I cannot use the csscan tool on my device, as it seems to use a compiler for getting the syscalls, which I do not have on my platform. Is there any other way to get the configuration?
It's using the C preprocessor to extract some syscall numbers from system headers. You probably need to patch iommap.py and find the line "[SYS_mmap, SYS_munmap] = ..." and put in the numbers directly. On my system this would be "[SYS_mmap, SYS_munmap] = [222,215]", but numbers on your system may vary. You might find them in /usr/include/asm/unistd.h or /usr/include/asm-generic/unistd.h under something like __NR_mmap or __NR3264_mmap. Or, if you've got 'strace' you could trace some commands and find them that way.
I'll look to see if there's any way to make iommap.py get these without relying on the C preprocessor.
Al
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Thank you very much for your tips, especially strace was very helpful. I actually had already tried to patch [SYS_mmap, SYS_munmap] like you said but I always got a python error that I could make no sense of. strace showed me that the syscall for mmap was performed, but the offset parameter was wrong. So I now have [SYS_mmap, SYS_munmap] = [192,91] I also had to add the line "offset = int(offset/4096)" because mmap2 seems to want the offset in 4096 byte units.
So the csscan tool works now, but I don't know if the output is of any use.
After starting the trace I get: @0x500dc000 0x23b 0x956 r0.0 <unknown part> ETM <no arch> - claimed:0x1
If I force it to be detected as ETM (by setting condition in line 1120 to TRUE) I get: @0x500dc000 0x23b 0x956 r0.0 <unknown part> ETM <no arch> devid=0x0 pdsr=0x00000001 etmid1=0x410cf250 ETMv3.5 claimed:0x1
When I pass the address of my rom table (without running the tracing), I get this output: @0x50080000 0x020 0x500 r2.0 ROM table @0x50082000 0x23b 0x101 r1.0 <unknown part> CoreSight timestamp generator disabled frequency: 0Hz time: 0 time: 0 measured frequency: 0MHz 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 @0x50083000 0x23b 0x914 r2.0 <unknown part> port <no arch> - @0x50090000 0x020 0x001 r0.0 ROM table @0x50091000 0x23b 0x908 r3.0 CS Funnel funnel <no arch> in-ports:5 ports enabled: 00000 hold time: 3 @0x50092000 0x23b 0x961 r1.0 CS TMC fifo <no arch> TMC:ETF size:8192 memwidth:128 mode: circular buffer flush control: formatting format-triggers stop-on-flush status: TMCready FtEmpty state: Disabled @0x50093000 0x23b 0x912 r5.0 CS TPIU port <no arch> TPIU @0x50094000 0x23b 0x906 r5.0 CS CTI CTI <no arch> channels:4 triggers:8 CTI disabled channel gate: 1111 trigger inputs: 00000010 latched: 00000000 trigger outputs: 00000000 channel inputs: 0000 channel outputs: 0000 @0x500a0000 0x23b 0x963 r1.0 CS STM-500 STM Arm STM rev1 ports:65536 @0x500d0000 0x23b 0xc07 r5.0 <unknown part> core-debug <no arch> - @0x500d1000 0x23b 0x9a7 r5.0 <unknown part> PMU (core) <no arch> - @0x500d2000 0x23b 0xc07 r5.0 <unknown part> core-debug <no arch> - @0x500d3000 0x23b 0x9a7 r5.0 <unknown part> PMU (core) <no arch> - @0x500d8000 0x23b 0x906 r4.0 CS CTI CTI <no arch> channels:4 triggers:8 CTI disabled channel gate: 1111 trigger inputs: 00010000 latched: 00000000 trigger outputs: 00000000 channel inputs: 0000 channel outputs: 0000 @0x500d9000 0x23b 0x906 r4.0 CS CTI CTI <no arch> channels:4 triggers:8 CTI disabled channel gate: 1111 trigger inputs: 00010000 latched: 00000000 trigger outputs: 00000000 channel inputs: 0000 channel outputs: 0000 @0x500dc000 0x23b 0x956 r0.0 <unknown part> ETM <no arch> - @0x500dd000 0x23b 0x956 r0.0 <unknown part> ETM <no arch>
Best regards, Finn
unfortunately I cannot use the csscan tool on my device, as it seems to use a compiler for getting the syscalls, which I do not have on my platform. Is there any other way to get the configuration?
It's using the C preprocessor to extract some syscall numbers from system headers. You probably need to patch iommap.py and find the line "[SYS_mmap, SYS_munmap] = ..." and put in the numbers directly. On my system this would be "[SYS_mmap, SYS_munmap] = [222,215]", but numbers on your system may vary. You might find them in /usr/include/asm/unistd.h or /usr/include/asm-generic/unistd.h under something like __NR_mmap or __NR3264_mmap. Or, if you've got 'strace' you could trace some commands and find them that way.
I'll look to see if there's any way to make iommap.py get these without relying on the C preprocessor.
iommap.py is now fixed to call libc.mmap - the direct syscall turned out to be unnecessary. csscan.py also has some tweaks to show older ETMs.
Looking at your trace data, the first frame starts by indicating trace stream 0x10, and then the address packet immediately follows. That suggests it's the first frame that the formatter has seen. If there were earlier frames (that you might be missing because of an ETF readout problem) the indicator would likely have been in those.
So it would appear the formatter never saw the A-sync. Are you able to double-check the order of enabling, and check that the buffer is enabled first, then the funnels, then the ETM last, so that when the ETM puts out its initial A-sync, it's not going to get lost? It's supposed to work like that already, but possibly it's gone wrong.
Al
Al
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I think I have double-checked everything, but still no A-sync. I tried different orders of enabling and configuring the tracing components, but nothing seems to change. 1. First I enable the sink (ETF) 2. Then the Funnel ports are activated 3. ETM source id is set. This uses the function cs_set_trace_source_id() which calls _cs_unlock(d), so this should lead to the ETM emitting an a-sync packet, which does not happen. 4. Then the configuration of the ETM is set 5. Finally, cs_trace_enable is called, which clears the programming bit, which should also lead to an a-sync packet.
My quick&dirty workaround so far is to manually insert an a-sync packet at the beginning of cstrace.bin . That leads to a decodable trace that seems to be correct. Does this have any disadvantages?
Hi,
On Tue, 28 Jun 2022 at 09:36, finn.burmester@student.uni-luebeck.de wrote:
I think I have double-checked everything, but still no A-sync. I tried different orders of enabling and configuring the tracing components, but nothing seems to change.
- First I enable the sink (ETF)
- Then the Funnel ports are activated
- ETM source id is set. This uses the function cs_set_trace_source_id() which calls _cs_unlock(d), so this should lead to the ETM emitting an a-sync packet, which does not happen.
No - cs_unlock only enables access to the coresight device registers . This will not cause any trace to be emitted.
- Then the configuration of the ETM is set
- Finally, cs_trace_enable is called, which clears the programming bit, which should also lead to an a-sync packet.
Enabling trace is where the first ASYNC should appear.
My quick&dirty workaround so far is to manually insert an a-sync packet at the beginning of cstrace.bin . That leads to a decodable trace that seems to be correct. Does this have any disadvantages?
This will fail is the trace wraps in the buffer. There would then be no guarantee that the earliest trace is actually synchronised. I this case you must allow the decoder to look for the first ASYNC packet. It is advisable to set the periodic sync to less than your buffer size.
Regards
Mike
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On Tue, 28 Jun 2022 at 09:36, finn.burmester@student.uni-luebeck.de wrote:
I think I have double-checked everything, but still no A-sync. I tried different orders of enabling and configuring the tracing components,
but nothing seems to change.
- First I enable the sink (ETF)
- Then the Funnel ports are activated 3. ETM source id is set. This
uses the function cs_set_trace_source_id() which calls _cs_unlock(d), so this
should lead to the ETM emitting an a-sync packet, which does not happen.
No - cs_unlock only enables access to the coresight device registers . This will not cause any trace to be emitted.
- Then the configuration of the ETM is set 5. Finally,
cs_trace_enable is called, which clears the programming bit, which should also
lead to an a-sync packet.
Enabling trace is where the first ASYNC should appear.
... assuming the ETM isn't already enabled. cs_trace_enable() doesn't specifically check for that.
Is there any possibility the ETM is still enabled from a previous time, so that your programming is being ignored (but you don't notice since the programming is correct from the previous time)? Then when you think you're re-enabling it, nothing happens.
Try calling cs_trace_disable() on the ETM immediately before enable().
Al
My quick&dirty workaround so far is to manually insert an a-sync packet at the
beginning of cstrace.bin . That leads to a decodable trace that seems to be correct. Does this have any disadvantages?
This will fail is the trace wraps in the buffer. There would then be no guarantee that the earliest trace is actually synchronised. I this case you must allow the decoder to look for the first ASYNC packet. It is advisable to set the periodic sync to less than your buffer size.
Regards
Mike
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-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org
Hi,
What I tried: 1. Reboot the board and start tracing immediately after the reboot. -> I get a trace, but no async 2. cs_trace_disable immediately before cs_trace_enable -> Now I get no trace anymore 3. cs_trace_disable before the configuration -> I get a trace, but no async 4. When I print the ETM Config before the configuration, ETMCR is set to 0x460, so the Programming Bit is set. Also immeditately before enabling it is 0x460. Directly after enabling becomes 0x860, so the ProgBit is cleared and ETMEN is set. So this behaves as expected.
Regards Finn
-
Al Grant -
finn.burmester＠student.uni-luebeck.de -
Mike Leach