Hi Jeremy,
As Mathieu is away, I'll comment on some of the ETM programming issues here.
On Fri, 2 Aug 2019 at 03:30, Jeremy Ng ngyzj95@gmail.com wrote:
Hi Mathieu,
I will like to ask how I might be able to configure the options in trcconfig driver file, found in /sys/bus/coresight/devices/*.etm/mgmt/ .
For example, the trcidr0 denotes that tssize = 64bits (which indicates that timestamps are supported), retstack, cc, bb are also supported.
However, my trcconfig file shows that none of the options are activated.
trcconfig is maintained as RO from sysfs as it is programmed according to options selected in the driver, particularly the mode parameter. 'mode' selects trace features according to the bits set in the value. These mode selections are interpreted by the driver to program up one or more registers in the hardware.
The mode bits are defined in the coresight-etm4x.h file - though it would be useful to document them as well. Some relevant bits are shown below:-
ETM_MODE_EXCLUDE BIT(0) - sets include(0) / exclude(1) for the current address range. ETM_MODE_BB BIT(4) - sets branch broadcast mode. ETMv4_MODE_CYCACC BIT(5) - sets cycle accurate mode ETMv4_MODE_CTXID BIT(6) - sets context ID trace ETM_MODE_VMID BIT(7) - sets VMID trace ETMv4_MODE_TIMESTAMP BIT(11) - sets timestamps on ETM_MODE_RETURNSTACK BIT(12) - sets return stack on. ETM_MODE_ATB_TRIGGER BIT(19) - insert event triggers into the trace frames. ETM_MODE_VIEWINST_STARTSTOP BIT(27) - start state if using start / stop logic - set to 1 if filtering using address ranges.
In the *.etm driver files, it has the following files in it that I thought might have been linked to trcconfig, or at least be related to activating some of the options that are currently activated: 1. bb_ctrl (obviously bb) 2. cntr_ctrl 3. cyc_threshold (cc?) 4. event_ts (ts)
The above registers directly access the relevent TRC... registers in the hardware.
I am hoping that help in activating these options can be provided.
On another note, I will also like to ask if there might be example files that I may refer to to using sequencer/resource/events.
In the *.etm file, there are seq_event,seq_idx,seq_reset_event,seq_state/res_ctrl, res_idx/event,event_instren,event_ts,event_vinst in the respective order (seq/res/events).
Examples of programming sequencers and events are given in the spec you mention below. These registers relate directly to the hardware registers in this spec (seq_idx selects the relevant .
I will like to understand how I might use these features to improve my tracing results. As well as understanding the various values I could apply to the mode file.
As quoted in sysfs-bus-coresight-devices-etm4x, What: /sys/bus/coresight/devices/<memory_map>.etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing.
However it does not explain how that file can control various modes. I have tried toying with this files and it went from useful tracing results to just kernel instruction tracing results. After applying 0x0 to the mode again (which was the default value when i start up my device), I am unable to re-obtain useful trace results and had to resort to re-power my device.
This cleared VIEWINST_STARTSTOP - by default on start the driver sets up the logic to trace all addresses by setting up the first address range comparators and other logic to allow trace to be collected as soon as enabled. Hence from power up you can collect trace by simply enabling the ETM. (it may be that this default is not being reflected in the 'mode' value). Clearing VIEWINST_STARTSTOP has a side effect of disabling the tracing when using range comparators.
If you want to clear all the programming simply write a value to the /reset parameter. This will clear all the logic to 0 (and remove the default address range). Alternative set the VIEWINST_STARTSTOP in 'mode'
Lastly, I understand that nr_ss_cmp meant that my etm can only have 1 single-shot comparator during a trace (correct me if I am wrong).
This indicates 1 single shot control register - this can control any and all the comparators on the device. (p 7-381 in the spec).
This explains why when I applied 0x3 to addr_idx and set addr_start value, I am unable to set a value for addr_stop. On the other hand,i have 0x4 nr_addr_cmp. However, I do not understand how I might be able to use the other 2 addr comparator (i.e. when addr_idx = 0, I am able to set addr_start and addr_stop, which took up 2 addr_cmp. How then, might I be able to use the other 2 addr_cmp?)
When the driver sets an address comparator, it internally tags it as "in use" with the type of use. If you then attempt to change the use of this comparator you will see an error. So if you set addr_idx to 0x3 - and set addr_start - this is tagged as in use as a START address and the vissctlr is also set to use this comparator as start /stop logic. If you then attempt to write addr_stop using the same addr_idx value, then you will get an error. You need to use 1 comparator for start and a different one for stop.
Regards
Mike
My apologies for many amateurish questions. I have been looking at the etm documentation (IHI0064F), particularly on comparators, bb, ts, events, resources but unfortunately unable to connect the dots on how I might be able to use them with the coresight drivers.
Yours Sincerely, Jeremy Ng _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight