Hi Chunyan,
CoreSight components that output trace onto the ATB (into a funnel or other interconnect component) will need either an ATCLK or be clocked synchronously to this clock.
This is transparent to the programming and use of STM.
Regards
Mike
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-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf ib.html
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