This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11.
Signed-off-by: James Clark james.clark@arm.com --- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 5 +++-- drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 682819467755..a0cdd2cd978a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -707,10 +707,11 @@ static ssize_t bb_ctrl_store(struct device *dev, * individual range comparators. If include then at least 1 * range must be selected. */ - if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0)) + if ((val & TRCBBCTLR_MODE) && (REG_VAL(val, TRCBBCTLR_RANGE) == 0)) return -EINVAL;
- config->bb_ctrl = val & GENMASK(8, 0); + config->bb_ctrl = val & (TRCBBCTLR_MODE | + (TRCBBCTLR_RANGE_MASK << TRCBBCTLR_RANGE_SHIFT)); return size; } static DEVICE_ATTR_RW(bb_ctrl); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 9d0978540338..4d943faade33 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -254,6 +254,10 @@ #define TRCSSPCICRn_PC_SHIFT 0 #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
+#define TRCBBCTLR_MODE BIT(8) +#define TRCBBCTLR_RANGE_SHIFT 0 +#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions