7 Jun
2019
7 Jun
'19
11:04 a.m.
On 07/06/2019 08:04, Student - Ng Yi Zher Jeremy wrote:
Hi Sir,
Thank you for your prompt reply.
Please CC the coresight mailing list when asking questions.My sincerest apologies for not following the protocols.
> Looking at the documentations for etm4x and tmc (<https://outlook.office.com/mail/inbox/id/AAQkADA5Mzc3ZWFlLWY1MzItNDhiOS1iZmRkLWI2NTE1NWNlM2RlZQAQACr6RgSGfxZKoiPE7yQIcBQ%3D>https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x and https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc respectively), I understand that the special files that I have access to read from registers directly are not writeable. However, in the coresight documentations, What special files are you referring to?I was referring to the filesystem's special files that give us read (and some write) access to the registers (i.e. the files in /sys/bus/coresight/devices)
Register TRCCONFIGR has been set as RO because, from sysfs, there was no use case to make it otherwise. That can be altered if you need to use some of the functionality in that register. Simply get back to me with the one you're looking for and we can discuss how it will be made available.
- I will like to activate DA ,DV and COND. I understand that these 2 bits depend on TRCCONFIGR.INSTP0 while this depends on TRCIDR0.INSTP0. Unfortunately, TRCIDR0.INSTP0 is 0b00 in my case. is there any way to work around this to activate data traces?
Arm v8-A ETM implementations do not support Data trace unfortunately. And the TRCIDR0 is a read only register describing the hardware features.
1) You cannot write anything to it. 2) Even if you managed to write, it will not enable data tracing.
- The reason for wanting to activate data traces is to look at my program instructions and determine, at a hardware level, for any bugs that might have been attributed to hardware bugs.
You may use instruction trace to debug your program, but not the data trace on an armv8-A core.
Cheers Suzuki