Dear Sir,

Sorry for the spam, I forgot to attach the file as discussed earlier.

Yours Sincerely, Jeremy Ng ________________________________ From: Student - Ng Yi Zher Jeremy Sent: 07 June 2019 15:04 To: Mathieu Poirier Cc: Coresight ML Subject: Re: Enquiry on Using sysFS for Coresight on Android

Hi Sir,

Thank you for your prompt reply.

Please CC the coresight mailing list when asking questions. My sincerest apologies for not following the protocols.

Looking at the documentations for etm4x and tmc (https://outlook.office.com/mail/inbox/id/AAQkADA5Mzc3ZWFlLWY1MzItNDhiOS1iZmRkLWI2NTE1NWNlM2RlZQAQACr6RgSGfxZKoiPE7yQIcBQ%3Dhttps://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-dev... and https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-dev... respectively), I understand that the special files that I have access to read from registers directly are not writeable. However, in the coresight documentations,

What special files are you referring to? I was referring to the filesystem's special files that give us read (and some write) access to the registers (i.e. the files in /sys/bus/coresight/devices)

Register TRCCONFIGR has been set as RO because, from sysfs, there was no use case to make it otherwise. That can be altered if you need to use some of the functionality in that register. Simply get back to me with the one you're looking for and we can discuss how it will be made available.

1. I will like to activate DA ,DV and COND. I understand that these 2 bits depend on TRCCONFIGR.INSTP0 while this depends on TRCIDR0.INSTP0. Unfortunately, TRCIDR0.INSTP0 is 0b00 in my case. is there any way to work around this to activate data traces? 2. The reason for wanting to activate data traces is to look at my program instructions and determine, at a hardware level, for any bugs that might have been attributed to hardware bugs. 3. I have attached a sample of the instruction address decoded using ptm2human library. I was also unable to find a walkthrough on how I can use DS-5 to decode coresight binary trace files.

The ETF's MODE register does not need to be configured by users - the framework will place the ETF in the correct mode based on its role in the trace session. If the ETF's "enable_sink" entry is selected, the ETF is used as a sink and will be configured in circular buffer mode. If another sink is selected and the ETF is part of the path from a source to that sink, the framework will configure it in HW FIFO mode.

Thank you very much for this!! Anyway, I will like to expand on this point

1. I was following the tutorial to coresight tracing on https://wiki.linaro.org/WorklingGroups/Kernel/Coresight/traceDecodingWithDS5 (which I no longer have access since this morning) and https://www.kernel.org/doc/Documentation/trace/coresight.txt. 2. When I was following the tutorial with traceDecoding in Linaro website, I tried to follow as much as I can, including changing the code in `sysrq.c`. However, when I trigger the sysrq, I was not able to trigger a trace (i.e. the `rwp` value continues to stay at the same position). In fact, sometimes my `rwp` value does not even change despite enabling the sink and the source.

To put into perspective, this is the following commands that I have run to attempt to repeat what was shown in that tutorial.

# cat /proc/kallsyms | grep sysrq

... ffffff80086415dc t sysrq_handle_showregs ffffff8008641624 t sysrq_handle_show_timers ...

# echo ffffff80086415dc ffffff8008641624 ecc40000.etm/addr_range # echo 1 > ec036000.etf/enable_sink # ​cat ec036000.etf/mgmt/rwp 0x0 # echo 1 > ecc40000.etm/enable_source # cat ec036000.etf/mgmt/rwp 0x0 # cat ec036000.etf/mgmt/sts 0x10 # cat ec036000.etf/mgmt/ctl 0x1 # taskset -p 1 $(echo $$) pid 2502's current affinity mask: ff pid 2502's new affinity mask: 1 # echo p > /proc/sysrq-trigger # cat ec036000.etf/mgmt/rwp <--- the pointer did not move 0x0

​I am unable to understand the reason behind the lack of response from the sinks. There is a different response each time i reboot the device and repeat the steps.

​# echo 1 > ec036000.etf/enable_sink # ​cat ec036000.etf/mgmt/rwp 0x0 # echo 1 > ecc40000.etm/enable_source # cat ec036000.etf/mgmt/rwp 0xae0 # cat ec036000.etf/mgmt/sts 0x1 # cat ec036000.etf/mgmt/ctl 0x1 # cat ec036000.etf/mgmt/rrp 0xae0 # taskset -p 1 $(echo $$) pid 2502's current affinity mask: ff pid 2502's new affinity mask: 1 # echo p > /proc/sysrq-trigger # cat ec036000.etf/mgmt/rwp <--- the pointer did not move 0xae0

​Regardless the attempts, the pointer did not move.

I am particularly interested in the values in my status register. The first time i did the procedure, the sts returns 0x10 --> STS.EMPTY=1. The second time I got 0x1 --> STS.FULL. How could it be full if rwp == rrp when the size of my registers is 0x400 (obtained from # cat ec036000.etf/mgmt/rsz.)

3. Aside from that, I feel very much embarrassed to ask you for assistance for trivial matters such as this. If there are resources out there that dabbles with coresight from sysFS perspective, I will love to read it myself rather than to disturb you. However, I was not able to find any resources in this area that are updated and allow me to systematically understand the causation behind each tweaks I made.

Look forward to hearing your reply!

Yours Sincerely, Jeremy Ng

________________________________ From: Mathieu Poirier mathieu.poirier@linaro.org Sent: 07 June 2019 01:29 To: Student - Ng Yi Zher Jeremy; Coresight ML Subject: Re: Enquiry on Using sysFS for Coresight on Android

Hi Jeremy,

Please CC the coresight mailing list when asking questions.

On Thu, 6 Jun 2019 at 02:55, Student - Ng Yi Zher Jeremy jeremy_ng@mymail.sutd.edu.sg wrote:

Dear Sir,

I have been looking at the documentations for Coresight to understand how I may be able to set parameters and options to tracing units through sysFS.

Looking at the documentations for etm4x and tmc (https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-dev... and https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-dev... respectively), I understand that the special files that I have access to read from registers directly are not writeable. However, in the coresight documentations,

What special files are you referring to?

(https://static.docs.arm.com/ihi0064/f/etm_v4_4_architecture_specification_IH... and http://infocenter.arm.com/help/topic/com.arm.doc.ddi0461b/DDI0461B_tmc_r0p1_... respectively), some of these registers are actually writeable. Particularly, TRCCONFIGR in ETM drivers and MODE register in ETF drivers are RW accessible. However, when I try to write to these addresses directly from /dev/mem (or rather, mmap), I often get bus errors (even for those that claims to be readable).

Register TRCCONFIGR has been set as RO because, from sysfs, there was no use case to make it otherwise. That can be altered if you need to use some of the functionality in that register. Simply get back to me with the one you're looking for and we can discuss how it will be made available.

The ETF's MODE register does not need to be configured by users - the framework will place the ETF in the correct mode based on its role in the trace session. If the ETF's "enable_sink" entry is selected, the ETF is used as a sink and will be configured in circular buffer mode. If another sink is selected and the ETF is part of the path from a source to that sink, the framework will configure it in HW FIFO mode.

I am using Hikey960 device on AOSP Android version R, Linux kernel 4.9. $ uname -a returns Linux localhost 4.9.176-12953-g7c09ed7b46a4-dirty #13 SMP PREEMPT Tue Jun 4 10:16:26 +08 2019 aarch64

Hikey960 have 2 CPUs with 4 processors each: Cortex-A53 and Cortex-A73. Both have ETM4.0 r4 chips installed (this was derived from TRCIDR1, which yields 0x4100f404 when read).

It will be a great help if you can assist me or point me to any link for reference.

I can't guide you to anything specific without a question.

Thanks, Mathieu

I look forward to your reply!

Yours Sincerely, Jeremy

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Dear Sirs,

My apologies for the late reply.

Much thanks for all the assistance and kind explanation!

Yours Sincerely, Jeremy ________________________________ From: Suzuki K Poulose suzuki.poulose@arm.com Sent: 07 June 2019 19:04 To: Student - Ng Yi Zher Jeremy; mathieu.poirier@linaro.org Cc: coresight@lists.linaro.org Subject: Re: Enquiry on Using sysFS for Coresight on Android

On 07/06/2019 08:04, Student - Ng Yi Zher Jeremy wrote:

Hi Sir,

Thank you for your prompt reply.

Please CC the coresight mailing list when asking questions.

My sincerest apologies for not following the protocols.

> Looking at the documentations for etm4x and tmc (<https://outlook.office.com/mail/inbox/id/AAQkADA5Mzc3ZWFlLWY1MzItNDhiOS1iZmRkLWI2NTE1NWNlM2RlZQAQACr6RgSGfxZKoiPE7yQIcBQ%3D>https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
and
https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
respectively), I understand that the special files that I have access to
read from registers directly are not writeable. However, in the coresight
documentations,

What special files are you referring to?

I was referring to the filesystem's special files that give us read (and some write) access to the registers (i.e. the files in /sys/bus/coresight/devices)

Register TRCCONFIGR has been set as RO because, from sysfs, there was
no use case to make it otherwise.  That can be altered if you need to
use some of the functionality in that register.  Simply get back to me
with the one you're looking for and we can discuss how it will be made
available.

1. I will like to activate DA ,DV and COND. I understand that these 2 bits depend on TRCCONFIGR.INSTP0 while this depends on TRCIDR0.INSTP0. Unfortunately, TRCIDR0.INSTP0 is 0b00 in my case. is there any way to work around this to activate data traces?

Arm v8-A ETM implementations do not support Data trace unfortunately. And the TRCIDR0 is a read only register describing the hardware features.

1) You cannot write anything to it. 2) Even if you managed to write, it will not enable data tracing.

2. The reason for wanting to activate data traces is to look at my program instructions and determine, at a hardware level, for any bugs that might have been attributed to hardware bugs.

You may use instruction trace to debug your program, but not the data trace on an armv8-A core.

Cheers Suzuki

The above message may contain confidential and/or proprietary information that is exempt from disclosure under applicable law and is intended for receipt and use solely by the addressee(s) named above. If you are not the intended recipient, you are hereby notified that any use, dissemination, distribution, or copying of this message, or any attachment, is strictly prohibited. If you have received this email in error, please inform the sender immediately by reply e-mail or telephone, reversing the charge if necessary. Please delete the message thereafter. Thank you.