Re: [PATCH v2 4/8] perf/x86: Add barrier after updating bts

On Wed, Jun 02, 2021 at 06:30:03PM +0800, Leo Yan wrote:

Add barrier wmb() to separate the AUX data store and aux_head store.

Signed-off-by: Leo Yan leo.yan@linaro.org

arch/x86/events/intel/bts.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 6320d2cfd9d3..4a015d160bc5 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -209,6 +209,9 @@ static void bts_update(struct bts_ctx *bts) } else { local_set(&buf->data_size, head); }

• /* The WMB separates data store and aux_head store matches. */
• wmb();

Alexander, do we indeed need an MFENCE here? or is the BTS hardware coherent, in which case a compiler barrier would be sufficient.