Hi All,
The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC ETR driver.
Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00
Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length field is implementation defined, the maximum value supported by our chip is 0x7.
We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?
With Regards, Tanmay
The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC ETR driver.
Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00
Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length field is implementation defined, the maximum value supported by our chip is 0x7.
We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?
We could add a new AXI burst size property into the DT/ACPI description of the ETR, and the driver could use that, and fall back to 16 if not supplied.
Another option is to have the system firmware configure the ETR's AXI burst length at boot time (and possibly other system-level configuration) and then set a flag in DT/ACPI to tell the Linux ETR driver not to override it. Do you have the option of configuring the ETR from firmware, or is Linux going to be the first thing that touches it?
Al
With Regards, Tanmay _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
Hi Al,
-----Original Message----- From: Al Grant Al.Grant@arm.com Sent: Thursday, August 5, 2021 5:04 PM To: Tanmay Jagdale tanmay@marvell.com; coresight@lists.linaro.org Cc: Sunil Kovvuri Goutham sgoutham@marvell.com; Linu Cherian lcherian@marvell.com Subject: Query regarding AXI Write Burst Length in ETR driver
External Email
The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC
ETR
driver.
Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00
Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length
field is
implementation defined, the maximum value supported by our chip is 0x7.
We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?
We could add a new AXI burst size property into the DT/ACPI description of the ETR, and the driver could use that, and fall back to 16 if not supplied.
Can we set the default value of AXI burst size to a lower value such that it works for all silicons?
Later, we can introduce a new DT/ACPI parameter for setting the maximum supported burst size since adding new parameters to DT/ACPI would be a longer process.
With Regards, Tanmay
Another option is to have the system firmware configure the ETR's AXI burst length at boot time (and possibly other system-level configuration) and then set a flag in DT/ACPI to tell the Linux ETR driver not to override it. Do you have the option of configuring the ETR from firmware, or is Linux going to be the first thing that touches it?
Al
With Regards, Tanmay _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
-----Original Message----- From: Tanmay Jagdale tanmay@marvell.com Sent: 06 August 2021 15:52 To: Al Grant Al.Grant@arm.com; coresight@lists.linaro.org Cc: Sunil Kovvuri Goutham sgoutham@marvell.com; Linu Cherian lcherian@marvell.com Subject: Query regarding AXI Write Burst Length in ETR driver
Hi Al,
-----Original Message----- From: Al Grant Al.Grant@arm.com Sent: Thursday, August 5, 2021 5:04 PM To: Tanmay Jagdale tanmay@marvell.com; coresight@lists.linaro.org Cc: Sunil Kovvuri Goutham sgoutham@marvell.com; Linu Cherian lcherian@marvell.com Subject: Query regarding AXI Write Burst Length in ETR driver
External Email
The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC
ETR
driver.
Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00
Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length
field is
implementation defined, the maximum value supported by our chip is 0x7.
We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?
We could add a new AXI burst size property into the DT/ACPI description of the ETR, and the driver could use that, and fall back to 16 if not
supplied. Can we set the default value of AXI burst size to a lower value such that it works for all silicons?
16 (0xF) should work for all silicon, as AXI allows burst sizes up to 16. So unless we've missed something, this is an implementation non-compliance and we should not be penalising compliant implementations by reducing the default burst size - the question is how we can enable the upstream kernel to workaround the issue on this chip only, and to me that sounds like it needs something that can be triggered by a setting in DT/ACPI.
Al
Later, we can introduce a new DT/ACPI parameter for setting the maximum supported burst size since adding new parameters to DT/ACPI would be a longer process.
With Regards, Tanmay
Another option is to have the system firmware configure the ETR's AXI burst length at boot time (and possibly other system-level configuration) and then set a flag in DT/ACPI to tell the Linux ETR driver not to override it. Do you have the option of configuring the ETR from firmware, or is Linux going to be the first thing that touches it?
Al
With Regards, Tanmay _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
Hi,
On Fri, 6 Aug 2021 at 17:53, Al Grant Al.Grant@arm.com wrote:
-----Original Message----- From: Tanmay Jagdale tanmay@marvell.com Sent: 06 August 2021 15:52 To: Al Grant Al.Grant@arm.com; coresight@lists.linaro.org Cc: Sunil Kovvuri Goutham sgoutham@marvell.com; Linu Cherian lcherian@marvell.com Subject: Query regarding AXI Write Burst Length in ETR driver
Hi Al,
-----Original Message----- From: Al Grant Al.Grant@arm.com Sent: Thursday, August 5, 2021 5:04 PM To: Tanmay Jagdale tanmay@marvell.com; coresight@lists.linaro.org Cc: Sunil Kovvuri Goutham sgoutham@marvell.com; Linu Cherian lcherian@marvell.com Subject: Query regarding AXI Write Burst Length in ETR driver
External Email
The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC
ETR
driver.
Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00
Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length
field is
implementation defined, the maximum value supported by our chip is 0x7.
We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?
We could add a new AXI burst size property into the DT/ACPI description of the ETR, and the driver could use that, and fall back to 16 if not
supplied. Can we set the default value of AXI burst size to a lower value such that it works for all silicons?
16 (0xF) should work for all silicon, as AXI allows burst sizes up to 16. So unless we've missed something, this is an implementation non-compliance and we should not be penalising compliant implementations by reducing the default burst size - the question is how we can enable the upstream kernel to workaround the issue on this chip only, and to me that sounds like it needs something that can be triggered by a setting in DT/ACPI.
Another possibility would be to introduce an errata workaround in Kconfig for your silicon. There are a number of these already in KConfig for PE issues e.g. CONFIG_ARM64_ERRATUM_826319, and we have introduced CONFIG_ETM4X_IMPDEF_FEATURE for silicon specific variants in the ETMv4 driver.
The latter config compiles in implementation defined workarounds which operate on the basis of matching the AMBA ID for the silicon. This means they will operate only if configured in KConfig and only on silicon where the workaround is needed.
Regards
Mike
Al
Later, we can introduce a new DT/ACPI parameter for setting the maximum supported burst size since adding new parameters to DT/ACPI would be a longer process.
With Regards, Tanmay
Another option is to have the system firmware configure the ETR's AXI burst length at boot time (and possibly other system-level configuration) and then set a flag in DT/ACPI to tell the Linux ETR driver not to override it. Do you have the option of configuring the ETR from firmware, or is Linux going to be the first thing that touches it?
Al
With Regards, Tanmay _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
-
Al Grant -
Mike Leach -
Tanmay Jagdale