Hi Levi,

On Wed, Jul 02, 2025 at 12:10:17PM +0100, Yeoreum Yun wrote:

[...]

...

@@ -579,6 +572,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)

if (!drvdata->paused) rc = etm4_enable_trace_unit(drvdata);

• /*

• * As recommended by section 4.3.7 (Synchronization of register updates)
  

• * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

• * ISB instruction after programming the trace unit registers.
  

• */
  

• isb();

But according to 4.3.7 ("Synchronization when using memory-mapped interface"), doesn't it need to dsb like:

if (csa->iomem) dsb(sy); isb();

Or am I missing something?

Section 4.3.7 suggests using a DSB barrier to ensure that writes have completed in MMIO mode. It also mentions an alternative:

"If the memory is marked as Device-nGnRE or stronger, read back the value of any register in the trace unit. This relies on the peripheral coherence order defined in the Arm architecture."

In the etm4_{enable|disable}_trace_unit() functions, each time the TRCPRGCTLR register is written, the driver polls bits in TRCSTATR. This acts as synchronization using read-after-write (RAW), which is exactly the approach suggested above.

This is why we don't need DSB() anymore.

Thanks, Leo