I want to restrict access to the Coresight registers to the secure world, so the normal world OS can not tamper with the tracing. Is this generally possible, and if yes, how? I already tried to use the address space controller (TZC-400) with the memory-addresses of the registers, but that didn’t work, because it is only for protecting DDR-memory regions, as I later found out.

I guess you have already found the various debug enables like SPIDEN etc., but you want to prevent Non-Secure transactions accessing the debug register space in any way?

Programming the interconnect or something like TZC-400 might be a way to go. When you say TZC-400 can only protect DDR-memory regions, what specific problems are you seeing? Are you designing your own system in FPGA and finding you can't put a TZC-400 in between the CPU and the debug APB? What interconnects are you using?

Al

Best regards

Finn _______________________________________________ CoreSight mailing list -- coresight@lists.linaro.org To unsubscribe send an email to coresight-leave@lists.linaro.org