Linaro-mm-sig

linaro-mm-sig@lists.linaro.org

6 participants
3122 discussions

Re: [Linaro-mm-sig] [PATCH v2 2/4] drm/msm: Avoid mutex in shrinker_count()

by Rob Clark

On Thu, Apr 1, 2021 at 8:34 AM Doug Anderson <dianders(a)chromium.org> wrote: > > Hi, > > On Wed, Mar 31, 2021 at 6:24 PM Rob Clark <robdclark(a)gmail.com> wrote: > > > > @@ -45,6 +30,9 @@ msm_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) > > list_for_each_entry(msm_obj, &priv->inactive_dontneed, mm_list) { > > if (freed >= sc->nr_to_scan) > > break; > > + /* Use trylock, because we cannot block on a obj that > > + * might be trying to acquire mm_lock > > + */ > > nit: I thought the above multi-line commenting style was only for > "net" subsystem? we do use the "net" style a fair bit already.. (OTOH I tend to not really care what checkpatch says) > > if (!msm_gem_trylock(&msm_obj->base)) > > continue; > > if (is_purgeable(msm_obj)) { > > @@ -56,8 +44,11 @@ msm_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) > > > > mutex_unlock(&priv->mm_lock); > > > > - if (freed > 0) > > + if (freed > 0) { > > trace_msm_gem_purge(freed << PAGE_SHIFT); > > + } else { > > + return SHRINK_STOP; > > + } > > It probably doesn't matter, but I wonder if we should still be > returning SHRINK_STOP if we got any trylock failures. It could > possibly be worth returning 0 in that case? On the surface, you'd think that, but there be mm dragons.. we can hit shrinker from the submit path when the obj is locked already and we are trying to allocate backing pages. We don't want to tell vmscan to keep trying, because we'll keep failing to grab that objects lock > > > @@ -75,6 +66,9 @@ vmap_shrink(struct list_head *mm_list) > > unsigned unmapped = 0; > > > > list_for_each_entry(msm_obj, mm_list, mm_list) { > > + /* Use trylock, because we cannot block on a obj that > > + * might be trying to acquire mm_lock > > + */ > > If you end up changing the commenting style above, should also be here. > > At this point this seems fine to land to me. Though I'm not an expert > on every interaction in this code, I've spent enough time starting at > it that I'm comfortable with: > > Reviewed-by: Douglas Anderson <dianders(a)chromium.org> thanks BR, -R

4 years, 7 months

[PATCH v2 0/4] drm/msm: Shrinker (and related) fixes

by Rob Clark

From: Rob Clark <robdclark(a)chromium.org> I've been spending some time looking into how things behave under high memory pressure. The first patch is a random cleanup I noticed along the way. The second improves the situation significantly when we are getting shrinker called from many threads in parallel. And the last two are $debugfs/gem fixes I needed so I could monitor the state of GEM objects (ie. how many are active/purgable/purged) while triggering high memory pressure. We could probably go a bit further with dropping the mm_lock in the shrinker->scan() loop, but this is already a pretty big improvement. The next step is probably actually to add support to unpin/evict inactive objects. (We are part way there since we have already de- coupled the iova lifetime from the pages lifetime, but there are a few sharp corners to work through.) Rob Clark (4): drm/msm: Remove unused freed llist node drm/msm: Avoid mutex in shrinker_count() drm/msm: Fix debugfs deadlock drm/msm: Improved debugfs gem stats drivers/gpu/drm/msm/msm_debugfs.c | 14 ++--- drivers/gpu/drm/msm/msm_drv.c | 4 ++ drivers/gpu/drm/msm/msm_drv.h | 15 ++++-- drivers/gpu/drm/msm/msm_fb.c | 3 +- drivers/gpu/drm/msm/msm_gem.c | 65 ++++++++++++++++++----- drivers/gpu/drm/msm/msm_gem.h | 72 +++++++++++++++++++++++--- drivers/gpu/drm/msm/msm_gem_shrinker.c | 28 ++++------ 7 files changed, 150 insertions(+), 51 deletions(-) -- 2.30.2

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH] drm/amd/amdgpu/gfx_v7_0: Trivial typo fixes

by Alex Deucher

Applied. Thanks! Alex On Thu, Mar 25, 2021 at 5:26 AM Nirmoy <nirmodas(a)amd.com> wrote: > > > Reviewed-by: Nirmoy Das<nirmoy.das(a)amd.com> > > On 3/25/21 9:53 AM, Bhaskar Chowdhury wrote: > > s/acccess/access/ > > s/inferface/interface/ > > s/sequnce/sequence/ .....two different places. > > s/retrive/retrieve/ > > s/sheduling/scheduling/ > > s/independant/independent/ > > s/wether/whether/ ......two different places. > > s/emmit/emit/ > > s/synce/sync/ > > > > > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 22 +++++++++++----------- > > 1 file changed, 11 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > index a368724c3dfc..4502b95ddf6b 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -1877,7 +1877,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) > > mutex_unlock(&adev->srbm_mutex); > > > > /* Initialize all compute VMIDs to have no GDS, GWS, or OA > > - acccess. These should be enabled by FW for target VMIDs. */ > > + access. These should be enabled by FW for target VMIDs. */ > > for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { > > WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); > > WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); > > @@ -2058,7 +2058,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev) > > * @adev: amdgpu_device pointer > > * > > * Set up the number and offset of the CP scratch registers. > > - * NOTE: use of CP scratch registers is a legacy inferface and > > + * NOTE: use of CP scratch registers is a legacy interface and > > * is not used by default on newer asics (r6xx+). On newer asics, > > * memory buffers are used for fences rather than scratch regs. > > */ > > @@ -2172,7 +2172,7 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > > * @seq: sequence number > > * @flags: fence related flags > > * > > - * Emits a fence sequnce number on the gfx ring and flushes > > + * Emits a fence sequence number on the gfx ring and flushes > > * GPU caches. > > */ > > static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, > > @@ -2215,7 +2215,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, > > * @seq: sequence number > > * @flags: fence related flags > > * > > - * Emits a fence sequnce number on the compute ring and flushes > > + * Emits a fence sequence number on the compute ring and flushes > > * GPU caches. > > */ > > static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, > > @@ -2245,14 +2245,14 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, > > * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring > > * > > * @ring: amdgpu_ring structure holding ring information > > - * @job: job to retrive vmid from > > + * @job: job to retrieve vmid from > > * @ib: amdgpu indirect buffer object > > * @flags: options (AMDGPU_HAVE_CTX_SWITCH) > > * > > * Emits an DE (drawing engine) or CE (constant engine) IB > > * on the gfx ring. IBs are usually generated by userspace > > * acceleration drivers and submitted to the kernel for > > - * sheduling on the ring. This function schedules the IB > > + * scheduling on the ring. This function schedules the IB > > * on the gfx ring for execution by the GPU. > > */ > > static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, > > @@ -2402,7 +2402,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) > > > > /* > > * CP. > > - * On CIK, gfx and compute now have independant command processors. > > + * On CIK, gfx and compute now have independent command processors. > > * > > * GFX > > * Gfx consists of a single ring and can process both gfx jobs and > > @@ -2630,7 +2630,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) > > ring->wptr = 0; > > WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); > > > > - /* set the wb address wether it's enabled or not */ > > + /* set the wb address whether it's enabled or not */ > > rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); > > WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); > > WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); > > @@ -2985,7 +2985,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, > > mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; > > mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; > > > > - /* set the wb address wether it's enabled or not */ > > + /* set the wb address whether it's enabled or not */ > > wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); > > mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; > > mqd->cp_hqd_pq_rptr_report_addr_hi = > > @@ -3198,7 +3198,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) > > /** > > * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP > > * > > - * @ring: the ring to emmit the commands to > > + * @ring: the ring to emit the commands to > > * > > * Sync the command pipeline with the PFP. E.g. wait for everything > > * to be completed. > > @@ -3220,7 +3220,7 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) > > amdgpu_ring_write(ring, 4); /* poll interval */ > > > > if (usepfp) { > > - /* synce CE with ME to prevent CE fetch CEIB before context switch done */ > > + /* sync CE with ME to prevent CE fetch CEIB before context switch done */ > > amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); > > amdgpu_ring_write(ring, 0); > > amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); > > -- > > 2.30.1 > > > _______________________________________________ > amd-gfx mailing list > amd-gfx(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx

4 years, 7 months

Re: [Linaro-mm-sig] WARNING: AMDGPU DRM warning in 5.11.9

by Christian König

Hi, Am 25.03.21 um 09:17 schrieb Oleksandr Natalenko: > Hello. > > On Thu, Mar 25, 2021 at 07:57:33AM +0200, Ilkka Prusi wrote: >> On 24.3.2021 16.16, Chris Rankin wrote: >>> Hi, >>> >>> Theee warnings ares not present in my dmesg log from 5.11.8: >>> >>> [ 43.390159] ------------[ cut here ]------------ >>> [ 43.393574] WARNING: CPU: 2 PID: 1268 at >>> drivers/gpu/drm/ttm/ttm_bo.c:517 ttm_bo_release+0x172/0x282 [ttm] >>> [ 43.401940] Modules linked in: nf_nat_ftp nf_conntrack_ftp cfg80211 >> Changing WARN_ON to WARN_ON_ONCE in drivers/gpu/drm/ttm/ttm_bo.c >> ttm_bo_release() reduces the flood of messages into single splat. >> >> This warning appears to come from 57fcd550eb15bce ("drm/ttm: Warn on pinning >> without holding a reference)" and reverting it might be one choice. >> >> >>> There are others, but I am assuming there is a common cause here. >>> >>> Cheers, >>> Chris >>> >> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c >> index a76eb2c14e8c..50b53355b265 100644 >> --- a/drivers/gpu/drm/ttm/ttm_bo.c >> +++ b/drivers/gpu/drm/ttm/ttm_bo.c >> @@ -514,7 +514,7 @@ static void ttm_bo_release(struct kref *kref) >> * shrinkers, now that they are queued for >> * destruction. >> */ >> - if (WARN_ON(bo->pin_count)) { >> + if (WARN_ON_ONCE(bo->pin_count)) { >> bo->pin_count = 0; >> ttm_bo_del_from_lru(bo); >> ttm_bo_add_mem_to_lru(bo, &bo->mem); >> >> >> >> -- >> - Ilkka >> > WARN_ON_ONCE() will just hide the underlying problem. Do we know why > this happens at all? The patch was incorrectly back ported to 5.11 without also porting the driver changes to not trigger this warning back as well. We are probably going to revert it for 5.11.10. Regards, Christian. > > Same for me, BTW, with v5.11.9: > > ``` > [~]> lspci | grep VGA > 0a:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Lexa PRO [Radeon 540/540X/550/550X / RX 540X/550/550X] (rev c7) > > [ 3676.033140] ------------[ cut here ]------------ > [ 3676.033153] WARNING: CPU: 7 PID: 1318 at drivers/gpu/drm/ttm/ttm_bo.c:517 ttm_bo_release+0x375/0x500 [ttm] > … > [ 3676.033340] Hardware name: ASUS System Product Name/Pro WS X570-ACE, BIOS 3302 03/05/2021 > … > [ 3676.033469] Call Trace: > [ 3676.033473] ttm_bo_move_accel_cleanup+0x1ab/0x3a0 [ttm] > [ 3676.033478] amdgpu_bo_move+0x334/0x860 [amdgpu] > [ 3676.033580] ttm_bo_validate+0x1f1/0x2d0 [ttm] > [ 3676.033585] amdgpu_cs_bo_validate+0x9b/0x1c0 [amdgpu] > [ 3676.033665] amdgpu_cs_list_validate+0x115/0x150 [amdgpu] > [ 3676.033743] amdgpu_cs_ioctl+0x873/0x20a0 [amdgpu] > [ 3676.033960] drm_ioctl_kernel+0xb8/0x140 [drm] > [ 3676.033977] drm_ioctl+0x222/0x3c0 [drm] > [ 3676.034071] amdgpu_drm_ioctl+0x49/0x80 [amdgpu] > [ 3676.034145] __x64_sys_ioctl+0x83/0xb0 > [ 3676.034149] do_syscall_64+0x33/0x40 > … > [ 3676.034171] ---[ end trace 66e9865b027112f3 ]--- > ``` > > Thanks. >

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH] i915_vma: Rename vma_lookup to i915_vma_lookup

by Daniel Vetter

On Tue, Mar 23, 2021 at 01:42:21PM +0000, Liam Howlett wrote: > Use i915 prefix to avoid name collision with future vma_lookup() in mm. > > Signed-off-by: Liam R. Howlett <Liam.Howlett(a)Oracle.com> > Reviewed-by: Matthew Wilcox (Oracle) <willy(a)infradead.org> Applied to i915-gem-next branch for 5.13. We have a bit a branch shuffling going on right now so unusal path, it should show up in linux-next through drm-next hopefully this week still. -Daniel > --- > drivers/gpu/drm/i915/i915_vma.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c > index caa9b041616b..ee0028c697f6 100644 > --- a/drivers/gpu/drm/i915/i915_vma.c > +++ b/drivers/gpu/drm/i915/i915_vma.c > @@ -230,7 +230,7 @@ vma_create(struct drm_i915_gem_object *obj, > } > > static struct i915_vma * > -vma_lookup(struct drm_i915_gem_object *obj, > +i915_vma_lookup(struct drm_i915_gem_object *obj, > struct i915_address_space *vm, > const struct i915_ggtt_view *view) > { > @@ -278,7 +278,7 @@ i915_vma_instance(struct drm_i915_gem_object *obj, > GEM_BUG_ON(!atomic_read(&vm->open)); > > spin_lock(&obj->vma.lock); > - vma = vma_lookup(obj, vm, view); > + vma = i915_vma_lookup(obj, vm, view); > spin_unlock(&obj->vma.lock); > > /* vma_create() will resolve the race if another creates the vma */ > -- > 2.30.0 -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH] drm/etnaviv: Remove redundant NULL check

by Christian Gmeiner

Am Di., 23. März 2021 um 03:46 Uhr schrieb Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com>: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c:622:2-8: WARNING: NULL > check before some freeing functions is not needed. > > ./drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c:618:2-8: WARNING: NULL > check before some freeing functions is not needed. > > ./drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c:616:2-8: WARNING: NULL > check before some freeing functions is not needed. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> Reviewed-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH] dma-buf: use wake_up_process() instead of wake_up_state()

by Christian König

Am 19.03.21 um 03:58 schrieb Wang Qing: > Using wake_up_process() is more simpler and friendly, > and it is more convenient for analysis and statistics > > Signed-off-by: Wang Qing <wangqing(a)vivo.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> Should I pick it up or do you want to push it through some other tree than DRM? Thanks, Christian. > --- > drivers/dma-buf/dma-fence.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 7475e09..de51326 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -655,7 +655,7 @@ dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb) > struct default_wait_cb *wait = > container_of(cb, struct default_wait_cb, base); > > - wake_up_state(wait->task, TASK_NORMAL); > + wake_up_process(wait->task); > } > > /**

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH] drm/i915/gt: A typo fix

by Randy Dunlap

On 3/18/21 3:19 AM, Bhaskar Chowdhury wrote: > > s/bariers/barriers/ > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> Acked-by: Randy Dunlap <rdunlap(a)infradead.org> > --- > drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c > index 037b0e3ccbed..25fc7f44fee0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_timeline.c > +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c > @@ -435,7 +435,7 @@ void intel_timeline_exit(struct intel_timeline *tl) > spin_unlock(&timelines->lock); > > /* > - * Since this timeline is idle, all bariers upon which we were waiting > + * Since this timeline is idle, all barriers upon which we were waiting > * must also be complete and so we can discard the last used barriers > * without loss of information. > */ > -- > 2.26.2 > -- ~Randy

4 years, 7 months

Re: [Linaro-mm-sig] [PATCH 3/3] RFC: dma-buf: Add an API for importing and exporting sync files (v5)

by Daniel Vetter

On Wed, Sep 30, 2020 at 11:39:06AM +0200, Michel Dänzer wrote: > On 2020-03-17 10:21 p.m., Jason Ekstrand wrote: > > Explicit synchronization is the future. At least, that seems to be what > > most userspace APIs are agreeing on at this point. However, most of our > > Linux APIs (both userspace and kernel UAPI) are currently built around > > implicit synchronization with dma-buf. While work is ongoing to change > > many of the userspace APIs and protocols to an explicit synchronization > > model, switching over piecemeal is difficult due to the number of > > potential components involved. On the kernel side, many drivers use > > dma-buf including GPU (3D/compute), display, v4l, and others. In > > userspace, we have X11, several Wayland compositors, 3D drivers, compute > > drivers (OpenCL etc.), media encode/decode, and the list goes on. > > > > This patch provides a path forward by allowing userspace to manually > > manage the fences attached to a dma-buf. Alternatively, one can think > > of this as making dma-buf's implicit synchronization simply a carrier > > for an explicit fence. This is accomplished by adding two IOCTLs to > > dma-buf for importing and exporting a sync file to/from the dma-buf. > > This way a userspace component which is uses explicit synchronization, > > such as a Vulkan driver, can manually set the write fence on a buffer > > before handing it off to an implicitly synchronized component such as a > > Wayland compositor or video encoder. In this way, each of the different > > components can be upgraded to an explicit synchronization model one at a > > time as long as the userspace pieces connecting them are aware of it and > > import/export fences at the right times. > > > > There is a potential race condition with this API if userspace is not > > careful. A typical use case for implicit synchronization is to wait for > > the dma-buf to be ready, use it, and then signal it for some other > > component. Because a sync_file cannot be created until it is guaranteed > > to complete in finite time, userspace can only signal the dma-buf after > > it has already submitted the work which uses it to the kernel and has > > received a sync_file back. There is no way to atomically submit a > > wait-use-signal operation. This is not, however, really a problem with > > this API so much as it is a problem with explicit synchronization > > itself. The way this is typically handled is to have very explicit > > ownership transfer points in the API or protocol which ensure that only > > one component is using it at any given time. Both X11 (via the PRESENT > > extension) and Wayland provide such ownership transfer points via > > explicit present and idle messages. > > > > The decision was intentionally made in this patch to make the import and > > export operations IOCTLs on the dma-buf itself rather than as a DRM > > IOCTL. This makes it the import/export operation universal across all > > components which use dma-buf including GPU, display, v4l, and others. > > It also means that a userspace component can do the import/export > > without access to the DRM fd which may be tricky to get in cases where > > the client communicates with DRM via a userspace API such as OpenGL or > > Vulkan. At a future date we may choose to add direct import/export APIs > > to components such as drm_syncobj to avoid allocating a file descriptor > > and going through two ioctls. However, that seems to be something of a > > micro-optimization as import/export operations are likely to happen at a > > rate of a few per frame of rendered or decoded video. > > > > v2 (Jason Ekstrand): > > - Use a wrapper dma_fence_array of all fences including the new one > > when importing an exclusive fence. > > > > v3 (Jason Ekstrand): > > - Lock around setting shared fences as well as exclusive > > - Mark SIGNAL_SYNC_FILE as a read-write ioctl. > > - Initialize ret to 0 in dma_buf_wait_sync_file > > > > v4 (Jason Ekstrand): > > - Use the new dma_resv_get_singleton helper > > > > v5 (Jason Ekstrand): > > - Rename the IOCTLs to import/export rather than wait/signal > > - Drop the WRITE flag and always get/set the exclusive fence > > > > Signed-off-by: Jason Ekstrand <jason(a)jlekstrand.net> > > What's the status of this? DMA_BUF_IOCTL_EXPORT_SYNC_FILE would be useful > for Wayland compositors to wait for client buffers to become ready without > being prone to getting delayed by later HW access to them, so it would be > nice to merge that at least (if DMA_BUF_IOCTL_IMPORT_SYNC_FILE is still > controversial). I think the missing bits are just the usual stuff - igt testcases - userspace using the new ioctls - review of the entire pile I don't think there's any fundamental objections aside from "no one ever pushed this over the finish line". Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 7 months

[PATCH] dma-fence: Document recoverable page fault implications

by Daniel Vetter

Recently there was a fairly long thread about recoreable hardware page faults, how they can deadlock, and what to do about that. While the discussion is still fresh I figured good time to try and document the conclusions a bit. This documentation section explains what's the potential problem, and the remedies we've discussed, roughly ordered from best to worst. v2: Linus -> Linux typoe (Dave) v3: - Make it clear drivers only need to implement one option (Christian) - Make it clearer that implicit sync is out the window with exclusive fences (Christian) - Add the fairly theoretical option of segementing the memory (either statically or through dynamic checks at runtime for which piece of memory is managed how) and explain why it's not a great idea (Felix) References: https://lore.kernel.org/dri-devel/20210107030127.20393-1-Felix.Kuehling@amd… Cc: Dave Airlie <airlied(a)gmail.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)intel.com> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Jerome Glisse <jglisse(a)redhat.com> Cc: Felix Kuehling <felix.kuehling(a)amd.com> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- Documentation/driver-api/dma-buf.rst | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index a2133d69872c..7f37ec30d9fd 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -257,3 +257,79 @@ fences in the kernel. This means: userspace is allowed to use userspace fencing or long running compute workloads. This also means no implicit fencing for shared buffers in these cases. + +Recoverable Hardware Page Faults Implications +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Modern hardware supports recoverable page faults, which has a lot of +implications for DMA fences. + +First, a pending page fault obviously holds up the work that's running on the +accelerator and a memory allocation is usually required to resolve the fault. +But memory allocations are not allowed to gate completion of DMA fences, which +means any workload using recoverable page faults cannot use DMA fences for +synchronization. Synchronization fences controlled by userspace must be used +instead. + +On GPUs this poses a problem, because current desktop compositor protocols on +Linux rely on DMA fences, which means without an entirely new userspace stack +built on top of userspace fences, they cannot benefit from recoverable page +faults. Specifically this means implicit synchronization will not be possible. +The exception is when page faults are only used as migration hints and never to +on-demand fill a memory request. For now this means recoverable page +faults on GPUs are limited to pure compute workloads. + +Furthermore GPUs usually have shared resources between the 3D rendering and +compute side, like compute units or command submission engines. If both a 3D +job with a DMA fence and a compute workload using recoverable page faults are +pending they could deadlock: + +- The 3D workload might need to wait for the compute job to finish and release + hardware resources first. + +- The compute workload might be stuck in a page fault, because the memory + allocation is waiting for the DMA fence of the 3D workload to complete. + +There are a few options to prevent this problem, one of which drivers need to +ensure: + +- Compute workloads can always be preempted, even when a page fault is pending + and not yet repaired. Not all hardware supports this. + +- DMA fence workloads and workloads which need page fault handling have + independent hardware resources to guarantee forward progress. This could be + achieved through e.g. through dedicated engines and minimal compute unit + reservations for DMA fence workloads. + +- The reservation approach could be further refined by only reserving the + hardware resources for DMA fence workloads when they are in-flight. This must + cover the time from when the DMA fence is visible to other threads up to + moment when fence is completed through dma_fence_signal(). + +- As a last resort, if the hardware provides no useful reservation mechanics, + all workloads must be flushed from the GPU when switching between jobs + requiring DMA fences or jobs requiring page fault handling: This means all DMA + fences must complete before a compute job with page fault handling can be + inserted into the scheduler queue. And vice versa, before a DMA fence can be + made visible anywhere in the system, all compute workloads must be preempted + to guarantee all pending GPU page faults are flushed. + +- Only a fairly theoretical option would be to untangle these dependencies when + allocating memory to repair hardware page faults, either through separate + memory blocks or runtime tracking of the full dependency graph of all DMA + fences. This results very wide impact on the kernel, since resolving the page + on the CPU side can itself involve a page fault. It is much more feasible and + robust to limit the impact of handling hardware page faults to the specific + driver. + +Note that workloads that run on independent hardware like copy engines or other +GPUs do not have any impact. This allows us to keep using DMA fences internally +in the kernel even for resolving hardware page faults, e.g. by using copy +engines to clear or copy memory needed to resolve the page fault. + +In some ways this page fault problem is a special case of the `Infinite DMA +Fences` discussions: Infinite fences from compute workloads are allowed to +depend on DMA fences, but not the other way around. And not even the page fault +problem is new, because some other CPU thread in userspace might +hit a page fault which holds up a userspace fence - supporting page faults on +GPUs doesn't anything fundamentally new. -- 2.30.0

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