On 11/07/2025 5:00 pm, Tomeu Vizoso wrote:
On Tue, Jun 24, 2025 at 3:50 PM Robin Murphy robin.murphy@arm.com wrote:
On 2025-06-06 7:28 am, Tomeu Vizoso wrote: [...]
diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h index 10acfe8534f00a7985d40a93f4b2f7f69d43caee..50e46f0516bd1615b5f826c5002a6c0ecbf9aed4 100644 --- a/drivers/accel/rocket/rocket_device.h +++ b/drivers/accel/rocket/rocket_device.h @@ -13,6 +13,8 @@ struct rocket_device { struct drm_device ddev;
struct mutex sched_lock;struct mutex iommu_lock;Just realised I missed this in the last patch, but iommu_lock appears to be completely unnecessary now.
struct rocket_core *cores;[...]
+static void rocket_job_hw_submit(struct rocket_core *core, struct rocket_job *job) +{
struct rocket_task *task;bool task_pp_en = 1;bool task_count = 1;/* GO ! *//* Don't queue the job if a reset is in progress */if (atomic_read(&core->reset.pending))return;task = &job->tasks[job->next_task_idx];job->next_task_idx++;rocket_pc_writel(core, BASE_ADDRESS, 0x1);rocket_cna_writel(core, S_POINTER, 0xe + 0x10000000 * core->index);rocket_core_writel(core, S_POINTER, 0xe + 0x10000000 * core->index);Those really look like bitfield operations rather than actual arithmetic to me.
rocket_pc_writel(core, BASE_ADDRESS, task->regcmd);I don't see how regcmd is created (I guess that's in userspace?), but given that it's explicitly u64 all the way through - and especially since you claim to support 40-bit DMA addresses - it definitely seems suspicious that the upper 32 bits never seem to be consumed anywhere :/
Yeah, but there's no other register for BASE_ADDRESS address in the TRM.
That only reaffirms the question then - if this value is only ever written verbatim to a 32-bit register, why is it 64-bit?
Thanks, Robin.