- linaro-toolchain - lists.linaro.org

[ACTIVITY] 1 - 4 April 2014

by Kugan

- TCWG-413 Spec2006 (5/10) - Analysed 456.hmmer - In the process of opening performance bug reports - Started looking at 453.povray - TCWG-291 CRC (2/10) - Not seeing performance improvement with redundant "and" instruction gone - Analysing with perf to see the reason - LP1301335 (3/10) - SLP vectorizer ICEs for QT5 Webkit for Linaro 4.7 - Doesn’t occur in trunk/4.8/4.7 FSF - Patch proposed for merge request which fixes - I also see some FAIL -> PASS in the regression with this patch - This patch is only relevant for Linaro 4.7 so we cant/don’t need to upstream it (?) == Plan == Continue with Spec2006 and crc

11 years, 5 months

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[Activity] 31 March - 04 Apr 2014

by Venkataramanan Kumar

4 day week 31-Oct local holiday Bug fix (2/10) * Looking at a register allocation issue with ARMv7 hard float issue. (3/10) Tried changing machine description pattern same as trunk in gcc 4.8 branch. Issue does not occur with trunk and reason is arm64 moved to lra. turning off lra bug occurs. Trying to find out if it is easy to fix in reload or wait for LRA backport. PGO - AArch64 (TCWG-179) (3/10) * Native CPU2006 runs on V8 foundation model. SPEC runs -O3 -mcpu=cortex-a57. INT benchmark failures seen with mcf and h264ref. rest benchmarks running. * Tried to use ubuntu saucy core image on V8 foundation model and mount NFS is failing. * Trying to install QEMU user static for aarch64 and use them from chroot environment GLIBC Systemtap (2/10) * Re spined libc systemtap probe patch to glibc. Will newton is testing it in hardware. Meetings (2/10) * Attend 1-1 with Ryan discuss 2014 goal planning. * Attend 1-1 with Maxim discuss PGO work.

11 years, 5 months

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[ACTIVITY] Week 14

by Renato Golin

== Progress == * Kernel (TCWG-417) - Implementing named register global variables (D3261) - Helping Milosz and Vinicius (LLVMLinux) to get a kernel ready - First LLVM-compiled kernel booted on Versatile Express hardware * Background - Reviewing patches, etc. - Apple merged their ARM64 back-end, fiddling bots - Making the new TableGen docs official - Jira farming - Became code owner for the ARM Linux support - LLVM Foundation announced - Trying to run SPEC on AArch64 * Time - CARD-124 6/10 - Others 4/10 == Plan == * Holiday for two and a half weeks * Follow up the named register patch

11 years, 5 months

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[ACTIVITY] 1 - 4 April 2014

by Will Newton

== Progress == * glibc patch review (2/10) * Helping out with aarch64 glibc setjmp/longjmp Systemtap probes testing (1/10) * Investigated and submitted patch for gas ARM alignment issue (3/10) * Committed library and script for malloc logging (1/10, TCWG-423) * Rebased and tidied up malloc microbenchmark (2/10, TCWG-160) * Various small binutils and glibc patches (1/10) == Issues == * None == Plan == * Submit patch for glibc malloc microbenchmark -- Will Newton Toolchain Working Group, Linaro

11 years, 5 months

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pthread_self() alignment when heap grows up

by Michael Hudson-Doyle

Hi all, I've just filed a bug on glibc I'd love you to take a look at: https://sourceware.org/bugzilla/show_bug.cgi?id=16796 Here's the description to save clicking: Hi, There is a test in glibc (tst-tls5) that tests that ((uintptr_t)pthread_self())%16 is zero. But watch this: (t-mwhudson)mwhudson@am1:~$ cat btp.c #include <stdint.h> #include <stdio.h> #include <pthread.h> int main(int argc, char** argv) { uintptr_t p = (uintptr_t)__builtin_thread_pointer(); uintptr_t q = (uintptr_t)pthread_self(); printf("p: %lx %ld\n", p, p%16); printf("q: %lx %ld\n", q, q%16); } (t-mwhudson)mwhudson@am1:~$ gcc -o btp btp.c -lpthread (t-mwhudson)mwhudson@am1:~$ ulimit -s unlimited (t-mwhudson)mwhudson@am1:~$ ./btp p: 2000028d88 8 q: 2000028698 8 (t-mwhudson)mwhudson@am1:~$ ulimit -S -s 8192 (t-mwhudson)mwhudson@am1:~$ ./btp p: 7f7fd086f0 0 q: 7f7fd08000 0 So something is clearly wrong; maybe it's just that the test is too strict, but somehow that seems a bit unlikely. FWIW, this doesn't happen if you don't link with libpthread so maaaaybe it's a bug in something that ends up in libpthread's .init section? Cheers, mwh

11 years, 5 months

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[ACTIVITY] March 24-30

by Maxim Kuvyrkov

== Week of March 24th == - STREAM regression (TCWG-388, 5/10) -- Finished prototype patch. The patch adds modeling of ARM L2 auto-prefetcher hardware to GCC scheduler (the model is very simple as auto-prefetcher is very lightly documented). Half of the patch cleans up and improves GCC scheduler, and the other half implements the auto-prefetcher model. -- While looking into ARM scheduling support noticed that ARM doesn't use multipass lookahead scheduling, which surprised me. Enabled it (multipass scheduling) in my patches. - Looked into lll_timed_wait Glibc/uClibc bug upstream (1/10) -- https://sourceware.org/ml/libc-alpha/2014-03/msg00905.html - Various discussions and reviews (4/10) == Week of March 30th == - STREAM regression (TCWG-388) -- Benchmark patches on SPEC2k and find/confirm best values for tuning parameters: --- dfa_lookahead: should normally be issue_rate-1. --- L2 auto-prefetcher queue depth: new tuning knob. -- Investigate any performance regressions from the patches. - lll_timed_wait Glibc/uClibc bug -- Make sure it is fixed upstream. Possibly backport to Linaro branches. -- Maxim Kuvyrkov www.linaro.org

11 years, 5 months

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[ACTIVITY] Week 13

by Yvan Roux

== Issues == * none == Progress == * Launchpad bugs: o TCWG-422 : ICE in assign_by_spills building linux btrfs module (1/10) - created blueprint for : https://bugs.launchpad.net/gcc-linaro/+bug/1296676 - Reported upstream as : http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60650 - Reduced testcase - Fix committed by Vladimir as rev208876 - still ICE when configured for arm-none-linux-gnueabihf o Backported "Internal compiler error in push_reload during bootstrap stage 2" to GCC 4.7 (1/10) - https://bugs.launchpad.net/gcc-linaro/+bug/1129013 - some testsuite regressions observed. will investigate. * Backports review: (5/10) o reviewed backport for pr60264 and rev202663 o cortex-a53 support backport: - Analysed testsuite regression - 22K Loc patch under review * LRA on AArch32: o TCWG-345 : Analyse performance of LRA for ARM. (1/10) - looked at the perf tool results * Misc: o Various meetings (1/10). o Various support to team members (1/10) o Cbuildv1 baby-sitting (Calxedas nodes have to be restarted after each upgrades !) == Next == - continue cortex-a53 review - continue on backports. - continue on TCWG-345.

11 years, 5 months

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[ACTIVITY] 24 - 28 March 2014

by Omair Javaid

== Progress == * Short Week -- Monday Day Off: Pakistan Day 23rd March public holiday roll over. [2/10] -- Short leave on Thursday [1/10] * Work on gdb testing utility [TCWG-96] [7/10] -- Writing a new gdb testing utility script that automates gdb testing in various configurations and compares testsuite results. -- Support for all kind of native, native-gdbserver and remote-gdbserver gdb configurations has been added. -- Interactive and configuration file based user input mode has been added. -- Testing configurations host alive, ssh possible, board file found and ability to build sources using user defined configure flags has been added. == Plan == * Work on gdb testing utility [TCWG-96]. -- Add support to run native and native-gdbserver test via ssh on remote machines like arm-linux. -- Bug fix and test gdb testing utility by running it various configurations. -- Update wiki page with testing utility and how to use it.

11 years, 5 months

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[Weekly] 24-28 MAR 2014

by Michael Collison

== This week == a53 support - Fixed regression found in arm testing and resubmitted build and merge requests - arrch64 testing passed with no regressions. Testing with a53 support enabled still required Merged 202663 (vectorizer bug) into 4.7 and 4.8 branches. Submitted merge and build requests == Next week == - Test aarch64 with a53 support enabled on qemu64 - Work on bug 60657 - [4.9 Regresssion] ICE: error: insn does not satisfy its constraints == Future ==

11 years, 5 months

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[ACTIVITY] Week 13

by Zhenqiang Chen

== Issues == * None == Progress == * Create prebuilt sysroot based on Linaro eglibc 2014.04 release (https://launchpad.net/linaro-toolchain-binaries/support/01/+download/linaro…) (1/10). * Enable shrink-wrap for apcs. Patch was out for community review. (1/10) * Reinvestigate shrink-wrap enhancement (4/10, TCWG-133) - There was improvement in ira to split_live_ranges_for_shrink_wrap (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10474). But it still can not handle the case in 453.povray. - Investigate to do a simple copy-forward when prepare_shrink_wrap. * Investigate lp:1296942 (pr60663). Patch is sent out for community review. (4/10) * Backporting the fix for pr60264 to Linaro 4..8. == Plans == * Continue on shrink-wrap enhancement. == Planned leaves == * April 7: Qingming holiday.

11 years, 5 months

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[ACTIVITY] 24 - 28 March 2014

by Kugan

== Progress == - TCWG-413 Spec2006 (7/10) - Investigated compiler error for 481.wrf with FSF 4.8.2. Issue is due to aarch64_cm<cmp><mode> pattern (fcmle and fcmlt supports only #0 as third val). This is already fixed in trunk and Linaro 4.8. - Ran profiling to analyse 4.9 regressions. Started looking into P7Vitterbui which is one of the functions that performs badly. - TCWG-291 CRC (3/10) Came up with a patch for improving vrp for test-case. Some c++ test cases are failing in regression testing with this patch. Looking into it. - TCWG-394 / PR60034 Patch committed and card closed. http://gcc.gnu.org/viewcvs?rev=208949&root=gcc&view=rev == Plan == Continue with Spec2006 and crc

11 years, 5 months

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[ACTIVITY] Week 13

by Renato Golin

== Progress == * Android (no card, 10 minutes. ;) - Implemented __builtin___clear_cache in Clang * Kernel (TCWG-417) 6/10 - VLAIS in crypto (last place in kernel) - __builtin__stack_pointer (new builtin) - Discussion in GCC list, named registers might be a better option - Discussion in LLVM list about implementing named registers - Implementing named register variables... - Planning on LAVA testing LLVM kernels with LLVMLinux - __aeabi_memset/cpy/move (both Android and Kernel) will have to be fixed * Libraries (TCWG-125) 2/10 - libc++abi's unwind routines assume (ARM == SjLj) - libc++ doesn't work without them - We'll need to teach it about EHABI (later) * Background 2/10 - Installed ArchLinux on my laptop, took some time to setup - Re-org of LLVM Jira Cards (TCWG-417) - Reviewing some GSoC proposals == Plan == * implement named register variables in LLVM, then Clang * Continue helping LLVMLinux and Milosz to test the LLVM kernel * Time allowing, check CBuild2 for an LLVM build * Two long weeks of holidays...

11 years, 5 months

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[ACTIVITY] 24 - 28 March 2014

by Will Newton

== Progress == * Bugfix aarch64 setcontext patch (2/10, TCWG-410) * malloc requirements wiki page (2/10, TCWG-414) * Lots of creating and updating and updating JIRA cards (1/10) * glibc patch review (1/10) * Assorted small patches - ld relasz, gnulib obstack, glibc strtod benchmark (2/10) * Investigate a couple of issues raised by member services and on lists (2/10) == Issues == * None == Plan == * Resurrect glibc malloc benchtest * More glibc benchmark infrastructure work * Check status of glibc ARM port build warnings -- Will Newton Toolchain Working Group, Linaro

11 years, 5 months

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[ACTIVITY] March 17-23

by Maxim Kuvyrkov

== Week of March 17th == - STREAM regression (TCWG-388, 4/10) -- Investigated how to prioritize memory references instructions in GCC scheduler to take full advantage of L2 autopretch hardware in certain ARM cores. -- Fixed -fdbg-cnt=sched_insn debug counter along the way. It appear to have been broken since GCC 4.7. - Discussed reg_pressure instruction scheduling with Charlie. (TCWG-135, 1/10) - Various discussions about instruction scheduling in GCC. (1/10) - Together with Michael prepared patch list for GCC contingency plan. (3/10) - Made first-in-series video about tips-and-trick of GCC development. Your critiques are welcome! -- Using GCC debug counters (7m34s): https://www.youtube.com/watch?v=IWRYCOkgL04 == Week of March 24th == - STREAM regression (TCWG-388) -- Get a prototype patch. - Other expected and unexpected tasks that come up. -- Maxim Kuvyrkov www.linaro.org

11 years, 5 months

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[Activity] 17-21 March 2014

by Charles Baylis

Last week * one day off [2/10] * NEON scheduling investigation - TCWG-135 [3/10] . investigated scheduler register pressure heuristics . call with Maxim about scheduling algorithm . still more investigation required * NEON intrinsics vs assembler libvpx performance difference investigation [5/10] . GCC seems to generate poor code for address generation in NEON loads/stores . maybe some improvements to the intrinsics code would also be possible Plan: . write down some conclusions about libvpx performance . investigate PR60609 . more on TCWG-135 . investigate LP1296676 & LP1296601 ICEs when building the kernel

11 years, 5 months

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[Activity] March 17-21 (2014)

by Venkataramanan Kumar

== Progress == Machine descriptions for stack smashing in Aarch64 - TCWG-23 (5/10) * Completed building QEMU for Aarch64 on Ubuntu 13.10. Ran regression tests on it. * Submitted patches for libssp as per Marcus suggestions and got it approved. PGO support for Aarch64 -TCWG- 179 (2/10) * Installed "CPU2006" tools in foundation model running open embedded image and started running benchmarks. Plan is to build it with -PGO next. Bug fix (2/10) * Working on reproducing and fixing PR60617. Misc (1/10) * AMD Internal meeting and work. == Plan == * Bug fix PR60617. * Build CPU006 benchmarks with -PGO flag * Restart PGO bootstrap failure investigations

11 years, 5 months

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Compatiblity of armv7 GCC produced binary on AArch32 on armv8

by Karlsson, Magnus

Hi, I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out. The following are obsoleted in ARMv8:  A32 SWP and SWPB instructions.  Jazelle (only trivial implementations are supported).  VFP short vectors and asynchronous bounces.  Fast Context Switch Extension (FCSE). Thanks: Magnus Magnus Karlsson Software Development Engineering Manager LSI Corporation Box 1024, Knarrarnäsgatan 15 SE-164 21 Kista, Sweden TEL +46 8 594 607 09 FAX +46 8 594 607 10 CELL +46 73 80 444 88 magnus.karlsson(a)lsi.com

11 years, 5 months

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[ACTIVITY] Week 12

by Yvan Roux

== Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - Stop progress on this card, will close it when FSF 4.9 will be released. o TCWG-345 : Analyse performance of LRA for ARM. (4/10) - Spec2K figures on Cortex-a15 Analysis. - re-run benchs in console mode chrubuntu without ASLR + perf tool * Backports review: (2/10) o Start to prepare cortex-a53 backports review * Misc: o Various meetings and slideware (4/10). - Linaro and internal ones. == Next == - continue cortex-a53 review - some backports to do. - continue on TCWG-345

11 years, 5 months

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[ACTIVITY] 17 - 21 March 2014

by Will Newton

== Progress == * Worked on getting eglibc git mirror back up and running * Released eglibc 2.19 2014.04 * Respin of glibc aarch64 setcontext patches * Respin of ld aarch64 RELASZ patch * Tidied up, rebased and committed ARM ld pointer equality patch * Work on resurrecting glibc benchmark result graphing script * Holiday on Friday == Issues == * Couple of hours power outage on Monday == Plan == * Get outstanding glibc and binutils patches committed * Reorganise JIRA cards for malloc work * glibc benchmarking -- Will Newton Toolchain Working Group, Linaro

11 years, 5 months

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[ACTIVITY] 17 - 21 March 2014

by Omair Javaid

== Progress == * Add support for fork/vfork/exec events/catchpoints in remote gdbserver [TCWG-263] [4/10] -- Debugged catchpoint code and reviewed gdbserver implementation for events. -- Still require a lot of code understanding before actual implementation can start. * Wrote a script that takes two gdb build trees and configuration arguments to test them in native, remote-native and remote-target configurations [TCWG-96] [3/10] * Laptop OS re-install [1/10] * GDB open cards issues review [1/10] * Sick half day off on Friday [1/10] == Plan == * Complete work on TCWG-96. -- Write a script that tests gdb in remote-native configuration using ssh. -- Integrate all testing scripts and test them. -- Update wiki page with updated scripts and how to use them. * Monday Day Off: Pakistan Day 23rd March public holiday roll over.

11 years, 5 months

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[Weekly] 17-21 MAR 2014

by Kugan

== Progress == CARD-1210 - optimizing prologue/epilogue With -fomit-frame-pointer (4/10) - regression tested the patch and fixed issues - Dropping the patch and closing the card as it has been worked on at arm. TCWG-15 - zero/sign extension elimination for crc (3/10) - Looked at crc and looked at the other optimizations listed in card 440. - Improved the local patch to remove the missing optimization TCWG-413 - Running spec2006 with aarch64 (3/10) - Built and set-up spec2006. - Ran into to some compile time and run time errors == Plan == Continue with zero/sign extension elimination Start looking at literal pool merging

11 years, 5 months

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Subject: [Weekly] 17-21 MAR 2014

by Michael Collison

== This week == Merged all backports related to a53 support and successfully built arm and aarch64 cross compilers: 202333 - [AArch64, ARM] Introduce "mrs" type attribute. 202334 - [AArch64] Use neon_<ldm,stm>_2 where appropriate as "type". 202448 - [AArch64] Prevent generic pipeline description from dominating other pipeline descriptions. 202560 - set "type" attribute properly in arm_cmpsi_insn, cleanup 203241 - Cortex-a53 use Cortex tuning 203611 – 203621 – Neon types Parts 1 to 10 204575 - [ARM, AArch64] Make aarch-common.c files more robust. 205050 - [ARM] Add missing type attribute to zero_extend on arm 204782 - [AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default. 204784 - [AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2" tuning options. 204852 - [AArch64] Remove simd_type 205014 - [AArch64] Remove v8type attribute. 205105 - [AArch64] Remove "mode", "mode2" attributes 204783 - [AArch64] [-mtune cleanup 3/5] [Temporary] When asked to tune for Cortex-A57, tune for Cortex-A15 == Next week == Test a53 support Backport vectorization bug == Future ==

11 years, 5 months

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[ACTIVITY] Week 12

by Zhenqiang Chen

== Issues == * None == Progress == * Identify a missing instruction pattern which blocks fcsel optimization. A patch was sent out for community review. [2/10, TCWG-309] * Identify a ICE when handling dwarf-info in ARM backend when testing shrink-wrap. A fix was committed to trunk. [2/10] * Rebase and test the shrink-wrap codes for APCS_FRAME. [5/10] * Prepare Linaro toolchain 2014.03 binaries release [1/10]. * Investigate CRC improvement chances. == Plans == * Create a prebuilt sysroot based on Linaro eglibc-2014.04. * Continue on shrink-wrap.

11 years, 5 months

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[ACTIVITY] Week 12

by Renato Golin

== Progress == * AArch64 (TCWG-387) - Implemented simple C sin/cos functions for sphereflake - AArch64 builds, passes check-all and test-suite - Closed Jira task * IAS (TCWG-377) - Updated release notes - IAS build, passes check-all, test-suite and compiles other large codebases - Closed Jira task * EHABI (TCWG-124) - Updated release notes - EHABI builds, passes check-all, test-suite - Waiting for last patch to go to close the Jira task * Compiler-RT (TCWG-125) - Re-testing with current trunk+RT, all pass - Next step, libunwind (not ready yet) * Background - Patch review, etc - Studying TableGen, writing some docs (http://llvm.org/docs/TableGen/) - Proposing changes to debug/EH unwind function attributes in IR - Changing Zorg to not submit LNT reports by default (avoids bot breakage) - Planning LLVM+Linux involvement as next big task * Time - CARD-862 8/10 - Others 2/10 == Plan == * Continue pushing __builtin___clear_cache and -fno-unwind-tables upstream * Implement the Clang part of __builtin___clear_cache and update the docs * Try to add LLVM/Clang to cbuildv2 * Start merging libunwind from libc++ to Compiler-RT and test it on ARM * Get the kernel task started with the LLVMLinux guys

11 years, 5 months

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New -fstack-protector-strong flag

by Diane Holt

Are there plans to offer this flag in an upcoming version of the Linaro toolchain? Thanks, Diane

11 years, 5 months

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-Bsymbolic breaks PMF comparison under ARM

by Giuseppe D'Angelo

Hello, the attached program changes the output from "true" to "false" when the -Bsymbolic / -Bsymbolic-functions options are passed to GCC. This happens on ARM -- on x86-64 output is always "true". The program involves a comparison, within a shared library, of a PMF defined inside the shared library itself with the same PMF passed by the application. At this stage I still don't know if it's a GCC problem, a ld.so problem, ABI constraints, undefined behaviour, or whatnot; but any help is appreciated. Compile with: > g++ -fPIC -shared -Wall -o libshared.so -Wl,-Bsymbolic shared.cpp > g++ -fPIE -Wall -o main main.cpp -L. -lshared (The long story is that Qt 5 is taking PMFs in its public API, and the comparison failing inside of Qt shared libraries is breaking code on ARM, as -Bsymbolic is set by default there.) Thanks, -- Giuseppe D'Angelo | giuseppe.dangelo(a)kdab.com | Software Engineer KDAB (UK) Ltd., a KDAB Group company Tel. UK +44-1738-450410, Sweden (HQ) +46-563-540090 KDAB - Qt Experts - Platform-independent software solutions

11 years, 6 months

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[ACTIVITY] Week 11

by Yvan Roux

On vacation the whole week == Issues == * none == Progress == * Released Linaro GCC 4.8-2014.03 * Raised loop optimization regression on 4.9 - http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60482 - quickly fixed by Jakub == Next == * Backports reviews * AArch32 LRA

11 years, 6 months

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[ACTIVITY] 10 - 14 March 2014

by Will Newton

== Progress == * Off Monday after travelling back from Connect * Catching up on email and post-Connect admin * Released Linaro binutils 2.24.0 2014.03 * Submitted aarch64 setcontext patches upstream * Submitted a patch for ld RELASZ issue * Looked into eglibc svn mirroring == Issues == * None == Plan == * Resolve eglibc mirror situation -- Will Newton Toolchain Working Group, Linaro

11 years, 6 months

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[ACTIVITY] 10 - 14 March 2014

by Omair Javaid

== Progress == * Get started with Aarch64 GDB testing and development process using foundation model. [6/10] [CARD-1115] -- Figured out steps for running gdb in remote mode using foundation model. -- Wrote a wiki page with steps on development process, still in progress. -- Completed a gdb testsuite run and made a comparison with arm gdb. -- All new testsuite results will be available on gdb wiki page. -- Setup aarch64 gdb remote debugging. * Updates to GDB pages on wiki.linaro.org [TCWG-96] [2/10] -- Added pages containing test scripts and gdb testing tips -- Added page containing current gdb testsuite results in various configurations * Add support for fork/vfork/exec events/catchpoints in remote gdbserver [TCWG-263] [1/10] -- GDB code review for task break down, still in progress. * Fix network and internet problems [1/10] == Plan == * Arm v8 reverse debugging support.[CARD-1115] -- Provide card update and deliverable list. -- Implement reverse debugging infrastructure for aarch64 gdb. * Add support for fork/vfork/exec events/catchpoints in remote gdbserver [TCWG-263] -- GDB code review for task break down, still in progress. * Update and cleanup gdb wiki pages on wiki.linaro.org * All open gdb card review and update.

11 years, 6 months

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[Activity] March 10-14 (2014)

by Venkataramanan Kumar

== Progress == * Went through few Linaro Connect - LCA14 slides and videos . * Restarted upstream discussions on writing machine descriptions for stack smashing. Working on submitting patches again as per Marcus suggestions. * Installed "CPU2006" in foundation model running open embedded image and tried running 403.gcc benchmark. * Tried buiding QEMU for aarch64 on ubuntu 12.04,2. I am getting segment fault on using -L <library path >. Need to debug further. * PGO runs: GCC boot strap failed when libjava building at stage3. Need to have re-look further. Issue may be missing package in opembedded image on foundation model. Misc ------ Attended some Internal meetings. == Plan == * Continue machine descriptions for stack smashing work. * Work on using QEMU for running gcc test suites * Restart PGO bootstrap failure investigations

11 years, 6 months

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[ACTIVITY] Week 11

by Zhenqiang Chen

== Issues == * None == Progress == * Validate R/M toolchain 4.8 q1 update release. * Try Cross-Native build based on Linaro crosstool-ng. * Handle conditional compare in ifcvt.c to make ccmp and csel work together. * Read document about FCMP/FCCMP and investigate on how to generate FCCMP instructions: - The tree representation of UNORDERED compare (UNLT, etc) can not fit into current framework to handle CCMP. - For LT, LE, GT and GE, the compiler will generate FCMPE instruction, which can not be the first compare of CCMP. - For NE, EQ, it is easy to handle them based on previous patches. == Plan == * Continue on ccmp performance tuning.

11 years, 6 months

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[ACTIVITY] Week 11

by Kugan

== Progress == 4 Day week (10/03/2014 - Public holiday) https://cards.linaro.org/browse/CARD-1210 (6/10) - Implemented patch to fix it and bootstrapped gcc - Regression testing pending https://support.linaro.org/tickets/727 (2/10) - Looks like a tool-chain bug - Looking into it https://bugs.launchpad.net/gcc-linaro/+bug/1270789 - Addressing review comments == Plan == - Benchmark CRC with the patches - Set-up AARCH64 qemu system - Start with VRP patches

11 years, 6 months

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[Weekly] 10-14 MAR 2014

by Michael Collison

== This week == Completed the following backports related to a53 support: 201375 - Insn classification refactoring 7/n Factor out "type" attribute 201376 - Insn classification refactoring 7/n Factor out common scheduling dependency routines (done) 201399 - Insn classification unification 1/n Define "type" attrib for all patterns (done) 201400 - Share the a53 pipeline description between arm and aarch64 backends 201436 - Insn classification unification 4/N load/store types 202272 - [AArch64, AArch32][Insn classification refactoring 6/N] Remove "neon_type" attribute 202291 - [AARCH64][Insn classification unification 3/N] ALU/shift types 202292 - [AArch64] Fix categorisation of the frecp* insns. 202323 - [Patch ARM] Add "type" attribute to Everything! 202328 - [ARM,AARCH64] Insn type reclassification. Split f_cvt type. 202329 - [Patch ARM AARCH64] Split "type" attributes: fdiv 202330 - [Patch AArch64] Fix types for some multiply instructions. 202331 - [AArch64, ARM] Rename the FCPYS type to FMOV 202332 - [AArch64, ARM] Use "multiple" for type, where more than one instruction is used for a move == Next week == Complete remaining backports for a53 support and complete builds for arm and aarch64. == Future == -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

11 years, 6 months

1
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[ANNOUNCE] Linaro GCC 4.8 2014.03 released

by Yvan Roux

The Linaro Toolchain Working Group is pleased to announce the 2014.03 engineering release of Linaro GCC 4.8. As announced at Linaro Connect USA 2013 Linaro GCC is moving to a pattern of quarterly stable releases, with engineering releases in the intervening months. This is the second engineering release. The next stable release will be the 2014.04 release. Linaro GCC 4.8 2014.03 is the twelfth release in the 4.8 series. Based off the latest GCC 4.8.3+svn208264 release, it includes performance improvements and bug fixes. Interesting changes include: * Updates to GCC 4.8.3+svn208264 The source tarball is available from: http://releases.linaro.org/14.03/components/toolchain/gcc-linaro/4.8 Downloads are available from the Linaro Releases website: http://www.linaro.org/downloads/ More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.8/4.8-2014.03 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org ~

11 years, 6 months

1
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[ACTIVITY] Week 11

by Renato Golin

== Progress == * Ill until Thusrday due to Chinese food allergy/intolerance/poisoning - Seems I'm not the only one... * EHABI - Adding a few more EH tests to test-suite - Integration with ARM compiler better handled by ARM - Plugging -fno-unwind-tables to disable EH tables in ARM * Android - Implementing __builtin___clear_cache in LLVM - Need to add parsing to Clang later, and docs to LangRef * AArch64 - Tested a "fix" on sphereflake, didn't work - Seems the problem is the sin() results on glibc variants - We might need to round the result a bit shorter to make it work everywhere * Time - CARD-862 8/10 - Others 2/10 == Plan == * Continue ___builtin__clear_cache implementation * Continue RT and AArch64 test-suite investigation

11 years, 6 months

1
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build errors

by JustinGuo＠via-alliance.com

Dear Linaro toolchain support team: I am Justin Guo from S3 graphics Inc. I am studying linaro's big-little codes and is using TC2 Platform. I used ./linaro_kernel_build_cmds.sh to build kernel, I got no problem when I set CONFIG_DEBUG_INFO=y to build for kernel. However, When I trace kernel, the traced line in source code level is jumping up/down, so I tried to turn off the optimization. After modified Makefile as below to turn off optimization: ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) else KBUILD_CFLAGS += -O0 endif I got errors when build linaro kernel for TC2: root@ubuntu:/home/justinguo/linaro/1309# ./linaro_kernel_build_cmds.sh Directory linaro-kernel exists. If the kernel code exists in this directory you may continue without cloning the git repository for the kernel. Are you sure you want to do this? (y/n) y M Makefile HEAD is now at dafe325... Merge branch 'linux-linaro-lsk' into linux-linaro-lsk-android % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 100 57281 100 57281 0 0 90703 0 --:--:-- --:--:-- --:--:-- 188k Using /home/justinguo/linaro/1309/linaro-kernel as source for kernel GEN /home/justinguo/linaro/1309/linaro-kernel/out/Makefile CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h make[2]: `include/generated/mach-types.h' is up to date. CC kernel/bounds.s GEN include/generated/bounds.h CC arch/arm/kernel/asm-offsets.s GEN include/generated/asm-offsets.h CALL /home/justinguo/linaro/1309/linaro-kernel/scripts/checksyscalls.sh CC scripts/mod/empty.o MKELF scripts/mod/elfconfig.h CC scripts/mod/devicetable-offsets.s GEN scripts/mod/devicetable-offsets.h HOSTCC scripts/mod/file2alias.o HOSTCC scripts/mod/modpost.o HOSTCC scripts/mod/sumversion.o HOSTLD scripts/mod/modpost CC init/main.o CHK include/generated/compile.h CC init/version.o CC init/do_mounts.o CC init/do_mounts_rd.o CC init/do_mounts_initrd.o LD init/mounts.o CC init/initramfs.o CC init/calibrate.o CC init/init_task.o LD init/built-in.o CC arch/arm/vfp/vfpmodule.o AS arch/arm/vfp/entry.o AS arch/arm/vfp/vfphw.o CC arch/arm/vfp/vfpsingle.o CC arch/arm/vfp/vfpdouble.o LD arch/arm/vfp/vfp.o LD arch/arm/vfp/built-in.o CC arch/arm/kernel/elf.o AS arch/arm/kernel/entry-armv.o AS arch/arm/kernel/entry-common.o CC arch/arm/kernel/irq.o CC arch/arm/kernel/opcodes.o CC arch/arm/kernel/process.o CC arch/arm/kernel/ptrace.o CC arch/arm/kernel/return_address.o /home/justinguo/linaro/1309/linaro-kernel/arch/arm/kernel/return_address .c:63:2: warning: #warning "TODO: return_address should use unwind tables" [-Wcpp] CC arch/arm/kernel/sched_clock.o CC arch/arm/kernel/setup.o CC arch/arm/kernel/signal.o CC arch/arm/kernel/stacktrace.o CC arch/arm/kernel/sys_arm.o CC arch/arm/kernel/time.o CC arch/arm/kernel/traps.o CC arch/arm/kernel/atags_parse.o CC arch/arm/kernel/cpuidle.o CC arch/arm/kernel/armksyms.o CC arch/arm/kernel/module.o AS arch/arm/kernel/sleep.o CC arch/arm/kernel/suspend.o CC arch/arm/kernel/smp.o CC arch/arm/kernel/smp_tlb.o CC arch/arm/kernel/smp_scu.o CC arch/arm/kernel/smp_twd.o CC arch/arm/kernel/arch_timer.o CC arch/arm/kernel/ftrace.o CC arch/arm/kernel/insn.o CC arch/arm/kernel/unwind.o CC arch/arm/kernel/devtree.o CC arch/arm/kernel/swp_emulate.o CC arch/arm/kernel/hw_breakpoint.o CC arch/arm/kernel/perf_event.o CC arch/arm/kernel/perf_event_cpu.o CC arch/arm/kernel/topology.o CC arch/arm/kernel/io.o CC arch/arm/kernel/psci.o /tmp/cciaYmCJ.s: Assembler messages: /tmp/cciaYmCJ.s:147: Error: .err encountered /tmp/cciaYmCJ.s:148: Error: .err encountered /tmp/cciaYmCJ.s:149: Error: .err encountered /tmp/cciaYmCJ.s:150: Error: .err encountered /tmp/cciaYmCJ.s:191: Error: .err encountered /tmp/cciaYmCJ.s:192: Error: .err encountered /tmp/cciaYmCJ.s:193: Error: .err encountered /tmp/cciaYmCJ.s:194: Error: .err encountered make[2]: *** [arch/arm/kernel/psci.o] Error 1 make[1]: *** [arch/arm/kernel] Error 2 make: *** [sub-make] Error 2 root@ubuntu:/home/justinguo/linaro/1309# Could you Please help fix these issues? Best regards, Justin Guo

11 years, 6 months

2
2
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Call for testing QEMU aarch64-linux-user emulation

by Alex Bennée

Hi, After a solid few months of work the QEMU master branch [1] has now reached instruction feature parity with the suse-1.6 [6] tree that a lot of people have been using to build various aarch64 binaries. In addition to the SUSE work we have fixed numerous edge cases and finished off classes of instructions. All instructions have been verified with Peter's RISU random instruction testing tool. I have also built and run many packages as well as built gcc and passed most of the aarch64 specific tests. I've tested against the following aarch64 rootfs: * SUSE [2] * Debian [3] * Ubuntu Saucy [4] In my tree the remaining insns that the GCC aarch64 tests need to implement are: FRECPE FRECPX CLS (2 misc variant) CLZ (2 misc variant) FSQRT FRINTZ FCVTZS Which I'm currently working though now. However for most build tasks I expect the instructions in master [1] will be enough. If you want the latest instructions working their way to mainline you are free to use my tree [5] which currently has: * Additional NEON/SIMD instructions * sendmsg syscall * Improved helper scripts for setting up binfmt_misc * The ability to set QEMU_LOG_FILENAME to /path/to/something-%d.log - this is useful when tests are failing N-levels deep as %d is replaced with the pid Feedback I'm interested in ========================== * Any instruction failure (please include the log line with the unsupported message) * Any aarch64 specific failures (i.e. not generic QEMU threading flakeiness). If you need to catch me in real time I'm available on #qemu (stsquad) and #linaro-virtualization (ajb-linaro). Many thanks to the SUSE guys for getting the aarch64 train rolling. I hope your happy with the final result ;-) Cheers, -- Alex Bennée QEMU/KVM Hacker for Linaro [1] git://git.qemu.org/qemu.git master [2] http://download.opensuse.org/ports/aarch64/distribution/13.1/appliances/ope… [3] http://people.debian.org/~wookey/bootstrap/rootfs/debian-unstable-arm64.tar… [4] http://people.debian.org/~wookey/bootstrap/rootfs/saucy-arm64.tar.gz [5] https://github.com/stsquad/qemu/tree/ajb-a64-working [6] https://github.com/susematz/qemu/tree/aarch64-1.6

11 years, 6 months

7
26
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linking AArch64 ELF image with aarch64-linux-gnu-ld yields RELASZ = 0

by Claudio Fontana

Hello, I am building an ELF image using aarch64-linux-gnu-ld from linaro: GNU ld (crosstool-NG linaro-1.13.1-4.8-2014.02 - Linaro GCC 2014.02) 2.24.0.20131220 I am linking in the libstc++.a, which contains in particular a GOT entry for __gthread_active_ptr that is of interest to me, pointing to __pthread_key_create, used for detecting pthread support for std::thread, and while I get the relocations for the GOT itself in a .rela.dyn section, and a nice pointer to it from the dynamic section (RELA), the dynamic RELASZ entry contains zero: Here is the comparison of the Dynamic section (note RELASZ) with the following .rela.dyn relocations: loader.elf: file format elf64-littleaarch64 loader.elf architecture: aarch64, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED start address 0x00000000400b0000 Program Header: LOAD off 0x0000000000000000 vaddr 0x0000000040090000 paddr 0x0000000040090000 align 2**16 filesz 0x0000000000407084 memsz 0x00000000004aa504 flags rwx TLS off 0x0000000000407080 vaddr 0x0000000040497080 paddr 0x0000000040497080 align 2**3 filesz 0x0000000000000004 memsz 0x0000000000000580 flags rw- DYNAMIC off 0x0000000000001000 vaddr 0x0000000040091000 paddr 0x0000000040091000 align 2**3 filesz 0x0000000000000120 memsz 0x0000000000000120 flags rw- EH_FRAME off 0x00000000003ce5fc vaddr 0x000000004045e5fc paddr 0x000000004045e5fc align 2**2 filesz 0x000000000000bae4 memsz 0x000000000000bae4 flags r-- NOTE off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x0000000000000000 align 2**3 filesz 0x0000000000000000 memsz 0x0000000000000000 flags --- Dynamic Section: NEEDED dummy-shlib.so INIT_ARRAY 0x00000000404841b8 INIT_ARRAYSZ 0x0000000000000330 HASH 0x000000004044bd58 STRTAB 0x00000000403e3320 SYMTAB 0x00000000403a4110 STRSZ 0x0000000000068a33 SYMENT 0x0000000000000018 DEBUG 0x0000000000000000 RELA 0x00000000404780c0 RELASZ 0x0000000000000000 RELAENT 0x0000000000000018 private flags = 0: ... 10 .rela.dyn 00002058 00000000404780c0 00000000404780c0 003e80c0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA ... and now the .rela.dyn.relocations from aarch64-linux-gnu-readelf -r loader.elf : Relocation section '.rela.dyn' at offset 0x3e80c0 contains 345 entries: Offset Info Type Sym. Value Sym. Name + Addend 0000404832d0 002b00000401 R_AARCH64_GLOB_DA 00000000405339c8 _ZNSt8time_getIwSt19is + 0 0000404832d8 004400000401 R_AARCH64_GLOB_DA 000000004047e450 _ZTISt7codecvtIcc11__m + 0 0000404832e0 004b00000401 R_AARCH64_GLOB_DA 00000000405338c8 _ZGVNSt8numpunctIcE2id + 0 0000404832e8 005800000401 R_AARCH64_GLOB_DA 000000004047c460 _ZTISt8messagesIcE + 0 0000404832f0 006200000401 R_AARCH64_GLOB_DA 000000004047df40 _ZTVSt9strstream + 0 0000404832f8 007200000401 R_AARCH64_GLOB_DA 00000000402870dc _ZNSt17bad_function_ca + 0 000040483300 008500000401 R_AARCH64_GLOB_DA 0000000040534e58 _ZGVN9__gnu_cxx16bitma + 0 000040483310 00c300000401 R_AARCH64_GLOB_DA 0000000040533a18 _ZNSt6locale2id11_S_re + 0 000040483318 00dd00000401 R_AARCH64_GLOB_DA 000000004047c160 _ZTISt5ctypeIwE + 0 000040483320 00ea00000401 R_AARCH64_GLOB_DA 0000000040534e18 _ZZN9__gnu_cxx9free_li + 0 000040483328 011700000401 R_AARCH64_GLOB_DA 0000000040533968 _ZGVNSt8time_getIwSt19 + 0 000040483330 013500000401 R_AARCH64_GLOB_DA 000000004047cfd8 _ZTISt7num_getIwSt19is + 0 000040483338 017300000401 R_AARCH64_GLOB_DA 000000004021d51c __pthread_key_create + 0 ... ^^...note the __pthread_key_create relocation I am interested in... I would expect the RELASZ in the dynamic section to be 0x2058 instead of 0. Any tips to what could be wrong? Thank you, Claudio Fontana

11 years, 6 months

2
1
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Building a native version of Linaro GCC in Ubuntu

by Felipe Rocha da Rosa

Hi, I'm trying to build the native compiler to a arm a9 using this tutorial,https://wiki.linaro.org/WorkingGroups/ToolChain/Using/GCCNative.Ho…, I need to compile in a x86_64 platform ubuntu, like this --target=arm-unknown-eabi --build=i686-pc-linux-gnu --host=arm-unknown-eabi, but without success.There is any possible solution? Thank you.Felipe Rocha da Rosa.

11 years, 6 months

4
4
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Trouble executing ARM code on linaro toolchain

by Vishwanath C

Hi all, We are using Linaro 13.03 toolchain(gcc-linaro-arm-linux-gnueabihf-4.7-2013.03-20130313_linux We are trying to execute a simple test code to check whether ARM assembly code executes on board or not. Execution is on Arndale Board. Every time We include assembly function, We get segmentation fault. Kindly check if I We are missing any arm related flags in makefile. We have attached the 'helloworld' test code and makefile. Regards, Vishwa =============================================================================== Please refer to http://www.aricent.com/legal/email_disclaimer.html for important disclosures regarding this electronic communication. ===============================================================================

11 years, 6 months

2
2
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RE: detecting the linaro toolchain via C/C++ preprocessor

by Vermeulen, Michiel

If your code is sensitive to the size of long long, can you use the predefine: __SIZEOF_LONG_LONG__ If that doesn't work, then you can use: gcc -dM -E - < /dev/null to tell you what predefines a gcc compiler has (I would probably look for predefines more specific to what your code is sensitive to than look for a particular compiler). I also wonder a little about your original problem statement since "%lld" should be a way to always print "long long" and if you have a matched set of compiler and library, then it should adjust both together. If you are using "%ld" instead, this works in situations where "long" is the same size as "long long" but may not work when these are different sizes. --mev, Mike Vermeulen

11 years, 6 months

1
0
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detecting the linaro toolchain via C/C++ preprocessor

by Isidor Zeuner

Hi there! On Linaro gcc 4.6, I am facing an issue due to "long long" integers not being 64 bit as they are on other platforms I'm targeting, which causes different issues, most importantly with printf format strings. I am now circumventing these by using the C/C++ preprocessor in order to choose the right format strings. In order to minimize the necessity for users to manually configure things, I'm wondering if there is a way to detect the Linaro gcc compiler through preprocessor macros. Is this possible? Thanks. Best regards, Isidor

11 years, 6 months

2
1
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Trouble executing ARM code on linaro toolchain

by Vishwa

Hi all, We are using Linaro 13.03 toolchain( gcc-linaro-arm-linux-gnueabihf-4.7-2013.03-20130313_linux We are trying to execute a simple test code to check whether ARM assembly code executes on board or not. Execution is on Arndale Board. Every time We include assembly function, We get segmentation fault. Kindly check if I We are missing any arm related flags in makefile. We have attached the ‘helloworld’ test code and makefile. Regards, Vishwa

11 years, 6 months

2
1
0 0

Building 4.8 without multilib

by Diane Holt

Is that supposed to be possible? When I add --disable-multilib to the configure options, the build fails on the install, because it hasn't built any of src/gcc-linaro-4.8-2014.02/libgcc: /bin/sh ../../../../src/gcc-linaro-4.8-2014.02/libgcc/../mkinstalldirs /home/ubuntu/work483/build/sysroot/home/ubuntu/opt/cross-gcc-linaro/lib/gcc/arm-linux-gnueabi/4.8.3 /usr/bin/install -c -m 644 libgcc_eh.a /home/ubuntu/work483/build/sysroot/home/ubuntu/opt/cross-gcc-linaro/lib/gcc/arm-linux-gnueabi/4.8.3/ /usr/bin/install: cannot stat `libgcc_eh.a': No such file or directory make[3]: *** [install-shared] Error 1 make[3]: Leaving directory `/home/ubuntu/work483/build/gcc/arm-linux-gnueabi/libgcc' make[2]: *** [install-target-libgcc] Error 2 make[2]: Leaving directory `/home/ubuntu/work483/build/gcc' make[1]: *** [install] Error 2 make[1]: Leaving directory `/home/ubuntu/work483/build/gcc' make: *** [stamp/gcc-install] Error 2 I don't want or need multilib, so I'd rather build the toolchain without it, but before I try to make that happen, I wanted to make sure it's supposed to be able to get built correctly that way. Thanks, Diane

11 years, 6 months

5
10
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[ACTIVITY] Week 9

by Renato Golin

== Progress == * IAS (TCWG-377) - Long discussions about magic in inline asm - Bottomline is: we're still validating anyway * AArch64 (TCWG-387) - Making it build with CMake, discarding some tests - Similar changes to the test-suite - All green except sphereflake * Buildbots - Investigating one failure on test-suite due to register allocator changes - Will continue this during or after Connect * Background - Connect preparations - EuroLLVM 14 sync call, paper discussions - Researching some kernel C/ASM syntax - Studying __builtin_constant_p usage - Patch reviews, etc. * Time - CARD-862 8/10 - Others 2/10 == Plan == * Connect

11 years, 6 months

1
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[ACTIVITY] 24 - 28 February 2014

by Will Newton

== Progress == * 3 day week (off Monday and travelling Friday) * QEMU ARMv8 CRC instructions (2/10, TCWG-52) * Slides for Connect (3/10) * Investigating AArch64 setcontext issue (1/10, TCWG-410) == Issues == * None == Plan == * LCA14 -- Will Newton Toolchain Working Group, Linaro

11 years, 6 months

1
0
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[ACTIVITY] 17 - 21 February 2014

by Will Newton

(slightly delayed) == Progress == * 3 day week (annual leave Thursday and Friday) * QEMU ARMv8 CRC instructions (4/10, TCWG-52) * Slides for Connect (1/10) * Further work on longjmp/setjmp Systemtap probes on ARM (1/10, TCWG-378) == Issues == * None == Plan == * Complete QEMU CRC instruction work * Preparation for Connect -- Will Newton Toolchain Working Group, Linaro

11 years, 6 months

1
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[Weekly] 17-21 FEB 2013

by Michael Collison

== This week == - US Holiday on Monday, January 17th - Backported 202407 - Fix parameter to vrsqte_f64 - Backported 202259 (on read/write branch) - AARCH64, fix return types for vaddvq_s64, vaaddvq_u64 - Backported 202321 - Fix vdup<bhsd>_lane<q>_* instrinsics' lane parameter - Backported 202322 - Fox register constraints for lane intrinsics - Installed Qemu64 simulator and attempted to test aarch64 backports. - Shared library issue is preventing qemu64 from executing; Rob Savoy is investigating == Next week == - Test pending git review backports with Qemu64 if issues resolved - Test backports completed this week on Qemu64 - New backports == Future == -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

11 years, 6 months

8
16
0 0

[ACTIVITY] Week 8

by Yvan Roux

== Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - No progress this week on my side. o TCWG-345 : Analyse performance of LRA for ARM. (4/10) - Analysed Spec2K figures on Cortex-a15. * Backports review: (1/10) o Start to look at the Gerrit review process. o Lack of testsuite results * Misc: o LCA'14 : AArch64 toolchain status session. (3/10) o Various meetings. (2/10) == Next == * Backports review * https://bugs.launchpad.net/bugs/1169164 * Connect

11 years, 6 months

1
0
0 0

[ACTIVITY] 23 - 28 Feburary 2014

by Omair Javaid

== Progress == * Completed testing and submitted patches upstream. [TCWG-251] [TCWG-252] [1/10] * Travel to capital Islamabad for Macau visa follow up. [3/10] * Shifting to new office space and setting up office [6/10] == Plan == * Study aarch64 code and create task breakdown for record/replay support. [TCWG-389] * Setup gdb for aarch64 and try to run a demo application. [TCWG-389] * Write how-to for using scripts to compare two gdb testsuite runs. [TCWG-96] * Setup network and internet etc in new office space.

11 years, 6 months

1
0
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[ACTIVITY] Week 08

by Zhenqiang Chen

== Issues == * None == Progress == * CCMP for AARCH64. - Design cases to cover most conditional compare combinations. - Set up qemu environment and run regression tests. And fix all the new FAILs. * Respawn 2014.01-01 baremental toolchains by setting CT_TARGET_LDFLAGS=" --specs=rdimon.specs " * Rebuild arm-linux-gnueabi toolchain and ran spec2k. But can not reproduce the regression about Linaro 4.8 based on 2014.01 release. == Plans == * Send out the CCMP patches for community review.

11 years, 6 months

1
0
0 0

[ACTIVITY] Feb 17-21

by Kugan

== Progress == - TCWG-394 (5/10) - Found one more issue, regression tested and posted the patch upstream for review - http://gcc.gnu.org/ml/gcc-patches/2014-02/msg01282.html. - TCWG-395 (1/10) - Started with a google doc for wiki update - Speck regression analysis with 4.7, 4.8 Nov and Dec releases (2/10) - Native build of these versions and rank spec2k benchmarking for all of them - Not able to reproduce it on a15 as reported == Misc == 1 Day off sick == Plan == - Get all the information required for wiki - TCWG-395 - Start working on TCWG-396

11 years, 6 months

1
0
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[Activity] Feb 17-23

by Rob Savoye

== Progress == * Fixed remote testing via Cbuildv2 (TCWG 324 - 3/10). Currently it supports multiple build farms, it uses my local hardware and the TCWG build farm, and when run via Jenkins it uses the TCWG build farm. * Got qemu-aarch64 built and working, added to the DejaGnu site.exp file used by Cbuildv2, so now aarch64 execution tests actually work. Then cloned qemu-aarch to the x86_64 tcwg build farm machines so Jenkins can use it. (TCWG 393 - 3/10) * Meetings and misc. (4/10) - Worked on LCA14 presentation. - Write documentation on how to tweak the config file for DejaGnu used by Cbuildv2 for remote test execution. - Got Gerritt and Jenkins integrated (thanks Paul!) so merge requests fire up Jenkins to do builds on everything in the TCWG build farm. - Had ITS create a new list 'tcwg-test-results', which soon will get buid failure notifications from Jenkins and any test regressions. - Added support for emailing test results to Cbuildv2. == Plan == * Test the Gerrit/Jenkins integration. * Improve new test analysis script to compare builds from more than the same day, since now some test runs take 32hours with all the execution tests running on a chromebook an Beagle Board. * Travel to Connect! == Issues == * Somebody needs to upgrade the crouton install on all our chromebooks, as the current version won't build GCC native.

11 years, 6 months

1
0
0 0

[ACTIVITY] Week 8

by Renato Golin

== Progress == * IAS (TCWG-377) - Abandoning softvfp implementation, we should not use it - Both softvfp and dwarf flags went back to kernel/android - Macro issue has been solved, IAS is now Gold! - Still doesn't compile the kernel, though... ;) - Discussions about inline assembly bailing on asm garbage * AArch64 (TCWG-387) - Trying to get the build working and passing tests - Some worries about config.guess updates (license) - Commented out some old JIT tests, they will never work - Memory allocation failures look real bugs, though - At least Five real bugs in test-suite * Background - Patch reviews - Further discussions about Dwarf vs. EH unwind tables - Discussing vectorizer pragmas with GCC list - Reviewing EuroLLVM14 papers - Helping Rob upgrade TCWG Chromebooks * Time - CARD-862 8/10 - Others 2/10 == Plan == * Take a look at Compiler-RT * Check some of the AArch64 errors * Maybe EH/unwind issues * Connect

11 years, 6 months

1
0
0 0

"invalid expression as operand" in aarch64 inline asm

by Kugan

Hi, I finally got around to checking the attached patch for the https://bugs.launchpad.net/ubuntu/+source/gcc-4.8/+bug/1270789 I noticed attached patch causes regression for pr38151.c in gcc test-suite. A reduced test-case that triggers this is: static unsigned long global_max_fast; int __libc_mallopt (int param_number, int value) { __asm__ __volatile__ ("# %[_SDT_A2]" :: [_SDT_A2] "nor" ((global_max_fast))); global_max_fast = 1; } In this regard I have couple of questions: 1. Is the in-line asm valid? Look ok to me. 2. For the pr38151.c regression, asm diff is as shown below. < add x0, x0, :lo12:.LANCHOR0 < ldr x0, [x0] --- > ldr x0, [x0,#:lo12:.LANCHOR0] This causes: pr38151.c:(.text+0x10c): relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against `.rodata' collect2: error: ld returned 1 exit status. If I however increase the alignment of .rodata where .LANCHOR0 is defined, this passes. Is alignment of BITS_PER_UNIT valid for SYMBOL_REF? If I change it as I am doing this attached patch, is there anything else I need to do. Thanks, Kugan

11 years, 6 months

2
2
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linaro/eglibc 2.19

by Khem Raj

Hi Linaro'ites We have upgraded eglibc to 2.19 in OpenEmbedded and I started to notice WARNING: No recipes available for: /home/kraj/angstrom/sources/meta-linaro/meta-linaro-toolchain/recipes-core/eglibc/eglibc_2.18.bbappend NOTE: Resolving any missing task queue dependencies And it seems in this bbappend the SRC_URIs are overridden to point to a Linaro release of eglibc I wanted to know if there is a 2.19 head for linaro eglibc being created ? in that case that bbappend needs fixing too. Thanks -Khem

11 years, 6 months

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Re: Reg: Recommended options for aarch64

by Matthew Gretton-Dann

Ganesh, Thank you for your email - please note this question is best directed at linaro-toolchain(a)lists.linaro.org where it is more likely to get picked up quickly. Our general rules for benchmarking are to use -mcpu=cortex-a## -O3 as the compiler flags (where ## is the particular CPU you are interested in). Linaro's philosophy is to try and get the best results possible that normal users will see, we don't go looking for 'magic' options that may give better performance on one benchmark, but not in general. Thanks, Matt On 20 February 2014 09:22, Gopalasubramanian, Ganesh <Ganesh.Gopalasubramanian(a)amd.com> wrote: > Hi, > > We would like to run some benchmarks in the foundation model. > I like to know which is the best option-set (GCC compiler options) that the linaro community recommends for aarch64. > > Regards > Ganesh > -- Matthew Gretton-Dann Linaro Toolchain Working Group matthew.gretton-dann(a)linaro.org

11 years, 6 months

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[ACTIVITY] 10-14 FEB 2014

by Kugan

== Progress == - vectorizer (7/10) - Looked into vectorizer target-hooks - enablement of half-float for vectorising; dropped the patch after discussing - Started analysing code generated with unlimited model - gcc 4.8 regression (1/10) - Built Novemnebr and December release (native with system libc) - Ran spec2k fp. Can see regression for ammp with -O3 (with -march=armv7-a and -mthumb) -Started bisecting - Chromebook reset-up (2/10) - SD card died and setup again - Using hdd for gcc testing == Plan == - Check ARMv5 regression for unaligned access - Look into vectorizer cost model/benchmarking

11 years, 6 months

2
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linaro toolchain recipe updates

by Khem Raj

The following changes since commit aa242029aa5eecc84a27f2ba026e8fedaf925dbd: Merge "linaro-image-lng: add package lng-network-config" (2014-02-14 16:24:51 +0000) are available in the git repository at: git://github.com/kraj/meta-linaro master for you to fetch changes up to e4b9751778fe7772185f12cbd29453bf80460546: binutils: Rename version to linux-2.24 (2014-02-16 05:16:00 +0000) ---------------------------------------------------------------- Khem Raj (3): gcc: Lets not override OE-Core gcc gcc-linaro-4.7: Delete binutils: Rename version to linux-2.24 .../binutils/binutils-cross-canadian.inc | 29 - .../binutils/binutils-cross-canadian_2.24.bb | 3 - .../binutils-cross-canadian_linaro-2.24.bb | 3 + .../recipes-devtools/binutils/binutils-cross.inc | 27 - .../binutils/binutils-cross_2.24.bb | 3 - .../binutils/binutils-cross_linaro-2.24.bb | 3 + ...dk_2.24.bb => binutils-crosssdk_linaro-2.24.bb} | 2 +- ...{binutils-2.24.inc => binutils-linaro-2.24.inc} | 5 +- .../binutils-armv5e.patch | 0 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11 years, 6 months

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-mfpu=softvfp+vfp in LLVM

by Renato Golin

Richard, I found some emails about you implementing softvfp back in 2003, and I'd like to know what is the expected behaviour when it conflicts with the target triple, for example: -triple arm-linux-gnueabihf + -mfpu=sofvfp+vfp In this case, in LLVM, the triple sets "-float-abi=hard" but the fpu would set "+soft-float-abi", which are contradictory flags. Is that case even possible? If so, what's the expected behaviour? Soft or hard float? Do the extra flags always override the triple behaviour? Is it expected that *every* compiler flag will work on a last-seen-sets-behaviour manner? cheers, --renato

11 years, 6 months

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[ACTIVITY] February 10-16

by Maxim Kuvyrkov

== Week of February 10th == - Reproduced STREAM performance regression. Started investigation. (3/10) - Setup development environment on HP Chromebook 11. (3/10) -- Chrome OS + crouton + ubuntu 12.04 + ppa/chromebook-arm -- produced a nice dev board environment. - Continued account setup and preparations for Connect. (2/10) - Misc. (2/10) -- Various meetings. -- Volunteered as admin for GCC's GSoC 2014. Filled in the application, started to stir up buzz in the GCC community. == Week of February 17th == - Continue investigation of STREAM performance regression. - Prepare FSF GCC 4.10 presentation for Connect. - Look more into how LAVA does things and how to customize rootfs'es for boards. -- In particular I'm interested in how to boot rootfs with matching kernel and linux-tools (perf is what I need) with ssh server on keystone board. -- Maxim Kuvyrkov www.linaro.org

11 years, 6 months

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[ACTIVITY] 10 - 14 Feburary 2014

by Omair Javaid

== Progress == * Updated, tested and re-submitted patch for arm native watchpoint/hwbreak rework. [2/10] * Updated, split-up and tested patches for process record ASIMD, VFP etc support. [TCWG-251] [TCWG-252] [3/10] * Tried setting up gdb for aarch64, no luck yet. [TCWG-389] [1/10] * Investigation of work required for catchpoints support for remote gdb and gdbserver. [TCWG-263] [2/10] * Study armv8 instruction set for record replay support. [TCWG-389] [2/10] == Plan == * Follow up on upstream patches. * Study aarch64 code and create task breakdown for record/replay support. [TCWG-389] * Setup gdb for aarch64 and try to run a demo application. [TCWG-389] * Write how-to for using scripts to compare two gdb testsuite runs. [TCWG-96] * Out of office on Tuesday and Wednesday for follow up on Macau visa application.

11 years, 6 months

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[ACTIVITY] Week 7

by Yvan Roux

== Issues == * none == Progress == * 4.8 2014.02 Engineering release. (3/10) * TCWG-58 : AArch64: Enable libsanitizer (2/10) o re-based christophe's patch on fresh LLVM sources. o committed in LLVM (Thanks Renato for your help) o Progress stopped on this card until 4.10 GCC is opened * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - No progress this week on my side. - Vladimir upstreamed a fix for Thumb code size regression http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59535 o TCWG-345 : Analyse performance of LRA for ARM. (1/10) - re-run Spec2K on Cortex-a15. * Misc: o LCA'14 : AArch64 toolchain status session. (1/10) o Support Christian Bruel in his Linaro ramp up. (1/10) o Various meetings. (2/10) == Next == * Continue the on-going tasks * backports review

11 years, 6 months

1
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[ACTIVITY] Week 07

by Zhenqiang Chen

== Issues == * None == Progress == * Take care lp: 1270040, lp:1278337 and Beagleboard "Abort" issue. * Respawn 2014.01 release to use newlib-linaro-2.1.0-2014.02 for baremetal toolchains (http://cbuild.validation.linaro.org/binaries/2014.01-01/) * Test codes to duplicate shared compares to get more conditional compares. Fix the bootstrap issue. But the latest test does not show performance improvement in Spec2K. * Rebase and test the CCMP patch. * Read document about aarch64 CCMP/CCMN instructions and write codes/patterns to generate the instructions. Test is ongoing. == Plans == * Ccmp for AARCH64.

11 years, 6 months

1
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[Activity] Feb 10-16

by Rob Savoye

== Progress == * Figure how to have tcwgweb and cbuild-tools process the test results from Jenkins and produce the diffs for comparison. (TCWG-391 6/10) * Wrote script to convert Jenkins produced data files to tcwgweb format. (TCWG-391 1/10) * Meetings and misc. (3/10) - Worked on LCA14 presentation. == Plan == * Continue fighting with tcwgweb to run test comparisons for Jenkins builds. TCWG-391) * Now that SSH is setup correctly in the TCWG build farm, GCC testing tries to execute the remote tests, but hit's an error in DejaGnu, which needs to be debugged and fixed. (TCWG-324) == Leave == * Off to Nepal & Mt Everest after Connect.

11 years, 6 months

1
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[Weekly] 10-14 FEB 2014

by Michael Collison

== This week == Monday - Off Reworked backports off origin instead of crypto-backport branch. Also used read/write git branch to push - Affected backports 201164-206168, 201170, 201175, 201261, 201263 and 202020 Submitted backports for code review via git review - Aarch64 ILP backports: 201164-206168, 201170, and 201175 - Aarch64 support for NEG in vectors registers: 201261 and 201263 - Aarch64 support for SISD shifts: 202020 == Next week == Submit backport 202256 for code review Backport 202407 assigned to me == Future == Things you plan to do in the future. -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

11 years, 7 months

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[ACTIVITY] Week 7

by Renato Golin

== Progress == * IAS (TCWG-377) - Stopping progress on .dn/.qn aliases, not suitable for IAS atm. - Working on softvfp+vfp aliases (PR18689) * EHABI (TCWG-124) - Removed -arm-disable-ehabi - Waiting for Keith's patch to work on EHABI respecting uwtables * Compiler-RT (TCWG-125) - Adding sanitizer guidelines for GCC developers - Implemented --rtlib=compiler-rt for Linux targets - Test-suite runs fine, only one error (PR18812) * AArch64 (TCWG-387) - First native builds, updating config.guess/sub (license issues) - Found some JIT problems, unittests should be disabled - Found some memory test failures - Found 20 failures in test-suite * Background - Usual patch reviews & discussions - Started a fire on GCC list, will monitor interactions closer - Had a BoF accepted at the GNU Cauldron about GCC+LLVM collaboration - Discussing possible LTO changes to binutils with GCC devs - Helping Christophe/Yvan add AArch64 support for asan * Time - CARD-862 8/10 - Others 2/10 == Plan == * Continue softvfp in Clang's driver * Work on Dwarf unwind tables * Investigate RT and AArch64 failures

11 years, 7 months

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[ACTIVITY] 10 - 14 February 2014

by Will Newton

== Progress == * newlib 2.1.0-2014.02 release (2/10) * Research and analysis of malloc workloads for benchmarking (2/10, TCWG-160) * QEMU ARMv8 CRC instructions (4/10, TCWG-52) * Slides for Connect (1/10) * Misc. patch management and looking at bugs (1/10) == Issues == * None == Plan == * QEMU CRC instructions * Finalize slides for Connect * malloc -- Will Newton Toolchain Working Group, Linaro

11 years, 7 months

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[ANNOUNCE] Linaro GCC 4.8 2014.02 released

by Yvan Roux

The Linaro Toolchain Working Group is pleased to announce the 2014.02 engineering release of Linaro GCC 4.8. As announced at Linaro Connect USA 2013 Linaro GCC is moving to a pattern of quarterly stable releases, with engineering releases in the intervening months. This is the first engineering release. The next stable release will be the 2014.04 release. Linaro GCC 4.8 2014.02 is the eleventh release in the 4.8 series. Based off the latest GCC 4.8.3+svn207411 release, it includes performance improvements and bug fixes. Interesting changes include: * Updates to GCC 4.8.3+svn207411 * ARM-v8 crypto intrinsics support * New vectorizer cost model The source tarball is available from: http://releases.linaro.org/14.02/components/toolchain/gcc-linaro/4.8 Downloads are available from the Linaro Releases website: http://www.linaro.org/downloads/ More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.8/4.8-2014.02 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? Inquire at support(a)linaro.org

11 years, 7 months

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Fwd: seemingly bug in Linaro gcc 4.8

by Koen Kooi

This should match what we have in meta-linaro/dora, which is the linaro 2013.12 toolchain release. ---------- Forwarded message ---------- From: Koen Kooi <koen(a)dominion.thruhere.net> Date: 17 January 2014 19:35 Subject: Fwd: seemingly bug in Linaro gcc 4.8 To: Koen Kooi <koen.kooi(a)linaro.org> Begin doorgestuurd bericht: > Van: Khem Raj <raj.khem(a)gmail.com> > Onderwerp: seemingly bug in Linaro gcc 4.8 > Datum: 17 januari 2014 17:56:23 CET > Aan: Koen Kooi <koen(a)dominion.thruhere.net> > > Hey Koen > > I am seeing a problem with linaro gcc-48 basically angstrom/2013.12 release > The issue is attached sample C file. When compiled and run on my ArchLinux > box which is running upstream gcc 4.8.2 it works ok > > but on beagleboard it fails. > > > to compile > > $CXX -pthread -std=gnu++11 a.cpp > > on ARCH > > kraj@leo ~ > g++ b.cpp -std=gnu++11 -pthread > kraj@leo ~ > ./a.out > 140309495478016 i: 1 > 140309503870720 i: 2 > > on Beagleboard > > root@beagleboard:~# ./std-thread > pure virtual method called > terminate called without an active exception > Aborted > > Can you pass this to right folks in Linaro and get some help in resolving it > > I havent yet trried it with OE-Core gcc which is also gcc 4.8 > > The issue is most probably ARM related as it seems to me. > > Thanks for help > > -Khem >

11 years, 7 months

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Configuration specifics of prebuilt libc binaries

by Evan Carson

Hello, I'm maintaining an older release we have which uses the older toolchian binaries in gcc-linaro-arm-linux-gnueabi-2012.03-20120326_linux. I've identified a bug in glibc we appear to be encountering and would like to port the fix back. I initially went the route of compiling the above toolchain binaries from source as described in the readme.txt but then found that the cross compiler binary build does not include the e/glibc build and these appear to be sucked in in binary form (oneiric-sysroot-r1). Are there any documents how these prebuilt libc binaries were created? Please note that I'm not asking in general how to build glibc. I've built a version with and without this bug patched to verify that it is indeed what we are hitting. I'm more hoping to get an idea of how the specific binaries mentioned above were built. Thanks in advance for any help! Evan Carson

11 years, 7 months

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[Weekly] 3-7 FEB 2014

by Michael Collison

== This week == - Backported 206261 and 201263 - AArch64 support NEG in vector registers - Backported 202020 - Support SISD shifts - Backported 202259 - AARCH64, fix return types for vaddvq_s64, vaaddvq_u64 - Travel back to US on Friday, February 7th == Next week == - Submit backport for review once crypto instruction review is complete and approved - Continue backports from trunk - New backports == Future == -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

11 years, 7 months

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linaro_binutils-2_24-2013_12_release tag and associated commits missing

by Gregory Fong

Hello, The binutils 2.24-2013.12 release page says that the release was built from the linaro_binutils-2_24-2013_12_release tag, but that tag doesn't seem to actually be present in the git repo at http://git.linaro.org/toolchain/binutils.git . Could that tag please be pushed? Thanks and regards, Gregory

11 years, 7 months

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[Activity] Feb 3-9

by Rob Savoye

== Progress == * Cbuildv2 now builds a static gdbserver for cross linux targets. (1/10) * Fixed Cbuildv2 bugs and added feature requests from Venkat, who is bravely being our beta site. (1/10) * Got .sum files produced from Jenkins builds copied to tcwgweb. Much of this was getting everything setup to allow files to be copied securely. (TCWG-386 - 3/10) * QEMU image prep for softfp and Rasberry PI testing. (TCWG-380 - 2/10) * Meetings and misc. (3/10) - Tweaks to Jenkins support so build names the remote directory in a way tcwgweb expects. - Added more info to TCWG Build Farm wiki page. (https://wiki.linaro.org/TCWG%20build%20farm) == Plan == * Figure out how to make tcwgweb run test comparisons. * Now that SSH is setup correctly in the TCWG build farm, GCC testing tries to execute the remote tests, but hits an error in DejaGnu, which needs to be debugged and fixed. (TCWG 324) * Add Win32 installer for Canadian cross built binary releases to Cbuildv2. (TCWG-381)

11 years, 7 months

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[ACTIVITY] Week 6

by Yvan Roux

== Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - No progress this week. o TCWG-345 : Analyse performance of LRA for ARM. (3/10) - Continue analysis on Cortex-a15. * LRA on AArch64: (2/10) o Start to look at PR 59222 (ICE with ILP32). * Branch merge and backports reviews. (2/10) * Continued Linaro 4.8 release performance on Cortex-a15. (2/10) * Various meetings. (1/10) * Misc: o start to prepare AArch64 toolchain status for Connect session. == Next == * Continue the on-going tasks * 4.8 2014.02 Engineering release

11 years, 7 months

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[ACTIVITY] 3-7 February 2014

by Christophe Lyon

== Progress == * Libsanitzer for AArch64: (3/10) - QEMU patch to handle missing mmap flag accepted. - Charles was able to build GCC + run the sanitizer tests on board - cleanup patch, ready to be sent to the LLVM list for approval * Cross-validation: (1/10) - extending timeout to 5h for aarch64-linux seems to be sufficient when using qemu-aarch64 * 2014.02 release preparation: (4/10) - branch merge - backported new vectorizer cost model (cheap, dynamic, unlimited), and ran some benchmarks. - asked Kugan to check the few improvements observed when using -fvect-cost-model=unlimited - reviewed Crypto intrinsics backport from Michael Collison. Discussed the use of gerrit+jenkins with him and Rob. - Charles ran the validation of the Crypto intrinsics backport on AArch64 hardware - I cross-validated it using binutils-linaro-2.24-2013.12, to make sure we release components capable enough to interoperate. - upgrading binutils in cbuildv1/tcwg-web would help, until we can switch to jenkins+cbuildv2+gerrit * Misc (2/10): conf-calls, meetings == Next == * libsanitizer on AArch64: post patch to LLVM list * crypto intrinsics: commit patch for 2014.02 release

11 years, 7 months

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[ACTIVITY] 3 - 7 Feburary 2014

by Omair Javaid

== Progress == * Short week: Public holiday on Wednesday 5th Feburary 2014. [2/10] * Ran gdb testsuites for arm and x86 (native + remote) with all in progress patches applied. [1/10] * Investigated and triaged arm only failures. [2/10] * Investigated gdb.dwarf2/implptr-64bit.exp failure and submitted patch to disable it for 32-bit targets.[2/10] * Installation and configuration of new desktop machine. [1/10] * Investigation of stack unwinding failures on arm. [1/10] * Investigation of work required to implement record and replay on aarch64. [1/10] == Plan == * Setup gdb for aarch64 and try to run a demo application. * Investigate remaining arm only failures in gdb for arm and work towards closeout of CARD-321. * Travel to Islamabad to receive passport back from Chinese embassy for Macau visa.

11 years, 7 months

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[ACTIVITY] February 3-9

by Maxim Kuvyrkov

== Week of February 3rd == - Various administrative bits and account setup. (6/10) - Worked my way through to getting access to LAVA board lab. Tried to reproduce performance regression on STREAM benchmark. (2/10) - Public holiday. (2/10) == Week of February 10th == - Continue account setup. Get work environment up. - Get to know the team. - Continue investigation of STREAM benchmark. -- Maxim Kuvyrkov www.linaro.org

11 years, 7 months

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[ACTIVITY] Week 05 & 06

by Zhenqiang Chen

== Issues == * None == Progress == * Jan. 31 - Feb. 6: Chinese Spring Festival holidays . * Test codes to duplicate shared compares to get more conditional compares. But still get unexpected bootstrap fail on Chrome book. * Test codes to enable shrink-wrap for TARGET_APCS_FRAME. * Update patch for PR 59837. * Create a reference linaro-arm-linux-gnueabihf-raspbian build . == Plans == * Tuning ccmp performance * Enable shrink-wrap for TARGET_APCS_FRAME.

11 years, 7 months

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[ACTIVITY] 3 -7 February 2014

by Kugan

== Progress == - Started implementing TARGET_ATOMIC_ASSIGN_EXPAND_FENV (5/10) - Regression testing with the implementation; found some issues and discussed with Matt - Working on fixing them - Patch for Vectorizer generates unaligned access when -mno-unaligned-access committed upstream (2/10) - This also triggered some regression with ARMv5 and looking into them (2/10) - Set-up qemu aarch64 for gcc testing (1/10) == Plan == - Check ARMv5 regression for unaligned access - Look into vectorizer cost model/benchmarking

11 years, 7 months

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Yocto Build of Toolchain with package tool rpm doesn't like the "dash" in the Release

by Gary Hannon

This is an attempt to build TI mcsdk 3.0.3.15 with bitbake tisdk-server-rootfs-image It fails trying to make rpms for the linaro toolchain. | DEBUG: Python function write_specfile finished | DEBUG: Executing shell function BUILDSPEC | error: line 4: invalid tag value("^[A-Za-z0-9+._]+$") Release: Release: r2-arago3 | error: Package has no %description: external-linaro-toolchain-2.15.armv7ahf_vfp_neon | Building target platforms: armv7ahf_vfp_neon-oe-linux-gnueabi | DEBUG: Python function do_package_rpm finished | DEBUG: Python function do_package_write_rpm finished | ERROR: Function failed: BUILDSPEC (see /home2/ghannon/keyDSP/build/mcsdk/build/arago-tmp-external-linaro-toolch ain/work/armv7ahf-vfp-neon-oe-linux-gnueabi/external-linaro-toolchain-20 13.03-r2-arago3/temp/log.do_package_write_rpm.8491 for further information) ERROR: Task 40 (/home2/ghannon/keyDSP/build/mcsdk/sources/meta-linaro/recipes-devtools/ external-linaro-toolchain/external-linaro-toolchain.bb, do_package_write_rpm) failed with exit code '1' If I change Release: r2-arago3 to not have a - in the spec file then I can build the rpms manually with the same command. Is there a place where I can change that globally? Gary Hannon Sr. Software Engineer CSP Inc. 43 Manning Road Billerica, MA 01821 978-663-7598 x1509 ghannon(a)cspi.com

11 years, 7 months

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[ACTIVITY] Week 6

by Renato Golin

== Progress == * IAS - Having a go at .dn/.qn aliases - Some Dwarf 2/3 discussions, kernel build flags, etc * EHABI - Tables being generated even when no EH in C - Will need some tinkering in Clang and LLVM - Huge discussion about EHABI, Dwarf unwinding and exception tables - Starting the refactory of EHABI to cope with the differences * Compiler-RT - Finding the best way to use compiler-RT with Clang (not an easy task!) * Background - Usual patch reviews & discussions - Mapping AArch64 features implemented for Connect session - Playing with the Calxedas for some benchmarks * Time - CARD-862 8/10 - Others 2/10 == Plan == * Continue with EHABI refactoring * Implement --rtlib in Clang for compiler-rt usage * Continue .dn/.qn implementation

11 years, 7 months

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[ACTIVITY] 3 -7 February 2014

by Will Newton

== Progress == * 3 day week * Further work on longjmp/setjmp Systemtap probes on ARM (1/10, TCWG-378) * Research and analysis of malloc workloads for benchmarking (5/10, TCWG-160) == Issues == * None == Plan == * More work on an application level malloc benchmark framework * Resurrect glibc benchmark graphing script * newlib release * gdb 7.7 release (build an rc to troubleshoot releasing from git) -- Will Newton Toolchain Working Group, Linaro

11 years, 7 months

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kernel support for cortex A8 hardware watchpoints

by Marc Kleine-Budde

Hello Ulrich, I'm on a freescale mx53 (single core, cortex a8) and trying to find a nasty problem in our $CUSTOMER's application. Working hardware watch point support in gdb should solve the problem, or at least brings us a big step forward. I stumbled over your about three years old thread[1] about the cortex a8 memory mapped debug registers problem. Do I understand correctly, that you had a8 watch point running on at least one board? Have you got any code and or pointers to get watch point support running? regards, Marc Kleine-Budde [1] http://lists.linaro.org/pipermail/linaro-toolchain/2011-February/000820.html -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |

11 years, 7 months

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Linaro GNU Compiler (GCC) toolchain : for Renesas RZ (ARM Cortex-A9) + FreeRTOS (Demo Project)

by Steffen Sprung

*Hi LINARO-TEAM,* I would like start a software development on a “Renesas RZ (ARM Cortex-A9) MPU (R7S721010xxx” by using Eclipse IDE (Kepler - 4.3.1). > Global objective = Use free SW development tools I have read, that the “Linaro GCC Toolchain Release Supports Full Range of ARM Cortex-A Processors” and it’s an open source software for the ARM architecture, including the GCC toolchain. > Well – I think that is what I need. So, I have installed the Linaro Toolchain (gcc-arm-none-eabi-4_7-2013q3-20130916-win32.exe) and test the compilation of the “*Hello World ARM C Project*” for the Target Processor “cortex-A9” > So, the compilation is OK. *NOW, I would like prepare a small TEST-Project with FreeRTOS.* FreeRTOSV8.0.0_Release_Candidate_2 > I have found the “Renesas RZ (ARM Cortex-A9) RTOS Demo”: http://www.freertos.org/Renesas_RZ_Cortex-A9-RTOS.html But the two projects are provided to be built with the* IAR Embedded Workbench <http://www.iar.com/ewarm>* or the *ARM DS-5 <http://arm.com/products/tools/software-tools/ds-5/index.php> embedded development tools*. > I have seen that the DS-5 Development Studio is not for free but it use also the Linaro GNU Compiler (GCC) toolchain. So, I have tried to import the “Renesas RZ (ARM Cortex-A9) RTOS Demo” project to Eclipse, *but the import doesn’t work – and I’m not sure that the project uses the Linaro GNU GCC Compiler**.* > I think that Demo project for DS-5 use also special plugins/configuration settings from the Development Studio – so this can’t work ?!… *HELP:* *I’m new in the “Eclipse IDE / Compiler (GCC) toolchain” WORLD … * So, can you help me to give me a good direction - *what I need to do *to make running this small “Blinky-Demo for Renesas RZ (ARM Cortex-A9) with the FreeRTOS” by using the Linaro GCC Toolchain. > Or have you another small Demo project for the Linaro GCC Toolchain which uses the FreeRTOS for the Renesas RZ (ARM Cortex-A9) family? … Or you think that is not easily possible to do that for a Newcomer like me? I hope that you can help me to put me on the right road. Best regards, *Steffen SPRUNGACTIA Automotive* ================= Software Engineer ================= *ACTIA* Automotive 5 Rue Jorge SEMPRUN – BP 74215 31432 TOULOUSE Cedex 4 (FRANCE) Tél.: + 33 (0)5 61 17 68 75 Fax: +33 (0)5 61 55 42 31 Skype: steffen.sprung EMAIL: steffen.sprung(a)actia.fr ACTIA: http://www.actia.com [image: image001] *P* Avant d’imprimer ce mail, demandez-vous si ceci est nécessaire. Before printing this email, assess if it is really needed.

11 years, 7 months

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systemtap test suite compilation failed: runtime/vma.c :133:21: error: pointer targets in initialization differ in signedness

by Naresh Kamboju

Hi, The systemtap test suite compilation failed with below error. ARCH: arm --------------- kernel location: kernel version: 3.13.0-1-linaro-arndale systemtap location: /usr/local/bin/stap systemtap version: version 2.5/0.157, non-git sources gcc location: /usr/bin/gcc gcc version: gcc (Ubuntu/Linaro 4.8.1-10ubuntu8) 4.8.1 **** failed systemtap kernel-devel smoke test: In file included from /usr/local/share/systemtap/runtime/sym.c:16:0, from /usr/local/share/systemtap/runtime/linux/runtime.h:198, from /usr/local/share/systemtap/runtime/runtime.h:24, from /tmp/stapvEzrD5/stap_f7468ebd0051d533d2bae853173fe5a7_892_src.c:24: /usr/local/share/systemtap/runtime/vma.c: In function '_stp_vma_mmap_cb': /usr/local/share/systemtap/runtime/vma.c:133:21: error: pointer targets in initialization differ in signedness [-Werror=pointer-sign] const char *name = (dentry != NULL) ? dentry->d_name.name : NULL; ^ cc1: all warnings being treated as errors make[4]: *** [/tmp/stapvEzrD5/stap_f7468ebd0051d533d2bae853173fe5a7_892_src.o] Error 1 make[3]: *** [_module_/tmp/stapvEzrD5] Error 2 WARNING: kbuild exited with status: 2 Pass 4: compilation failed. [man error::pass4] **** aborting testing. Please let me know if you need more information. Best regards Naresh kamboju

11 years, 7 months

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[ACTIVITY] 27 - 31 January 2014

by Omair Javaid

== Progress == * Fixed remaining issues in rework of hwbreakpoint and watchpoint implementation for arm native targets. Tested and submitted patch. [TCWG-177] [8/10] * Installation and Setting up of new desktop machine. [2/10] == Plan == * Run testsuites to see current status of arm gdb. * Follow up on submitted patches. * Public holiday on Wednesday 5th February.

11 years, 7 months

1
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[ACTIVITY] 27-31 Januery 2014

by Christophe Lyon

* Libsanitizer for AArch64: (4/10) - seems to be mostly working, but trouble with validation both using the Foundation Model and qemu-aarch64. - Some tests seems to loop forever while unwinding under qemu, but run fine under the Foundation model - Conversely the Foundation Model shows some random errors, and the corresponding tests pass under qemu - Some random timeouts with the Foundation Model, despite using ssh multiplexing - Added a small patch to qemu to hande missing mmap flag. Need to send upstream. - asked Rob to run GCC testsuite with my patch on AArch64 but it's too unstable these days * Cross-validation (2/10) - script now able to validate a GCC patch and compare results with unmodified GCC trunk - added arm-none-eabi target - using qemu-aarch64 for aarch64-none-linux-gnueabi but the validations now time out. Need investigation, but I might have to revert to no execution for this target. - identified a problem with the recent armv7-ve patch * Benchmarks: (1/10) - collecting data for 4.8 tables * Peeling: (1/10) - backported new vectorizer cost model to check it if's OK to include it in our next release * Misc (2/10): conf-calls, meetings, docs (howtos for TCWG) == Next == * libsanitizer on AArch64 * fix cross-validation on aarch64-none-linux-gnu * benchmarks: complete table * backports: chek new vectorizer cost model, monthly branch merge, review Michael's backports of Crypto intrinsics

11 years, 7 months

1
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[ACTIVITY] Week 5

by Yvan Roux

* 2 days week (university & child care). == Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (0/10) - No progress this week o TCWG-345 : Analyse performance of LRA for ARM. (1/10) - Configured and ran benchmarks on Cortex-a15. * Looked at Linaro 4.8 release performance on Cortex-a15. (2/10) * Misc. (1/10) o Booked Hotel and flight for connect == Next == * Back on LRA and lib GMP

11 years, 7 months

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[Activity] 27 Jan - 31 Jan 2014

by Venkataramanan Kumar

== Progress == * Investigate "PGO" for Aarch64 (3/10). Bootstap testing aarch64 with PGO for GCC.Stage 2, feedback profile in progress. Tested a small test case for -fbranch-probabilities, works same as x86_64. Working on checking the "gcda" files generated and profile runs for coremark. * Cbuild2 discussed with rob, ryan on using cbuild2 for developement. (3/10) Thanks Rob for fixing some issues and adding features that I requested. Tested some features added. Captured it as FAQ. * Reinstalled ubuntu OS on my laptop (2/10) Misc (2/10) ------------- AMD internal meetings and did some investigations == Plan == - Continue run EMBCC and coremark benchmarks with -PGO enabled. - Going on marriage vacation from 07-Feb till 06 March == Issues=== Follow up upstream libssp GCC discussions. No response yet after 2 pings :(

11 years, 7 months

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[ACTIVITY] 27 - 31 January 2014

by Kugan

== Progress == * 4 Day week (Monday Public Holiday) (6/10) * Posted patches for bugs assigned https://sourceware.org/ml/binutils/2014-01/msg00332.html http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60034 http://gcc.gnu.org/ml/gcc-patches/2014-02/msg00048.html * TARGET_ATOMIC_ASSIGN_EXPAND_FENV implementation (2/10) Looked at glibc implementations of required functionality == Plan == * Finish TARGET_ATOMIC_ASSIGN_EXPAND_FENV implementation * Follow up on patches if required

11 years, 7 months

1
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[Activity] Jan 27-Feb 2

by Rob Savoye

== Progress == * Got binary release building working again. (2/10) * Added a node_selector to Jenkins for the new Beagle Board Blacks, and get those working for native builds. (TCWG-379, 1/10) * Fix configuration of 'build-all' project in Jenkins, now fires up cross builds for supported targets, plus native builds on Chromebooks and Beagle Board Blacks. (1/10) make networking route externally. (TCWG-380) * Meetings and Misc. (3/10) * Got TCWG build farm, all nodes offline fixed. * Wrote wiki page on the build farm. * Updated Java to 1.6 on the Beagle Board Blacks in the TCWG build farm. * Added support to specify an alternate prefix for installation. * Got QEMU and Foundation Model running on TCWG x86_64 build slaves so Jenkins can use them for native builds. (TCWG-380 - 2/10) * Got Rasberry PI softfp image running under QEMU, tried to do build. (TCWG-380 - 1/10) == Plan == * Build static gdbserver for target via Cbuildv2. * Add Win32 installer for Canadian cross built binary releases to Cbuildv2. * Get Kugan's benchmark branch running on build farm. * More Jenkins maintainance. == Potential Leave == * Still working out the huge amount of details, but strongly considering going to Mt Everest after Connect. It'd be a long and rough trip, but a once in a lifetime opportunity.

11 years, 7 months

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[Weekly] 26-31 JAN 2014

by Michael Collison

== This week == - Successfully submitted crypto using git-review - Completed merge of ILP backports from trunk to Linaro 4.8 branch: 201164, 201165, 201166, 201167, 201168, 201170 and 201175 - Attended ARM architecture training on Friday == Next week == - Submit ILP backports for review using git review - New backports == Future ==

11 years, 7 months

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[ACTIVITY] 27 - 31 January 2014

by Will Newton

== Progress == * Rework QEMU patch for AArch32 ARMv8 16<->64bit VCVT (2/10, TCWG-51) * Further work on longjmp/setjmp Systemtap probes on ARM (4/10, TCWG-378) * Research and analysis of malloc workloads for benchmarking (4/10, TCWG-160) == Issues == * None == Plan == * Finish testing setjmp/longjmp changes * malloc benchmarking and improvements -- Will Newton Toolchain Working Group, Linaro

11 years, 7 months

1
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[ACTIVITY] Week 5

by Renato Golin

== Progress == * EHABI - Turning EHABI on by default on non-Darwin ARM - Had to add some relocations to MCJIT - Re-enabled EH tests on test-suite - Check-all, self-hosting and test-suite bots green * Compiler-RT - Enabling RT+San libraries to compile on ARM - Changing Clang to look for the generic libraries (arm, not armv7l) * MCJIT - Remote protocol fixed, all tests passing on self-hosting bot - All tests re-enabled on ARM * Background - More IAS, Compiler RT patch reviews - Buildbot cleaning up before every build (more stable) - Cambridge LLVM Social - Rumours that LLVM can compile the kernel with the integrated assembler on ARM * Time - CARD-862 8/10 - Others 2/10 == Plan == * FOSDEM - Talking about LLVM auto-vectorization this Sunday * EHABI - ARM detected some conflicts with Dwarf stack unwinding, investigate Compiler-RT - Run test-suite, benchmarks, applications with it * IAS - Confirm the rumours about the kernel compiling clean - Pick up some remaining task to implement

11 years, 7 months

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TARGET_ATOMIC_ASSIGN_EXPAND_FENV

by Kugan

I had a look at the missing target hook TARGET_ATOMIC_ASSIGN_EXPAND_FENV to fix the C11 memory model testcase in regressions in trunk. I looked at the x86 implementation of this target hooks and x86 has instructions (FNSTENV,FLDENV,FNSTSW,FNCLEX) for feholdexcept, feclearexcept and feupdateenv. Does ARM has something similar? Any pointers/links I can refer to. Please see the gcc internal documentation for the target hook below. — Target Hook: void TARGET_ATOMIC_ASSIGN_EXPAND_FENV (tree *hold, tree *clear, tree *update) ISO C11 requires atomic compound assignments that may raise floating-point exceptions to raise exceptions corresponding to the arithmetic operation whose result was successfully stored in a compare-and-exchange sequence. This requires code equivalent to calls to feholdexcept, feclearexcept and feupdateenv to be generated at appropriate points in the compare-and-exchange sequence. This hook should set *hold to an expression equivalent to the call to feholdexcept, *clear to an expression equivalent to the call to feclearexcept and *update to an expression equivalent to the call to feupdateenv. The three expressions are NULL_TREE on entry to the hook and may be left as NULL_TREE if no code is required in a particular place. The default implementation leaves all three expressions as NULL_TREE. The __atomic_feraiseexcept function from libatomic may be of use as part of the code generated in *update. Thanks, Kugan

11 years, 7 months

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[ACTIVITY] 20 - 24 January 2014

by Christophe Lyon

== Progress == - releases (3/10) * GCC 4.7 and 4.8 releases done * more cbuild2 feedback - cross-validations (2/10) * followup * adding capability to test a patch over a given revision on several targets/cpu/fpu/runtestflags - libsanitizer on AArch64 (3/10) * most tests are now functional * still some errors in the GCC testsuite, to be analyzed (there are some timeouts, too despite using SSH multiplexing to the Foundation model) - misc (2/10): conf-calls and meetings == Next == - libsanitizer on AArch64: analyze errors, try QEMU == Future == On sick leave starting Feb 11th

11 years, 7 months

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[Activity] 20 Jan - 24 Jan 2014

by Venkataramanan Kumar

== Progress == * Libc probes support for Aarch64 (2/10). Wrote a small patch for setjmp and longjmp LIBC probe. Requested "will newton" to test them . * Investigate "PGO" for Aarch64 (3/10). Bootstap testing GCC with PGO for GCC. Stage 2, feedback profile in progress. Ran coremark on foundation model with PGO. The benchmark builds with profile-generate and runs. "gcda" files are generated and uses them to profile. Profile generated runs does not run cleanly. Cross checking if the generated profile is valid. * Resubmmited libssp machine description support in GCC (2/10). * Cbuild2 discussed with rob, ryan on SYSROOT installation while building (1/10) cross compiler for aarch64. "SYSROOT" is expected to be in /opt/linaro, but cbuild2 does not do this by default. Misc (1/10) ------------- AMD internal meetings and did some investigations == Plan == - Run EMBCC benchmarks with -PGO enabled. - Follow up upstream libssp GCC discussions.

11 years, 7 months

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[ACTIVITY] Week 4

by Yvan Roux

* 4 days week (university). == Issues == * none == Progress == * LRA on AArch32: o TCWG-343 : Make LRA the default for the ARM backend (3/10) - Looking backend places (ARM and AArch64) where reload_in_progress is used to verify if lra_in_progress is needed as well: Tested lot of configurations, testsuite results analysis ongoing. o TCWG-345 : Analyse performance of LRA for ARM. (0/10) - No progress this week. * GMP library AArch64 port review: (4/10) o Analyzing code generated from C generic implementation vs assembly. * Misc. (1/10) o Various meetings. == Next == * Child care (chickenpox) * Still some time spend at university * Continue on LRA and lib GMP

11 years, 7 months

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[ACTIVITY] 20 - 24 January 2014

by Omair Javaid

== Progress == * Implemented per process hwbreakpoint and watchpoint cache for arm native targets. Also added a reference count for per thread hardware breaks. [TCWG-177] [7/10] * Travelled to Islamabad for Macau visa application. [3/10] == Plan == * Continue work on forking/vforking hardware breakpoints support for arm-native. Tweak hardware breakpoint cache and thread breaks reference count to get it in sync with linux-native. [TCWG-177]

11 years, 7 months

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