[LLD]
Fixed interworking problem causing Thumb2 kernel not to
Some diagnosis of LLD problem when .ctor and .init_array initialisers are used.
[LLVM-MC]
Upstream reviews for some methods to avoid llvm-mc making symbols
inter-positionable that the code generator has assumed are not.
[Morello]
reviews.
[Other]
Clean up my Jira tickets so that they can be passed on or closed.
This is my last week as a Linaro assignee, will be going back to the
Arm as of next week. I've really enjoyed my time here, thank you for
having me.
Buildbots, busy week that took up most of spare time
- deploying timezone fix to containers
- a couple of weekend patches that broke Arm and AArch64 bisected and
followed up.
- difficult to track down stage-2 failure that was difficult to work
out whether there was a bug in clang, or a code-gen failure in the
backend, also made it harder to bisect. Turned out that it had caused
more easy to bisect failures in other projects and by the time I'd
found the patch it had been fixed.
[ClangBuiltLinux]
LLD's simplified interworking looks to be insufficient for the linux
kernel thumb-2 build. Got agreement with upstream on how to proceed.
Have a patch ready to send upstream.
A small amount of upstream review and bisecting some Linaro CI build
failure for the -fpatchable-functions feature in Clang-10. Looks to
have been resolved.
[VIRT-327 # Richard's upstream QEMU work ]
* tcg patch queue flush, including some VHE prereqs.
* target/hppa patch queue flushing.
* combined the two in-flight avr patch sets, hoping
to move that project to completion.
* patch review.
* target/s390x local variable "leak" fix,
to satisfy a static analyzer.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
* started rebasing, and addressing the collected
comments from v4 in December.
r~
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: debugging
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m: local
newlib/crt0 patches, patched simulator. Running various validation
configurations
* GCC upstream validation:
- reported a couple of failures/regressions
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ RTH's bug fix for the PAuth ComputePAC operation
+ patchset adding DMA support for Exynos4210 UARTs
- small patchset documenting the right way to conditionally run
expensive computations that are only needed for trace event output,
and updating a handful of places that used an older (worse) method
- more QEMU documentation conversion to rST; in particular wrote a
Sphinx 'hxtool' extension to handle pulling out fragments of documentation
from QEMU's '.hx' files which define and document command line options
thanks
-- PMM
hiI am progressing in the implementation of the proposal "GDB process record and replay with ARM Coresight" https://lists.linaro.org/pipermail/coresight/2019-July/003021.html
so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7). and I can collect the traces from the perf mmapped aux area.
For parsing them I needed to gather information about the cpu and etm registers. those are available in the events of type PERF_RECORD_AUXTRACE_INFO in the priv section. priv is a kind of "opaque" data structure where the layout is depending on the perf pmu drivers. the implementation of perf tool gives a good example to follow. I needed also to make a wrapper around opencsd library and again perf was offering a good example to follow.
those are good reasons to think about factoring out the functionality of parsing etm traces on linux system in a dedicated library that can be reused by other software, a kind of libcoresightperf.is there any plan or ongoing activities for such a library?
Kind RegardsZied Guermazi
== Progress ==
* More EuroLLVM submissions reviews
* More investigations into Morello bare metal debugging
* Started looking into updating lldb for the latest Morello architecture
changes
* Asked Adhemerval to look into PR44157
== Plan ==
* More Morello
* Keep an eye out for 10.0.0 - rc1
[VIRT-327 # Richard's upstream QEMU work ]
* Implement x86_64-linux-user vsyscall page,
which should keep Peter's pre-merge testing working.
* Another tcg queue pull without the bits that depend
on the vsyscall implementation above.
* Posted v2 of some fixes to -accel option processing.
* Posted v2 of some fixes to target/arm syn data syndrome bits.
* Wrote some test cases for a target/arm pauth sbox fix.
* Investigated a fix for memory layout of -static-pie binaries.
* Random patch review.
r~
