== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
~ Progress ~
* Three days off [6/10]
* TCWG-1050, GDB 8.0 release. [2/10]
Pushed in some patches fixing ARM reverse debugging bug.
Investigating a GDB internal error.
Review Python btrace stuff, still trying to make it more generic.
* Misc, [2/10], catch up emails
~ Plan ~
* TCWG-1050.
* Review IBM linux kernel awareness patches.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.03 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn246148 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246148
* Backport of [Bugfix] [AArch64] PR target/71112 ICE with -fpie on
aarch64 ILP32 big-endian
* Backport of [Bugfix] [AArch64] PR target/71727 -O3 -mstrict-align
produces code which assumes unaligned vector accesses work
* Backport of [Bugfix] [AArch64] PR target/78382 ICE when compiling on
aarch64 in ILP32 mode with traditional thread local storage and pic
* Backport of [AArch32] Add vfpv2 and neon-vfpv3
* Backport of [AArch32] Fix assembly comment syntax in -mprint-tune-info
* Backport of [AArch64] Add commandline support for -march=armv8.3-a
* Backport of [AArch64] Expand DImode constant stores to two SImode
stores when profitable
* Backport of [AArch64] Fix aarch64 PGO bootstrap
* Backport of [AArch64] Fix exception handling for ILP32 aarch64
* Backport of [AArch64] Have the verbose cost model output output be
controllable
* Backport of [AArch64] Implement popcount pattern
* Backport of [AArch64] Optimized implementation of search_line_fast
for the CPP lexer
* Backport of [AArch64] Use new target pass registration framework for
FMA steering pass
* Backport of [Testsuite] [AArch32] Add Cortex-A15 tuning to
gcc.dg/uninit-pred-8_a.c
* Backport of [Testsuite] [AArch32] Skip optional_mthumb tests if GCC
has a default mode
* Backport of [Testsuite] [AArch32] Updating testcase unsigned-extend-2.c
* Backport of [Testsuite] [AArch64] Fix
gcc.dg/torture/float32-builtin.c with RTL checking
* Backport of [Testsuite] [AArch64] PR middle-end/78142 more registers
to be used for on gcc.target/aarch64/vector_initialization_nostack.c
* Backport of [Cleanup] [AArch32] Define arm_arch_core_flags in a single file
* Backport of [Cleanup] [AArch32] Remove unimplemented option -macps-float
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 2 days out of office (Thursday & Friday)
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
- Committed support for GEPs and 32-bit constants, which enables us
to put call parameters on the stack
- Proposed a fix for an AArch64 issue where the size of the stack
was computed incorrectly if the last parameter was sign- or
zero-extended into a stack slot
* Misc
- Mailing list etc.
== Plan ==
* Connect
