Progress: * UM-2 [QEMU upstream maintainership] - Implemented Neoverse N2 CPU model (easy as it's very similar to the Cortex-A710 we just implemented; but because it supports 48 bit physical addresses we can use it in the sbsa-ref board, so it's worth having both) - Wrote code to wire up the NS EL2 virtual timer IRQ on the virt board. This is part of FEAT_VHE, and we implemented the timer itself in the CPU ages ago, but forgot to ever wire up the interrupt line on the board models. Unfortunately doing this runs into a bug in EDK2 where it incorrectly asserts when it sees a dtb that reports the interrupt line. Leif Lindholm wrote patches to fix this in EDK2, but we'll need to update the QEMU testsuite and figure out how to communicate the need for an updated EDK2 to users. - Looked again at a long-standing missing feature in the virt board where it only has one UART. The main blocker for adding a second one has been odd EDK2 behaviour when the dtb tells it there are two UARTs. Investigated and wrote up exactly what it does to start a discussion about improving it. - Put together a target-arm pull request - Squashed a few -Wshadow warnings - Looking at a bug involving QEMU's PSCI emulation when QEMU is faking being EL3 firmware for a Linux guest
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Implemented and sent a patch for FEAT_HPMN0 (a very easy feature that makes MDCR_EL2.HPMN==0 valid)
-- PMM