BTW, is hard float mode, are 64-bit integers passed in core-regs still? I expect so, since hard-float doesn't imply neon, but it would probably be a bonus if they were passed in neon registers.
They are still passed in the core registers . It would be worth noting in any case that the VFP and Neon unit share a common register bank. The hard-float ABI addendum doesn't make any assumptions about the presence of a Neon unit but it does assume the presence atleast of 16 DP registers.
and b) right shifts are encoded as left shift by a negative amount, and negative shift amounts are normally considered undefined behaviour.
But the behaviour is defined for NEON, and this only appears at the assembly level - you implement a right shift by constant as the left shift by negative constant in the assembly.
I'm not talking about shifts by constants, this is shifts by variable. True, GCC is probably more forgiving in that case because it's less able to reason about them, but if some value range propagation pass can determine that it's negative (now or in future) you never know what might happen.
Well you should never represent a right shift of a DImode quantity as a neg followed by a left shift in RTL. Instead you ought to be retaining the right shift for as long as possible (until reload) and then split it into a neg followed by an operation that is represented with an UNSPEC.
cheers Ramana