-----Original Message----- From: linaro-toolchain-bounces@lists.linaro.org [mailto:linaro- toolchain-bounces@lists.linaro.org] On Behalf Of Yvan Roux Sent: 21 February 2013 15:54 To: linaro-toolchain@lists.linaro.org Subject: AArch64 asm statement question
Hi,
in the example below I want to explicitly generate a "store exclusive pair" instruction with an asm statement:
typedef struct { long unsigned int v1; long unsigned int v2; } mtype;
int main () { mtype val[2] ; val[0].v1 = 1234; val[0].v2 = 5678; int status;
do { __asm__ __volatile__( " stxp %0, %2, %3, %1" : "=&r" (status), "=Q" (val[1]) : "r" (val[0].v1), "r" (val[0].v2) ); } while (status != 0);
if (val[1].v1 == 1234 && val[1].v2 == 5678) return 0; return 1; }
The generated assembly is:
.L7: ldr x0, [sp] ldr x1, [sp,8] .L3: add x3, sp, 16 stxp x2, x0, x1, [x3] cbnz w2, .L7
and the issue is that the assembler is not happy of the register x2 used to store the exclusive access status, it should be w2, but looking at constraint.md it seems that there is no constraint to say that we want the 32bit version of the register. Any idea ?
IIRC it's just printed out with %w or the equivalent in the punctuation character on AArch64. There is no need for a separate constraint for the w registers as W2 is the low half of X2 in the AArch64 there so if w2 is written the upper half of the x2 register is automatically zero'd out.
So stxp %w0, %2, %3, %1 in your inline asm or look out for how this is printed in the equivalent sync pattern. I'd look in iterators.md for some of the attributes to confirm this.
HTH Ramana
Many thanks Yvan
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