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[PATCH] Platforms/AMD/Styx: enable SMMUs in the ACPI IORT table

by Ard Biesheuvel

Due to the fact that AMD Seattle maps all its DRAM starting at physical address 0x80_0000_0000, we currently only support DMA for devices that can access 40 bits of physical address space. This is not a problem for the onboard devices, but it would be useful if we could support random PCIe plug-in cards, even if they are only 32-bit DMA capable. Fortunately, there is a ARM (tm) Corelink(r) MMU-401 between the PCIe root complex and the CPU bus, and so all we need to do is to inform the OS about this. So add a description of it to the APCI IORT table. While we're at it, let's describe all the other SMMUs we may be able to make use of, i.e., 2x SATA and 2x XGBE, as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Platforms/AMD/Styx/AcpiTables/Iort.c | 301 ++++++++++++++++++++ Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 1 + 4 files changed, 304 insertions(+) diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf index 12e0444009ef..3615d7fc0279 100644 --- a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf @@ -37,6 +37,7 @@ Mcfg.c Csrt.c Dsdt.c + Iort.c [Packages] ArmPkg/ArmPkg.dec diff --git a/Platforms/AMD/Styx/AcpiTables/Iort.c b/Platforms/AMD/Styx/AcpiTables/Iort.c new file mode 100644 index 000000000000..408149d59db9 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Iort.c @@ -0,0 +1,301 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <AmdStyxAcpiLib.h> +#include <IndustryStandard/IoRemappingTable.h> + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#define STYX_PCIE_SMMU_BASE 0xE0A00000 +#define STYX_PCIE_SMMU_SIZE 0x10000 +#define STYX_PCIE_SMMU_INTERRUPT 0x16d + +#define STYX_ETH0_SMMU_BASE 0xE0600000 +#define STYX_ETH0_SMMU_SIZE 0x10000 +#define STYX_ETH0_SMMU_INTERRUPT 0x170 + +#define STYX_ETH1_SMMU_BASE 0xE0800000 +#define STYX_ETH1_SMMU_SIZE 0x10000 +#define STYX_ETH1_SMMU_INTERRUPT 0x16f + +#define STYX_SATA0_SMMU_BASE 0xE0200000 +#define STYX_SATA0_SMMU_SIZE 0x10000 +#define STYX_SATA0_SMMU_INTERRUPT 0x16c + +#define STYX_SATA1_SMMU_BASE 0xE0C00000 +#define STYX_SATA1_SMMU_SIZE 0x10000 +#define STYX_SATA1_SMMU_INTERRUPT 0x16b + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1]; +} STYX_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; +} STYX_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[16]; +} STYX_NC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + STYX_SMMU_NODE PciSmmuNode; + STYX_RC_NODE PciRcNode; + +#if DO_XGBE + STYX_SMMU_NODE Eth0SmmuNode; + STYX_NC_NODE Eth0NamedNode; + STYX_SMMU_NODE Eth1SmmuNode; + STYX_NC_NODE Eth1NamedNode; +#endif + + STYX_SMMU_NODE Sata0SmmuNode; + STYX_NC_NODE Sata0NamedNode; + STYX_SMMU_NODE Sata1SmmuNode; + STYX_NC_NODE Sata1NamedNode; +} STYX_IO_REMAPPING_STRUCTURE; + +#define __STYX_SMMU_NODE(Base, Size, Irq) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_SMMUv1v2, \ + sizeof(STYX_SMMU_NODE), \ + 0x0, \ + 0x0, \ + 0x0, \ + 0x0, \ + }, \ + Base, \ + Size, \ + EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \ + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ + SMMU_NSgIrpt), \ + 0x1, \ + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ + 0x0, \ + 0x0, \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + 0x0, \ + 0x0, \ + }, { \ + { \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + }, \ + } + +#define __STYX_ID_MAPPING(In, Num, Out, Flags, Ref) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +#define __STYX_NAMED_COMPONENT_NODE(Name) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_NAMED_COMP, \ + sizeof(STYX_NC_NODE), \ + 0x0, \ + 0x0, \ + 0x10, \ + FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \ + }, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \ + 0x0, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \ + 40, \ + }, \ + Name + +STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + STYX_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), +#if DO_XGBE + 10, // NumNodes +#else + 6, // NumNodes +#endif + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // PciSmmuNode + __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE, + STYX_PCIE_SMMU_SIZE, + STYX_PCIE_SMMU_INTERRUPT) + }, { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof(STYX_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, { + __STYX_ID_MAPPING(0x0, 0xffff, 0x0, 0x0, PciSmmuNode), + } +#if DO_XGBE + }, { + // Eth0SmmuNode + __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE, + STYX_ETH0_SMMU_SIZE, + STYX_ETH0_SMMU_INTERRUPT) + }, { + // Eth0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"), + { + __STYX_ID_MAPPING(0x0, 0x0, 0x00, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x01, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x02, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x03, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x04, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x05, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x06, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x07, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x10, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x11, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x12, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x13, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x14, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x15, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x16, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x17, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth0SmmuNode), + } + }, { + // Eth1SmmuNode + __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE, + STYX_ETH1_SMMU_SIZE, + STYX_ETH1_SMMU_INTERRUPT) + }, { + // Eth1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"), + { + __STYX_ID_MAPPING(0x0, 0x0, 0x00, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x01, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x02, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x03, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x04, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x05, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x06, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x07, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x10, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x11, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x12, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x13, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x14, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x15, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x16, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x17, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Eth1SmmuNode), + } +#endif + }, { + // Sata0SmmuNode + __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE, + STYX_SATA0_SMMU_SIZE, + STYX_SATA0_SMMU_INTERRUPT) + }, { + // Sata0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"), + { + __STYX_ID_MAPPING(0x0, 0x0, 0x00, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x01, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x02, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x03, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x04, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x05, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x06, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x07, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x10, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x11, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x12, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x13, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x14, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x15, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x16, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x17, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata0SmmuNode), + } + }, { + // Sata1SmmuNode + __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE, + STYX_SATA1_SMMU_SIZE, + STYX_SATA1_SMMU_INTERRUPT) + }, { + // Sata1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"), + { + __STYX_ID_MAPPING(0x0, 0x0, 0x00, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x01, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x02, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x03, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x04, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x05, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x06, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x07, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x10, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x11, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x12, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x13, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x14, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x15, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x16, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + __STYX_ID_MAPPING(0x0, 0x0, 0x17, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, Sata1SmmuNode), + } + } +}; + +#pragma pack() + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 + +EFI_ACPI_DESCRIPTION_HEADER * +IortHeader ( + VOID + ) +{ + if (FixedPcdGet8 (PcdSata1PortCount) == 0 || + (PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + + // ignore the last two nodes if Sata1 is not enabled + AcpiIort.Iort.NumNodes -= 2; + } + return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiIort.Iort.Header; +} diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h index 698a5d3f90f8..9438b8b0c27e 100644 --- a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -27,6 +27,7 @@ EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 1bad597a8eaa..8efb5ccfd8b7 100644 --- a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -65,6 +65,7 @@ AcpiPlatformEntryPoint ( AcpiTableList[TableIndex++] = SpcrHeader(); AcpiTableList[TableIndex++] = McfgHeader(); AcpiTableList[TableIndex++] = CsrtHeader(); + AcpiTableList[TableIndex++] = IortHeader(); AcpiTableList[TableIndex++] = NULL; DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); -- 2.9.3

7 years, 8 months

[PATCH] Drivers: MarvellYukonDxe driver binding fixes

by Leif Lindholm

Fix a case where MarvellYukonDriverStart attempted to free a buffer before it was allocated. Fix another case where the function returned without freeing the same buffer. Also correct the error message for that case, which was copied verbatim from the preceding if-statement. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm(a)linaro.org> --- Drivers/Net/MarvellYukonDxe/DriverBinding.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Drivers/Net/MarvellYukonDxe/DriverBinding.c b/Drivers/Net/MarvellYukonDxe/DriverBinding.c index 947d738b10..cbe8ad34e4 100644 --- a/Drivers/Net/MarvellYukonDxe/DriverBinding.c +++ b/Drivers/Net/MarvellYukonDxe/DriverBinding.c @@ -127,7 +127,6 @@ MarvellYukonDriverStart ( if (EFI_ERROR (Status)) { DEBUG ((EFI_D_ERROR, "Marvell Yukon: OpenProtocol: EFI_PCI_IO_PROTOCOL ERROR Status = %r\n", Status)); - gBS->FreePool (YukonDriver); return Status; } @@ -156,7 +155,8 @@ MarvellYukonDriverStart ( } if (ScData->msk_if[Port] == NULL) { - DEBUG ((DEBUG_ERROR, "Marvell Yukon: AllocatePool() failed with Status = %r\n", EFI_BAD_BUFFER_SIZE)); + DEBUG ((DEBUG_ERROR, "Marvell Yukon: invalid buffer size\n")); + gBS->FreePool (YukonDriver); return EFI_BAD_BUFFER_SIZE; } -- 2.11.0

7 years, 8 months

[PATCH] Platforms/ARM/Juno: fix RELEASE build with new PciHostBridgeLib

by Leif Lindholm

An array of static strings is set up for use in printing debug messages. This makes some compilers unhappy when building in RELEASE mode. So hide the definition behind #ifndef MDE_NDEBUG. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm(a)linaro.org> --- Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c index f5cb254465..5263a2985d 100644 --- a/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c +++ b/Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c @@ -138,9 +138,11 @@ PciHostBridgeFreeRootBridges ( } +#ifndef MDEPKG_NDEBUG STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { L"Mem", L"I/O", L"Bus" }; +#endif /** Inform the platform that the resource conflict happens. -- 2.11.0

7 years, 8 months

[PATCH] Platforms/AMD/Styx: fix duplicate typedef in AmdIscpDxe

by Leif Lindholm

The struct _AMD_ISCP_DXE_PROTOCOL is given an early typedef, only to be defined as "typedef struct _AMD_ISCP_DXE_PROTOCOL..." later on. Delete the duplication. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm(a)linaro.org> --- .../AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h index 5daeb0cbc2..50db778453 100644 --- a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h @@ -279,7 +279,6 @@ EFI_STATUS *---------------------------------------------------------------------------------------- */ /// ISCP DXE Protocol Structure -typedef struct _AMD_ISCP_DXE_PROTOCOL { AMD_EXECUTE_CPU_CORE_RESET AmdExecuteCpuCoreReset; ///< Execute CPU Core Reset AMD_EXECUTE_CPU_RETRIEVE_ID AmdExecuteCpuRetrieveId; ///< Execute CPU Retrieve ID @@ -304,6 +303,6 @@ struct _AMD_ISCP_DXE_PROTOCOL { AMD_EXECUTE_BMC_PRESENT AmdExecuteBmcPresent; ///< Execute BMC presence check AMD_EXECUTE_RETRIEVE_BERT_RECORD AmdExecuteRetrieveBertRecord; ///< Execute Retrieve Boot Error Record AMD_EXECUTE_REGISTER_ERROR_SOURCE AmdExecuteRegisterErrorSource; ///< Execute Register Generic Hardware Error Source -} AMD_ISCP_DXE_PROTOCOL; +}; #endif //_AMD_ISCP_DXE_PROTOCOL_H_ -- 2.11.0

7 years, 8 months

[PATCH v2 0/2] Platforms/AMD: fix legacy interrupt routing

by Ard Biesheuvel

Update the DTS and ACPI descriptions with correct information about the routing of legacy interrupts. For DT, this comes down to updating the interrupt-map with distinct sets of 4 GIC interrupt lines per PCIe slot. For ACPI, we need to update the PNP0A08 node and add three companion devices, one for each slot, whose _PRT methods describe the legacy interrupt routing of each respective slot. The _PRT method at the root of the PCI ACPI hierarchy is updated to map INTA (which is shared by all functions of the bridge device) to GIC interrupt #320. With this change, the boot log is free of warnings and non-MSI capable devices work as expected. Tested on Cello with xhci_hcd.quirks=64 passed on the kernel command line, in which case the xhci interrupt is routed to GIC interrupt #324 Ard Biesheuvel (2): Platforms/AMD: correct legacy PCI interrupt routing in DSDT Platforms/AMD: correct legacy PCI interrupt routing in DTS Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 63 +++++++++++--------- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 7973 -> 8123 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 20 +++++-- 3 files changed, 49 insertions(+), 34 deletions(-) -- 2.9.3

7 years, 8 months

[PATCH] Hisilicon: Fix ACPI/DSDT table checksum error

by Chenhui Sun

Refresh checksum after changing DSDT table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo(a)linaro.org> Signed-off-by: Yi Li <phoenix.liyi(a)huawei.com> Signed-off-by: Chenhui Sun <chenhui.sun(a)linaro.org> --- Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c index 41f5692..1f74d31 100644 --- a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c +++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c @@ -442,6 +442,29 @@ static EFI_STATUS ProcessDSDT( return EFI_SUCCESS; } +STATIC +VOID +AcpiCheckSum ( + IN OUT EFI_ACPI_SDT_HEADER *Table + ) +{ + UINTN ChecksumOffset; + UINT8 *Buffer; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + Buffer = (UINT8 *)Table; + + // + // set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Table->Length); +} + EFI_STATUS EthMacInit(void) { EFI_STATUS Status; @@ -478,6 +501,7 @@ EFI_STATUS EthMacInit(void) ProcessDSDT(AcpiTableProtocol, TableHandle); AcpiTableProtocol->Close(TableHandle); + AcpiCheckSum (Table); } return EFI_SUCCESS; -- 1.9.1

7 years, 8 months

[PATCH 1/2] Chips/Hisilicon: add missing UefiBootManagerLib resolution to shared .inc

by Ard Biesheuvel

Upstream EDK2 changes now require platforms that build the UEFI Shell from source to provide a resolution for UefiBootManagerLib, and some other library class it transitively depends on. So add them to the DSC include shared between the HiSilicon platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Chips/Hisilicon/Hisilicon.dsc.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Chips/Hisilicon/Hisilicon.dsc.inc b/Chips/Hisilicon/Hisilicon.dsc.inc index d856a659a8fb..716900874274 100644 --- a/Chips/Hisilicon/Hisilicon.dsc.inc +++ b/Chips/Hisilicon/Hisilicon.dsc.inc @@ -198,7 +198,12 @@ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf [LibraryClasses.common.UEFI_DRIVER] ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf -- 2.9.3

7 years, 8 months

[PATCH v3 0/6] Platforms/ARM: FVP spring cleaning -- OpenPlatformPkg edition

by Ard Biesheuvel

This is now mainly focused on FVP, although some changes affect TC2 and Juno as well. However, the switch to DtPlatformDxe, which is the primary purpose of this series, is only implemented for FVP. Note that the full functionality is only enabled when building with DT_SUPPORT=TRUE, in which case the platform is built with a bunch of DTB images built in, and a menu option that allows choosing between ACPI and DT (which does require working non-volatile storage). Without DT support, the platform is essentially ACPI only, unless a DTB is supplied to the OS via one of the available out-of-band mechanisms. Ard Biesheuvel (6): Platforms/VExpress: remove unused logo PCD Platforms/VExpress: remove unused StatusCode references Platforms/VExpress: get rid of Tiano compression Platforms/VExpress: remove BdsLib library class resolutions Platforms/FVP: add DtPlatformDtbLoaderLib implementation Platforms/FVP-AArch64: switch to simpler DT platform driver Platforms/ARM/Juno/ArmJuno.dsc | 8 ++ Platforms/ARM/Juno/ArmJuno.fdf | 9 -- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 13 +- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.fdf | 16 --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 33 ++--- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 54 ++------ Platforms/ARM/VExpress/ArmVExpress.dsc.inc | 24 +--- Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c | 134 ++++++++++++++++++++ Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf | 39 ++++++ 9 files changed, 221 insertions(+), 109 deletions(-) create mode 100644 Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.c create mode 100644 Platforms/ARM/VExpress/Library/ArmVExpressDtPlatformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf -- 2.9.3

7 years, 8 months

[PATCH] Platforms/Marvell/Armada: remove ARM BdsLib resolution

by Ard Biesheuvel

The EBL shell nog longer depends on the deprecated ARM BdsLib, so remove the library class resolution for it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/Marvell/Armada/Armada.dsc.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platforms/Marvell/Armada/Armada.dsc.inc b/Platforms/Marvell/Armada/Armada.dsc.inc index bdaf53710d9b..475fc6d05379 100644 --- a/Platforms/Marvell/Armada/Armada.dsc.inc +++ b/Platforms/Marvell/Armada/Armada.dsc.inc @@ -128,7 +128,6 @@ # SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf # BDS Libraries - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf -- 2.9.3

7 years, 8 months

[Linaro-uefi v3 0/3] D03/D05 platforms bug fix

by Chenhui Sun

ode can also be found in linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-04 Mainly include * refine the code style according Leif's comments * drop the "Hisilicon: Fix ACPI/DSDT table checksum error" path this time, and will send out after ERP17.04 Chenhui Sun (2): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature shaochangliang (1): Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++++++++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + 3 files changed, 191 insertions(+), 2 deletions(-) -- 1.9.1

7 years, 8 months

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