Linaro-uefi

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811 discussions

by Marcin Wojtas

Hi, I submit a series of patches adding analog parameters configuration sequences for Sata and Pcie, 10G link (SFI + RXAUI) initalization and 2 minor improvements. Also first part of PCD rework is added, moving the controllers description to MvHwDescLib. Per-board lanes description new implementation will be submitted after this one. The commits are also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any remarks or comments will be very welcome. Best regards, Marcin Marcin Wojtas (6): Platform/Marvell: ComPhyLib: Cleanup and fix SerDes lanes assignment Platform/Marvell: ComPhyLib: Mark failing lane as unconnected Platform/Marvell: ComPhyLib: Configure analog parameters for SATA Platform/Marvell: ComPhyLib: Configure analog parameters for PCIE Platform/Marvell: ComPhyLib: Add missing SFI and RXAUI configuration Platform/Marvell: ComPhyLib: Move devices description to MvHwDescLib Documentation/Marvell/PortingGuide/ComPhy.txt | 60 +- Platforms/Marvell/Armada/Armada70x0.dsc | 13 +- Platforms/Marvell/Include/Library/MvComPhyLib.h | 5 + Platforms/Marvell/Include/Library/MvHwDescLib.h | 38 + Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 886 +++++++++++++++++++++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 96 ++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 318 +++++++- Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 26 +- Platforms/Marvell/Marvell.dec | 28 +- 9 files changed, 1278 insertions(+), 192 deletions(-) -- 1.8.3.1

7 years, 8 months

[Linaro-uefi v3 0/3] D03/D05 platforms bug fix

by Chenhui Sun

ode can also be found in linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-04 Mainly include * refine the code style according Leif's comments * drop the "Hisilicon: Fix ACPI/DSDT table checksum error" path this time, and will send out after ERP17.04 Chenhui Sun (2): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature shaochangliang (1): Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++++++++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + 3 files changed, 191 insertions(+), 2 deletions(-) -- 1.9.1

7 years, 8 months

[Linaro-uefi v2 00/17] D03/D05 platforms bug fix

by Chenhui Sun

Code can also be found in inaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-17.04-03 Mainly include * fix SCT test fail issue * fix luvOS test fail issue * support the compatibility of kernel PCIe driver * refine the code style according Leif and Graeme's comments * drop some unnessary and some wrong patchset at v1 Chenhui Sun (6): Hisilicon: disable RC Option Rom Hisilicon: Add reconfig lane number feature Hisilicon/D03/D05: Change Monotonic Drive D03: update acpi tables to ACPI6.1 D05: update acpi tables to ACPI6.1 D02: update acpi tables to ACPI6.1 hensonwang (3): Hisilicon/D05: support the compatibility of kernel PCIe driver Hisilicon/D03: support the compatibility of kernel PCIe driver Hisilicon/D05: add num-pins package for Roce shaochangliang (2): Hisilicon/UpdateFdtDxe: fix memory overflow issue Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. wangyue (6): Hisilicon: Fix ACPI/DSDT table checksum error Hisilicon/D02: fix IORT test issue in luvOS test Hisilicon/D03: Fix IORT test issue in luvOS test Hisilicon/D05: Fix IORT test issue in luvOS test Hisilicon/FlashFvbDxe: Add Reset interface for block IO protocol Hisilicon/RamDisk: Add Reset interface for block IO protocol Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++ Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 13 + .../Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 184 ++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 + .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 +- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 +- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 159 ++++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 +++--- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 7 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 399 ++++++++++++++++++- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 28 +- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- Drivers/Block/ramdisk/ramdisk.c | 13 + Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 38 files changed, 1335 insertions(+), 698 deletions(-) -- 1.9.1

7 years, 8 months

[PATCH 1/2] Platforms/AMD: correct legacy PCI interrupt routing in DSDT

by Ard Biesheuvel

The _PRT method in the PCI0 object describes something that resembles the legacy interrupt routing of the first slot only, but applies it to all PCI-PCI bridges, which means the wrong interrupt is reported for devices in slots 2 and 3. Since most devices support MSI, this is not actually a big deal, but it would be nice to fix this nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/AcpiTables/Dsdt.asl | 52 +++++++------------- 1 file changed, 19 insertions(+), 33 deletions(-) diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl index 3bfa26acea07..49ef55fc7df6 100644 --- a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -508,39 +508,25 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) Name (_SEG, 0x00) // _SEG: PCI Segment Name (_BBN, 0x00) // _BBN: BIOS Bus Number Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute - Name (_PRT, Package (0x04) // _PRT: PCI Routing Table - { - Package (0x04) - { - 0xFFFF, - 0x00, - 0x00, - 0x0140 - }, - - Package (0x04) - { - 0xFFFF, - 0x01, - 0x00, - 0x0141 - }, - - Package (0x04) - { - 0xFFFF, - 0x02, - 0x00, - 0x0142 - }, - - Package (0x04) - { - 0xFFFF, - 0x03, - 0x00, - 0x0143 - } + Name (_PRT, Package () // _PRT: PCI Routing Table + { + // slot 1: dev 2 fn 1 + Package () { 0x20001, 0x0, 0x0, 0x140 }, + Package () { 0x20001, 0x1, 0x0, 0x141 }, + Package () { 0x20001, 0x2, 0x0, 0x142 }, + Package () { 0x20001, 0x3, 0x0, 0x143 }, + + // slot 2: dev 2 fn 2 + Package () { 0x20002, 0x0, 0x0, 0x144 }, + Package () { 0x20002, 0x1, 0x0, 0x145 }, + Package () { 0x20002, 0x2, 0x0, 0x146 }, + Package () { 0x20002, 0x3, 0x0, 0x147 }, + + // slot 3: dev 2 fn 3 + Package () { 0x20003, 0x0, 0x0, 0x148 }, + Package () { 0x20003, 0x1, 0x0, 0x149 }, + Package () { 0x20003, 0x2, 0x0, 0x14a }, + Package () { 0x20003, 0x3, 0x0, 0x14b } }) // _PRT Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings -- 2.9.3

7 years, 8 months

How to build aarch64 UEFI on Windows?

by Heyi Guo

Hi folks, I can see Linaro is Linux oriented, but most of my colleagues are much more familiar with Windows and Source Insight, rather than Linux and vim/emacs. We may be happier and more effective if we can build aarch64 UEFI on Windows directly. So how can we do that? Is there any detailed guideline? Thanks and regards, Gary (Heyi Guo)

7 years, 8 months

[PATCH v2] Platforms/AMD: implement DtPlatformDtbLoaderLib

by Ard Biesheuvel

In order to be able to switch to the generic DtPlatformDxe driver, implement the glue library that loads it and prepares it based on the properties of the actual hardware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 481 ++++++++++++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 64 +++ 2 files changed, 545 insertions(+) diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c new file mode 100644 index 000000000000..b18caf19985b --- /dev/null +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -0,0 +1,481 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PiDxe.h> + +#include <Guid/ArmMpCoreInfo.h> + +#include <libfdt.h> +#include <Library/ArmLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PrintLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/AmdMpCoreInfo.h> + +#define PMU_INT_FLAG_SPI 0 +#define PMU_INT_TYPE_HIGH_LEVEL 4 + +// +// PMU interrupts per core +// +#pragma pack(push, 1) +typedef struct { + UINT32 Flag; // 0 == SPI + UINT32 IntId; // GSIV == IntId+32 + UINT32 Type; // 4 == Level-Sensitive, Active-High +} PMU_INTERRUPT; +#pragma pack(pop) + +STATIC +BOOLEAN +ClusterInRange ( + IN ARM_CORE_INFO *ArmCoreInfoTable, + IN UINTN ClusterId, + IN UINTN LowIndex, + IN UINTN HighIndex + ) +{ + do { + if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId) + return TRUE; + } while (++LowIndex <= HighIndex); + + return FALSE; +} + + +STATIC +UINTN +NumberOfCoresInCluster ( + IN ARM_CORE_INFO *ArmCoreInfoTable, + IN UINTN NumberOfEntries, + IN UINTN ClusterId + ) +{ + UINTN Index, Cores; + + Cores = 0; + for (Index = 0; Index < NumberOfEntries; ++Index) { + if (ClusterId == ArmCoreInfoTable[Index].ClusterId) + ++Cores; + } + + return Cores; +} + + +STATIC +UINTN +NumberOfClustersInTable ( + IN ARM_CORE_INFO *ArmCoreInfoTable, + IN UINTN NumberOfEntries + ) +{ + UINTN Index, Cores, Clusters, ClusterId; + + Index = 0; + Clusters = 0; + Cores = NumberOfEntries; + while (Cores) { + ++Clusters; + ClusterId = ArmCoreInfoTable[Index].ClusterId; + Cores -= NumberOfCoresInCluster (ArmCoreInfoTable, + NumberOfEntries, + ClusterId); + if (Cores) { + do { + ++Index; + } while (ClusterInRange (ArmCoreInfoTable, + ArmCoreInfoTable[Index].ClusterId, + 0, Index-1)); + } + } + + return Clusters; +} + + +STATIC +INT32 +fdt_alloc_phandle ( + IN VOID *Fdt + ) +{ + INT32 Offset; + INT32 Phandle; + + Phandle = 0; + + for (Offset = fdt_next_node (Fdt, -1, NULL); Offset >= 0; + Offset = fdt_next_node (Fdt, Offset, NULL)) { + Phandle = MAX (Phandle, fdt_get_phandle (Fdt, Offset)); + } + + return Phandle + 1; +} + +STATIC +VOID +SetDeviceStatus ( + IN VOID *Fdt, + IN CONST CHAR8 *Device, + IN BOOLEAN Enable + ) +{ + INT32 Node; + INT32 SubNode; + INT32 Rc; + + Node = fdt_subnode_offset (Fdt, 0, "smb"); + if (Node >= 0) { + SubNode = fdt_subnode_offset (Fdt, Node, Device); + if (SubNode >= 0) { + Rc = fdt_setprop_string (Fdt, SubNode, "status", + Enable ? "okay" : "disabled"); + if (Rc) { + DEBUG ((DEBUG_ERROR, + "%a: Could not set 'status' property for '%a' node\n", + __FUNCTION__, Device)); + } + } + } +} + +#if DO_XGBE + +#define MAC_ADDRESS_BYTES 6 + +STATIC +VOID +SetMacAddress ( + IN VOID *Fdt, + IN CONST CHAR8 *Device, + IN UINT64 MacAddress + ) +{ + INT32 Node; + INT32 SubNode; + INT32 Rc; + + Node = fdt_subnode_offset (Fdt, 0, "smb"); + if (Node >= 0) { + SubNode = fdt_subnode_offset (Fdt, Node, Device); + if (SubNode >= 0) { + Rc = fdt_setprop (Fdt, SubNode, "mac-address", (VOID *)&MacAddress, + MAC_ADDRESS_BYTES); + if (Rc) { + DEBUG ((DEBUG_ERROR, + "%a: Could not set 'mac-address' property for '%a' node\n", + __FUNCTION__, Device)); + } + } + } +} + +#endif + +#define STYX_SOC_VERSION_MASK 0xFFF +#define STYX_SOC_VERSION_A0 0x000 +#define STYX_SOC_VERSION_B0 0x010 +#define STYX_SOC_VERSION_B1 0x011 + +STATIC +VOID +SetSocIdStatus ( + IN VOID *Fdt + ) +{ + UINT32 SocId; + BOOLEAN IsRevB1; + + SocId = PcdGet32 (PcdSocCpuId); + IsRevB1 = (SocId & STYX_SOC_VERSION_MASK) >= STYX_SOC_VERSION_B1; + + SetDeviceStatus (Fdt, "sata@e0d00000", + IsRevB1 && FixedPcdGet8 (PcdSata1PortCount) > 0); + SetDeviceStatus (Fdt, "gpio@e0020000", IsRevB1); + SetDeviceStatus (Fdt, "gpio@e0030000", IsRevB1); + SetDeviceStatus (Fdt, "gwdt@e0bb0000", IsRevB1); +#if DO_KCS + SetDeviceStatus (Fdt, "kcs@e0010000", IsRevB1); +#else + SetDeviceStatus (Fdt, "kcs@e0010000", FALSE); +#endif +} + +STATIC +VOID +SetXgbeStatus ( + IN VOID *Fdt + ) +{ +#if DO_XGBE + SetDeviceStatus (Fdt, "xgmac@e0700000", TRUE); + SetDeviceStatus (Fdt, "phy@e1240800", TRUE); + SetDeviceStatus (Fdt, "xgmac@e0900000", TRUE); + SetDeviceStatus (Fdt, "phy@e1240c00", TRUE); + + SetMacAddress (Fdt, "xgmac@e0700000", PcdGet64 (PcdEthMacA)); + SetMacAddress (Fdt, "xgmac@e0900000", PcdGet64 (PcdEthMacB)); +#else + SetDeviceStatus (Fdt, "xgmac@e0700000", FALSE); + SetDeviceStatus (Fdt, "phy@e1240800", FALSE); + SetDeviceStatus (Fdt, "xgmac@e0900000", FALSE); + SetDeviceStatus (Fdt, "phy@e1240c00", FALSE); +#endif +} + + +STATIC +EFI_STATUS +PrepareFdt ( + IN OUT VOID *Fdt, + IN UINTN FdtSize + ) +{ + EFI_STATUS Status; + INT32 Node; + INT32 CpuNode; + UINTN Index; + ARM_CORE_INFO *ArmCoreInfoTable; + UINTN ArmCoreCount; + INT32 MapNode; + INT32 ClusterNode; + INT32 PmuNode; + PMU_INTERRUPT PmuInt; + INT32 Phandle[NUM_CORES]; + UINT32 ClusterIndex; + UINT32 CoreIndex; + UINT32 ClusterCount; + UINT32 CoresInCluster; + UINT32 ClusterId; + UINTN MpId; + CHAR8 Name[10]; + AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol; + + // + // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms. + // + // For 'cpus' and 'cpu' device tree nodes bindings, refer to this file + // in the kernel documentation: + // Documentation/devicetree/bindings/arm/cpus.txt + // + Status = gBS->LocateProtocol ( + &gAmdMpCoreInfoProtocolGuid, + NULL, + (VOID **)&AmdMpCoreInfoProtocol + ); + ASSERT_EFI_ERROR (Status); + + // Get pointer to ARM core info table + ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount); + ASSERT (ArmCoreInfoTable != NULL); + ASSERT (ArmCoreCount <= NUM_CORES); + + // Get Id from primary CPU + MpId = (UINTN)ArmReadMpidr (); + + // Create /pmu node + PmuNode = fdt_add_subnode(Fdt, 0, "pmu"); + if (PmuNode >= 0) { + fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3"); + + // append PMU interrupts + for (Index = 0; Index < ArmCoreCount; Index++) { + MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, + ArmCoreInfoTable[Index].CoreId); + + Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId)); + return Status; + } + + PmuInt.Flag = cpu_to_fdt32 (PMU_INT_FLAG_SPI); + PmuInt.IntId = cpu_to_fdt32 (PmuInt.IntId); + PmuInt.Type = cpu_to_fdt32 (PMU_INT_TYPE_HIGH_LEVEL); + fdt_appendprop (Fdt, PmuNode, "interrupts", &PmuInt, sizeof(PmuInt)); + } + } else { + DEBUG ((DEBUG_ERROR, "FDT: Error creating 'pmu' node\n")); + return EFI_INVALID_PARAMETER; + } + + // Create /cpus noide + Node = fdt_add_subnode (Fdt, 0, "cpus"); + if (Node >= 0) { + // Configure the 'cpus' node + fdt_setprop_string (Fdt, Node, "name", "cpus"); + fdt_setprop_cell (Fdt, Node, "#address-cells", sizeof (UINTN) / 4); + fdt_setprop_cell (Fdt, Node, "#size-cells", 0); + } else { + DEBUG ((DEBUG_ERROR, "FDT: Error creating 'cpus' node\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Walk the processor table in reverse order for proper listing in FDT + // + Index = ArmCoreCount; + while (Index--) { + // Create 'cpu' node + AsciiSPrint (Name, sizeof (Name), "CPU%d", Index); + CpuNode = fdt_add_subnode (Fdt, Node, Name); + if (CpuNode < 0) { + DEBUG ((DEBUG_ERROR, "FDT: Error on creating '%a' node\n", Name)); + return EFI_INVALID_PARAMETER; + } + Phandle[Index] = fdt_alloc_phandle (Fdt); + fdt_setprop_cell (Fdt, CpuNode, "phandle", Phandle[Index]); + fdt_setprop_cell (Fdt, CpuNode, "linux,phandle", Phandle[Index]); + + fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci"); + + MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, + ArmCoreInfoTable[Index].CoreId); + MpId = cpu_to_fdt64 (MpId); + fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId)); + fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,armv8"); + fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu"); + } + + // Create /cpu-map node + MapNode = fdt_add_subnode (Fdt, Node, "cpu-map"); + if (MapNode >= 0) { + ClusterIndex = ArmCoreCount - 1; + ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable, + ArmCoreCount); + while (ClusterCount--) { + // Create 'cluster' node + AsciiSPrint (Name, sizeof (Name), "cluster%d", ClusterCount); + ClusterNode = fdt_add_subnode (Fdt, MapNode, Name); + if (ClusterNode < 0) { + DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name)); + return EFI_INVALID_PARAMETER; + } + + ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId; + CoreIndex = ClusterIndex; + CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable, + ArmCoreCount, + ClusterId); + while (CoresInCluster--) { + // Create 'core' node + AsciiSPrint (Name, sizeof (Name), "core%d", CoresInCluster); + CpuNode = fdt_add_subnode (Fdt, ClusterNode, Name); + if (CpuNode < 0) { + DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name)); + return EFI_INVALID_PARAMETER; + } + fdt_setprop_cell (Fdt, CpuNode, "cpu", Phandle[CoreIndex]); + + // iterate to next core in cluster + if (CoresInCluster) { + do { + --CoreIndex; + } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId); + } + } + + // iterate to next cluster + if (ClusterCount) { + do { + --ClusterIndex; + } while (ClusterInRange (ArmCoreInfoTable, + ArmCoreInfoTable[ClusterIndex].ClusterId, + ClusterIndex + 1, + ArmCoreCount - 1)); + } + } + } else { + DEBUG ((DEBUG_ERROR,"FDT: Error creating 'cpu-map' node\n")); + return EFI_INVALID_PARAMETER; + } + + SetSocIdStatus (Fdt); + SetXgbeStatus (Fdt); + + // Update the real size of the Device Tree + fdt_pack (Fdt); + + return EFI_SUCCESS; +} + + +/** + Return a pool allocated copy of the DTB image that is appropriate for + booting the current platform via DT. + + @param[out] Dtb Pointer to the DTB copy + @param[out] DtbSize Size of the DTB copy + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_NOT_FOUND No suitable DTB image could be located + @retval EFI_OUT_OF_RESOURCES No pool memory available + +**/ +EFI_STATUS +EFIAPI +DtPlatformLoadDtb ( + OUT VOID **Dtb, + OUT UINTN *DtbSize + ) +{ + EFI_STATUS Status; + VOID *OrigDtb; + VOID *CopyDtb; + UINTN OrigDtbSize; + UINTN CopyDtbSize; + INT32 Error; + + Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, 0, &OrigDtb, &OrigDtbSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + // + // Allocate space for the DTB: add a page of slack space to make some room + // for our modifications. + // + CopyDtbSize = OrigDtbSize + EFI_PAGE_SIZE; + CopyDtb = AllocatePool (CopyDtbSize); + if (CopyDtb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Error = fdt_open_into (OrigDtb, CopyDtb, CopyDtbSize); + if (Error != 0) { + // + // fdt_open_into() validates the DTB header, so if it fails, the template + // is most likely invalid. + // + return EFI_NOT_FOUND; + } + + Status = PrepareFdt (CopyDtb, CopyDtbSize); + if (EFI_ERROR (Status)) { + return Status; + } + + *Dtb = CopyDtb; + *DtbSize = CopyDtbSize; + + return EFI_SUCCESS; +} diff --git a/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf new file mode 100644 index 000000000000..f5ba5f1d1335 --- /dev/null +++ b/Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = StyxDtbLoaderLib + FILE_GUID = 3874890c-2917-46a6-8711-8fcaee92260a + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = DtPlatformDtbLoaderLib|DXE_DRIVER + +[Sources] + StyxDtbLoaderLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + AmdModulePkg/AmdModulePkg.dec + OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec + +[LibraryClasses] + ArmLib + BaseLib + DebugLib + DxeServicesLib + FdtLib + MemoryAllocationLib + PrintLib + UefiBootServicesTableLib + +[Pcd] + gAmdStyxTokenSpaceGuid.PcdStyxFdt + gAmdStyxTokenSpaceGuid.PcdSocCpuId + gAmdStyxTokenSpaceGuid.PcdEthMacA + gAmdStyxTokenSpaceGuid.PcdEthMacB + gArmTokenSpaceGuid.PcdSystemMemoryBase + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment + gAmdStyxTokenSpaceGuid.PcdPsciOsSupport + gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport + gAmdStyxTokenSpaceGuid.PcdSata1PortCount + +[Guids] + gDtPlatformDefaultDtbFileGuid + +[Protocols] + gAmdMpCoreInfoProtocolGuid ## CONSUMED + +[Depex] + gAmdMpCoreInfoProtocolGuid -- 2.9.3

7 years, 8 months

[PATCH 0/8] Platforms/AMD/Overdrive: switch to DtPlatformDxe

by Ard Biesheuvel

The FdtDxe implementation that lives in Platforms/AMD/Styx is a rather unhealthy mix of fossilized pieces of LinuxLoader combined with other dependencies on the deprecated ARM BdsLib. Since it does lots of things we don't need (involving memory DT nodes and other bits we don't use), and doesn't do what we do need (select between ACPI and DT but not enable both at the same time), it is time to get rid of it. So implement a DtPlatformDtbLoaderLib based on the pieces we want to keep, and switch Overdrive and Overdrive 1000 to use it, and finally remove FdtDxe altogether. Ard Biesheuvel (8): Platforms/AMD: remove /pmu node from Overdrive 1000 DTS Platforms/AMD: clean up whitespace in Overdrive 1000 DTS file Platforms/AMD: remove /pmu node from Overdrive DTS Platforms/AMD: clean up whitespace in Overdrive DTS file Platforms/AMD: implement DtPlatformDtbLoaderLib Platforms/AMD: switch Overdrive to DtPlatformDxe Platforms/AMD: switch Overdrive 1000 to DtPlatformDxe Platform/AMD: remove FdtDxe driver Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c | 760 ----------------- Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c | 274 ------ Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h | 54 -- Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf | 76 -- Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h | 173 ---- Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c | 200 ----- Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 473 +++++++++++ Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 64 ++ Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dtb | Bin 8117 -> 7969 bytes Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/styx-overdrive1000.dts | 72 +- Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc | 10 +- Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.fdf | 4 +- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 8089 -> 7973 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 878 ++++++++++---------- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 11 +- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 4 +- 16 files changed, 1016 insertions(+), 2037 deletions(-) delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/BdsLinuxFdt.c delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.c delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.h delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/FdtDxe.inf delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoader.h delete mode 100644 Platforms/AMD/Styx/Drivers/FdtDxe/LinuxLoaderHelper.c create mode 100644 Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c create mode 100644 Platforms/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf -- 2.9.3

7 years, 8 months

[OpenPlatformPkg/ARM] Incorrect _CID?

by Heyi Guo

Hi folks, I found some _CID values of devices on ARM platforms may not be correct: OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/Dsdt.asl: Name(_CID, "PL011") OpenPlatformPkg/Platforms/ARM/Juno/AcpiTables/Dsdt.asl: Name(_CID, "PL050_KBD") OpenPlatformPkg/Platforms/ARM/Juno/AcpiTables/Dsdt.asl: Name(_CID, "PL011") According to ACPI spec, _CID should be something as _HID or PCI ID string. There are also lots of similar mistakes in Hisilicon platform ASL files. We can start to fix them when the above issue is confirmed. Thanks and regards, Gary (Heyi Guo)

7 years, 8 months

[PATCH v3 0/4] Juno cleanup -- OpenPlatformPkg edition

by Ard Biesheuvel

Counterpart to the EDK2 series switching Juno to the generic non-discoverable device driver and generic PCI host bridge driver. Ard Biesheuvel (4): Platforms/Juno: add non-discoverable device driver and library Platforms/Juno: add PciHostBridgeLib implementation Platforms/Juno: switch to generic PCI host bridge driver Platforms/Juno: remove BdsLib dependency Platforms/ARM/Juno/ArmJuno.dsc | 24 ++- Platforms/ARM/Juno/ArmJuno.fdf | 11 +- Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 199 ++++++++++++++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf | 77 ++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c | 182 ++++++++++++++++++ Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h | 107 +++++++++++ 6 files changed, 585 insertions(+), 15 deletions(-) create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.c create mode 100644 Platforms/ARM/Juno/Library/JunoPciHostBridgeLib/XPressRich3.h -- 2.9.3

7 years, 8 months

[PATCH] Platforms/AMD/OverdriveBoard: add graphical console support

by Ard Biesheuvel

Add the modules that are needed to run the console in graphical mode, i.e., when a GFX expansion card with a compatible option ROM is inserted into the system. Note that this includes the BGRT driver, which creates the BGRT ACPI table on the fly, so update the hardcoded OEM ids as well. Since the BGRT driver generates ACPI tables on the fly, set the OEM vendor and table IDs to the same value we use in the static tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 11 ++++++++++- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 6 ++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 53c7d67bd9b6..47179d2c6186 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -296,7 +296,7 @@ DEFINE DO_KCS = 1 ## If TRUE, Graphics Output Protocol will be installed on virtual handle ## created by ConsplitterDxe. It could be set FALSE to save size. - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 @@ -443,6 +443,9 @@ DEFINE DO_KCS = 1 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"AMDINC" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20454c5454414553 # SEATTLE + # # Enable strict image permissions for all images. (This applies # only to images that were built with >= 4 KB section alignment.) @@ -570,6 +573,9 @@ DEFINE DO_KCS = 1 # # Console IO support # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf MdeModulePkg/Universal/SerialDxe/SerialDxe.inf @@ -638,6 +644,7 @@ DEFINE DO_KCS = 1 MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf !if $(DO_XGBE) # @@ -679,6 +686,7 @@ DEFINE DO_KCS = 1 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf # # SMBIOS Support @@ -707,6 +715,7 @@ DEFINE DO_KCS = 1 NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf } + MdeModulePkg/Logo/LogoDxe.inf # # Crypto Accelerator support (RNG only) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf index c0a12822beb9..d2f01e73fe21 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -113,6 +113,9 @@ READ_LOCK_STATUS = TRUE # # Console IO support # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf @@ -174,6 +177,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf !if $(DO_XGBE) # @@ -212,6 +216,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf # # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] @@ -237,6 +242,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Logo/LogoDxe.inf # # Crypto Accelerator support (RNG only) -- 2.7.4

7 years, 8 months

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