Linaro-uefi

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811 discussions

[PATCH 0/9] OpenPlatformPkg/all platforms: move to ArmBaseLib

by Ard Biesheuvel

This moves all platforms in OpenPlatformPkg to ArmBaseLib, which replaces all previously existing variants of ArmLib. I have build tested each of them, and boot tested the ones I can test (FVP and Overdrive). I picked up some fixes for D02/D03 along the way. These are listed first (#1 - #4), #1 is required to fix the build, #5 is required since ArmBaseLib no longer pulls in MemoryAllocationLib. #2 and #3 are optional, but useful improvements nonetheless. #5 does the ArmBaseLib switch itself for D02/D03 Patches #6 to #9 replace all ArmLib references to ArmBaseLib in the remaining platforms. NOTE: This series combines with my armlib-cleanup branch [0], which deviates from the v1 I sent out today. When testing these patches, please use this branch; it will be the basis of my v2 submission once we have confirmed that everything works as expected. This series can be found here [1] [0] https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/refs/he… [1] https://git.linaro.org/uefi/OpenPlatformPkg.git/shortlog/refs/heads/armlib-… Ard Biesheuvel (9): Hisilicon/D0x: remove UEFI_APPLICATION BuildOptions override Hisilicon/D0x: get rid of EDK2_SKIP_PEICORE Hisilicon/D0x: get rid of APRIORI declarations Hisilicon/IoInitDxe: add hidden dependency on MemoryAllocationLib to .inf Hisilicon/D0x: switch to ArmBaseLib BeagleBoardPkg Omap35xxPkg: switch to ArmBaseLib AMD/Styx: switch to ArmBaseLib Platforms/ARM: switch to ArmBaseLib Marvell/Armada: switch to ArmBaseLib Chips/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Chips/Hisilicon/Pv660/Pv660.dsc.inc | 12 ------ Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc | 2 +- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 3 +- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 3 +- Platforms/ARM/Juno/ArmJuno.dsc | 7 +--- Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 3 +- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 4 +- Platforms/Hisilicon/D02/Pv660D02.dsc | 34 +++++------------ Platforms/Hisilicon/D02/Pv660D02.fdf | 11 ------ Platforms/Hisilicon/D03/D03.dsc | 39 +++++--------------- Platforms/Hisilicon/D03/D03.fdf | 11 ------ Platforms/Marvell/Armada/Armada.dsc.inc | 4 +- Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc | 4 +- 14 files changed, 27 insertions(+), 111 deletions(-) -- 2.7.4

8 years, 3 months

[PATCH 1/2] Platforms/AMD: remove EFI_MEMORY_UC attribute from normal memory

by Ard Biesheuvel

On ARM systems, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Similarly, DC ZVA instructions are only supported on normal memory, not device memory. So remove the EFI_MEMORY_UC attribute that we set by default on system RAM. If any region requires this attribute, it is up to the driver to set this attribute, and to ensure that no offending operations are performed on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 5fb63349864e..70821d1b120b 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -143,7 +143,6 @@ MemoryPeim ( EFI_RESOURCE_SYSTEM_MEMORY, ( EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | @@ -164,7 +163,6 @@ MemoryPeim ( EFI_RESOURCE_SYSTEM_MEMORY, ( EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | -- 2.7.4

8 years, 3 months

[edk2][PATCH] OpenPlatformPkg: ARM GICv2/v3 Base Address width fix-up

by Dennis Chen

According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. This patch is trying to fix the original 32-bit width by using FixedPcdGet64() instead of FixedPcdGet32(). Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Dennis Chen <dennis.chen(a)arm.com> --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 66 +++++++++++----------- .../Pv660/Pv660AcpiTables/MadtHi1610.aslc | 66 +++++++++++----------- Platforms/ARM/Juno/AcpiTables/Madt.aslc | 28 ++++----- Platforms/ARM/VExpress/AcpiTables/Madt.aslc | 20 +++---- 4 files changed, 90 insertions(+), 90 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc index 600b984..4edb95d 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc @@ -65,56 +65,56 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), { EFI_ACPI_6_0_GIC_ITS_INIT(0,0x8C000000), // pc EFI_ACPI_6_0_GIC_ITS_INIT(1,0xC6000000), // dsa diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc index 5861636..6e8557e 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/MadtHi1610.aslc @@ -66,56 +66,56 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), { EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), } diff --git a/Platforms/ARM/Juno/AcpiTables/Madt.aslc b/Platforms/ARM/Juno/AcpiTables/Madt.aslc index 78531d2..dffa5d6 100644 --- a/Platforms/ARM/Juno/AcpiTables/Madt.aslc +++ b/Platforms/ARM/Juno/AcpiTables/Madt.aslc @@ -55,14 +55,14 @@ // For now we leave CPU2 (A53-0) at the first position. // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0 - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1 - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2 - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3 - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0 - EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase)) // A57-1 }, - EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0) + EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0) }; #else #pragma pack (1) @@ -100,25 +100,25 @@ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0 - 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1 - 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2 - 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3 - 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0 - 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 - 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 2), + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2), // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase) EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) }; diff --git a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc index 5130548..bf90a9f 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc @@ -49,37 +49,37 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { }, { EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + 7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0x2C02F000, 0x2C010000, 0x19, 0, 0), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3), + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3), /* GIC Redistributor */ { EFI_ACPI_6_1_GICR, // UINT8 Type sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length EFI_ACPI_RESERVED_WORD, // UINT16 Reserved - FixedPcdGet32 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress + FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress 0x00200000, // UINT32 DiscoveryRangeLength } }; -- 2.7.4

8 years, 3 months

Questions about ARM SBSA v3.0 and SBBR v1.0

by Heyi Guo

Hi folks, I have some questions about ARM SBSA v3.0 and SBBR v1.0. Could anyone please provide the answers or some ideas? 1. In SBSA it says that I/O virtualization property should be expressed by system firmware data. Then how to express this information by ACPI? Is only IORT table related? Or is there any examples? 2. In SBSA Section 4.1.3, page 14 as below, does the term "memory" here also include peripheral memory mapped IO spaces? Does the term "access" include both "read" and "write"? If write is also included, I'm afraid there might be some critical configuration registers which will cause unpredicted behavior or even system hang due to unintended random write. 3. In SBBR, EFI_LOAD_FILE2_PROTOCOL is a required protocol. However,it is not used for boot in UEFI, and is mainly used for loading PCIe option ROM in EDK2 implementation. So why is this protocol required while PCIe is not mandatory for ARM server? 4. In SBBR, for IPv6 related protocols, it is said that they are optional on platforms that do not support networking. The question is, on platforms that *do* support networking, do IPv6 protocols become mandatory? Or is it allowed for only supporting IPv4 protocols? Thanks and regards. Heyi

8 years, 3 months

[PATCH 0/2] Cello: add firmware uploader for Renesas PD720202

by Ard Biesheuvel

This is a completely untested but complete implementation of a firmware uploader for the Renesas PD720202 PCIe XHCI controller. It is enabled for Cello in patch #2 if '-D RENESAS_XHCI_FW_DIR=<dir>' is passed on the build command line, where it expects to find the firmware image, in a file called K2013080.mem Ard Biesheuvel (2): Drivers/Xhci: implement firmware download driver for Renesas PD720202 Platforms/AMD/CelloBoard: add Renesas PD720202 firmware downloader Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c | 365 ++++++++++++++++++++ Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf | 43 +++ OpenPlatformPkg.dec | 3 + Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 4 + Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf | 10 + 5 files changed, 425 insertions(+) create mode 100644 Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.c create mode 100644 Drivers/Xhci/RenesasFirmwarePD720202/RenesasFirmwarePD720202.inf -- 2.7.4

8 years, 3 months

[PATCH] Platforms/ARM/Juno: limit ACPI support to v5.0 and higher

by Sudeep Holla

The ACPI spec predates the AARCH64 architecture by 5 versions, so there is no point in supporting anything below v5.0. So set the PCD that controls the ACPI table generation to the appropriate value. Based on the commit e0692789058e ("ArmVirtPkg/ArmVirtQemu: limit ACPI support to v5.0 and higher") in the upstream TianoCore by Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Cc: Evan Lloyd <Evan.Lloyd(a)arm.com> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index c51d8f2e21ab..3029999bc66f 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -183,6 +183,10 @@ # gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + # + # ACPI Table Version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 [PcdsPatchableInModule] # Console Resolution (Full HD) -- 2.7.4

8 years, 3 months

[PATCH 0/7] Patches for the MarvellYukon driver

by Alan Ott

These patches are for v4 of the MarvellYukon driver posted by Daniil Egranov on June 16 to this mailing list. The impetus was to get this driver to work on a SoftIron Overdrive 1000 board using the AMD Opteron-A (Seattle/Styx) SoC. On this platform, in my testing, edk2 allocates DMA buffers with 64-bit addresses. The Marvell Yukon driver as posted did not support 64-bit addresses, and simply truncated any DMA address to 32-bits. After consulting with Ard Biesheuvel and Leif Lindholm on IRC, it seemed the proper fix was to add support for 64-bit DMA. For this I went back to the original source of this driver (FreeBSD), and brought over the appropriate code. A couple of patches are basic fixes, but the one titled "Don't re-use DMA buffers" changes how handling of DMA buffers works. This patch makes it work closer to how the FreeBSD implementation works and also adds some required DMA function calls. Its commit message is worth a read. I don't have a Juno board to test this on, so while this does work on my Overdrive 1000, there's a chance I broke something for other users. Let me know! Alan. Alan Ott (7): Drivers/Net/MarvellYukon: Remove ARM-specific include Drivers/Net/MarvellYukon: Set Dual Address Cycle Attribute Drivers/Net/MarvellYukon: Put model_name under MDEPKG_NDEBUG ifndef Drivers/Net/MarvellYukon: Use EFI_SIZE_TO_PAGES() Drivers/Net/MarvellYukon: Don't re-use DMA buffers Drivers/Net/MarvellYukon: Zero allocated memory for DMA receive buffers Drivers/Net/MarvellYukon: Add 64-bit DMA support Drivers/Net/MarvellYukonDxe/DeviceConfig.c | 4 +- Drivers/Net/MarvellYukonDxe/if_msk.c | 95 +++++++++++++++++++++++------- Drivers/Net/MarvellYukonDxe/if_mskreg.h | 17 +++++- 3 files changed, 91 insertions(+), 25 deletions(-) -- 2.5.0

8 years, 3 months

[PATCH] Platforms/Styx: ignore PcdArmPrimaryCoreMask

by Ard Biesheuvel

The PCD PcdArmPrimaryCoreMask is of dubious value, not only because it is unclear what the point is of masking out bits before comparing a given MPIDR_EL1 value with a known value belonging to the primary core, but also because the default value of 0xF03 masks out bits that belong to the actual affinity levels. For Styx, simply ignore the mask altogether. Since its version of ArmPlatformPeiBootAction () records the primary MPIDR_EL1 value upon first entry, we know its exact value, and no masking is necessary. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Hello Alan, Any chance you could try this patch, and check whether it solves the regression you have been experiencing? I'd try it myself it it weren't for the fact that my SPI flash programmer is broken atm. Thanks, Ard. Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S | 3 --- Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf | 1 - Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf | 1 - 3 files changed, 5 deletions(-) diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S index a3ac60282706..b7ec02f0e69f 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S @@ -58,9 +58,6 @@ ASM_FUNC(ArmGetCpuCountPerCluster) // IN UINTN MpId // ); ASM_FUNC(ArmPlatformIsPrimaryCore) - MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) - and x0, x0, x1 - ldr w1, PrimaryCoreMpid cmp w0, w1 diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf index 4a6469ee016c..8e9169161d16 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf @@ -67,7 +67,6 @@ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize [FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf index 0b9b6287168d..2a2d6ffb8c64 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf @@ -62,7 +62,6 @@ gArmTokenSpaceGuid.PcdFvBaseAddress [FixedPcd] - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore gArmPlatformTokenSpaceGuid.PcdCoreCount -- 2.7.4

8 years, 3 months

[PATCH] Platforms/AMD/Styx: add EBC support

by Ard Biesheuvel

Enable the EBC interpreter for Overdrive and Cello, so that PCIe cards with EBC option ROMs are supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 1 + Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 1 + 4 files changed, 4 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 36d675a9939b..7f1db26e284b 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -510,6 +510,7 @@ DEFINE DO_KCS = 0 EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # # Console IO support diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf index 436e445389f2..7a75197858be 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf @@ -105,6 +105,7 @@ READ_LOCK_STATUS = TRUE INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 81409b8f37ef..4497d3683922 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -546,6 +546,7 @@ DEFINE DO_KCS = 1 EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # # Console IO support diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf index 02e92434813c..e5b079d0e3f7 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -105,6 +105,7 @@ READ_LOCK_STATUS = TRUE INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf -- 2.7.4

8 years, 3 months

[PATCH] ArmJunoPkg/PciHostBridgeDxe: Fix for PCI Dual Address Cycle Attribute

by Daniil Egranov

The fix handles the PCI Dual Address Cycle Attribute case. It allows the Marvell Yukon driver with 64 bit DMA patches run on Juno. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c index 10a4575..18f90a6 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c @@ -518,11 +518,14 @@ PciRbMap ( PCI_TRACE ("PciRbMap()"); - if (Operation == EfiPciOperationBusMasterRead) { + if (Operation == EfiPciOperationBusMasterRead || + Operation == EfiPciOperationBusMasterRead64) { DmaOperation = MapOperationBusMasterRead; - } else if (Operation == EfiPciOperationBusMasterWrite) { + } else if (Operation == EfiPciOperationBusMasterWrite || + Operation == EfiPciOperationBusMasterWrite64) { DmaOperation = MapOperationBusMasterWrite; - } else if (Operation == EfiPciOperationBusMasterCommonBuffer) { + } else if (Operation == EfiPciOperationBusMasterCommonBuffer || + Operation == EfiPciOperationBusMasterCommonBuffer64) { DmaOperation = MapOperationBusMasterCommonBuffer; } else { return EFI_INVALID_PARAMETER; -- 2.7.4

8 years, 3 months

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