CoreSight September 2022

coresight@lists.linaro.org

7 participants
26 discussions

[PATCH v3] coresight: etm4x: add CPU hotplug support for probing

by Tamas Zsoldos

etm4x devices cannot be successfully probed when their CPU is offline. For example, when booting with maxcpus=n, ETM probing will fail on CPUs >n, and the probing won't be reattempted once the CPUs come online. This will leave those CPUs unable to make use of ETM. This change adds a mechanism to delay the probing if the corresponding CPU is offline, and to try it again when the CPU comes online. Signed-off-by: Tamas Zsoldos <tamas.zsoldos(a)arm.com> --- Changes since v2: * Fix tear down issue (thanks to Suzuki). --- .../coresight/coresight-etm4x-core.c | 153 +++++++++++++----- 1 file changed, 113 insertions(+), 40 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 87299e99dabb..71ab1d6e72dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -66,10 +66,13 @@ static enum cpuhp_state hp_online; struct etm4_init_arg { unsigned int pid; - struct etmv4_drvdata *drvdata; + struct device *dev; struct csdev_access *csa; }; +static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); +static int etm4_probe_cpu(unsigned int cpu); + /* * Check if TRCSSPCICRn(i) is implemented for a given instance. * @@ -1071,7 +1074,7 @@ static void etm4_init_arch_data(void *info) struct csdev_access *csa; int i; - drvdata = init_arg->drvdata; + drvdata = dev_get_drvdata(init_arg->dev); csa = init_arg->csa; /* @@ -1514,7 +1517,7 @@ void etm4_config_trace_mode(struct etmv4_config *config) static int etm4_online_cpu(unsigned int cpu) { if (!etmdrvdata[cpu]) - return 0; + return etm4_probe_cpu(cpu); if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) coresight_enable(etmdrvdata[cpu]->csdev); @@ -1890,48 +1893,20 @@ static void etm4_pm_clear(void) } } -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) { int ret; struct coresight_platform_data *pdata = NULL; - struct etmv4_drvdata *drvdata; + struct device *dev = init_arg->dev; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct coresight_desc desc = { 0 }; - struct etm4_init_arg init_arg = { 0 }; u8 major, minor; char *type_name; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) - pm_save_enable = coresight_loses_context_with_cpu(dev) ? - PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; - - if (pm_save_enable != PARAM_PM_SAVE_NEVER) { - drvdata->save_state = devm_kmalloc(dev, - sizeof(struct etmv4_save_state), GFP_KERNEL); - if (!drvdata->save_state) - return -ENOMEM; - } - - drvdata->base = base; - - spin_lock_init(&drvdata->spinlock); - - drvdata->cpu = coresight_get_cpu(dev); - if (drvdata->cpu < 0) - return drvdata->cpu; - - init_arg.drvdata = drvdata; - init_arg.csa = &desc.access; - init_arg.pid = etm_pid; + return -EINVAL; - if (smp_call_function_single(drvdata->cpu, - etm4_init_arch_data, &init_arg, 1)) - dev_err(dev, "ETM arch init failed\n"); + desc.access = *init_arg->csa; if (!drvdata->arch) return -EINVAL; @@ -2002,6 +1977,68 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return 0; } +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +{ + struct etmv4_drvdata *drvdata; + struct csdev_access access = { 0 }; + struct etm4_init_arg init_arg = { 0 }; + struct etm4_init_arg *delayed; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) + pm_save_enable = coresight_loses_context_with_cpu(dev) ? + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; + + if (pm_save_enable != PARAM_PM_SAVE_NEVER) { + drvdata->save_state = devm_kmalloc(dev, + sizeof(struct etmv4_save_state), GFP_KERNEL); + if (!drvdata->save_state) + return -ENOMEM; + } + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->cpu = coresight_get_cpu(dev); + if (drvdata->cpu < 0) + return drvdata->cpu; + + init_arg.dev = dev; + init_arg.csa = &access; + init_arg.pid = etm_pid; + + /* + * Serialize against CPUHP callbacks to avoid race condition + * between the smp call and saving the delayed probe. + */ + cpus_read_lock(); + if (smp_call_function_single(drvdata->cpu, + etm4_init_arch_data, &init_arg, 1)) { + /* The CPU was offline, try again once it comes online. */ + delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); + if (!delayed) { + cpus_read_unlock(); + return -ENOMEM; + } + + *delayed = init_arg; + + per_cpu(delayed_probe, drvdata->cpu) = delayed; + + cpus_read_unlock(); + return 0; + } + cpus_read_unlock(); + + return etm4_add_coresight_dev(&init_arg); +} + static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) { void __iomem *base; @@ -2040,6 +2077,35 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) return ret; } +static int etm4_probe_cpu(unsigned int cpu) +{ + int ret; + struct etm4_init_arg init_arg; + struct csdev_access access = { 0 }; + struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); + + if (!iap) + return 0; + + init_arg = *iap; + devm_kfree(init_arg.dev, iap); + *this_cpu_ptr(&delayed_probe) = NULL; + + ret = pm_runtime_resume_and_get(init_arg.dev); + if (ret < 0) { + dev_err(init_arg.dev, "Failed to get PM runtime!\n"); + return 0; + } + + init_arg.csa = &access; + etm4_init_arch_data(&init_arg); + + etm4_add_coresight_dev(&init_arg); + + pm_runtime_put(init_arg.dev); + return 0; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -2054,16 +2120,20 @@ static void clear_etmdrvdata(void *info) int cpu = *(int *)info; etmdrvdata[cpu] = NULL; + per_cpu(delayed_probe, cpu) = NULL; } static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) { - etm_perf_symlink(drvdata->csdev, false); + bool fully_registered; /* * Taking hotplug lock here to avoid racing between etm4_remove_dev() * and CPU hotplug call backs. */ cpus_read_lock(); + + fully_registered = (etmdrvdata[drvdata->cpu] == drvdata); + /* * The readers for etmdrvdata[] are CPU hotplug call backs * and PM notification call backs. Change etmdrvdata[i] on @@ -2071,12 +2141,15 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) * inside one call back function. */ if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) - etmdrvdata[drvdata->cpu] = NULL; + clear_etmdrvdata(&drvdata->cpu); cpus_read_unlock(); - cscfg_unregister_csdev(drvdata->csdev); - coresight_unregister(drvdata->csdev); + if (fully_registered) { + etm_perf_symlink(drvdata->csdev, false); + cscfg_unregister_csdev(drvdata->csdev); + coresight_unregister(drvdata->csdev); + } return 0; } -- 2.17.1

2 years, 1 month

Re: [PATCH v2] coresight: etm4x: Fix crash observed on Qcom ETM parts with 'Low power override'

by Leo Yan

Hi Bhupesh, On Thu, Aug 25, 2022 at 10:52:32AM +0530, Bhupesh Sharma wrote: > Some Qualcomm ETM implementations require skipping powering up > the trace unit, as the ETMs are in the same power domain as > their CPU cores. > > Via commit 5214b563588e ("coresight: etm4x: Add support for > sysreg only devices"), the setting of 'skip_power_up' flag was > moved after the 'etm4_init_arch_data' function is called, whereas > the flag value is itself used inside the function. This causes > a crash when ETM mode 'Low-power state behavior override' is set > on some Qualcomm parts. > > Fix the same. > > Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)linaro.org> > --- > - v1 can be seen here: https://lore.kernel.org/lkml/20220803191236.3037591-1-bhupesh.sharma@linaro… > - Addressed the review comments from Suzuki. > - Rebased on linux-next. > > drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index d39660a3e50c..14c1c7869795 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -977,6 +977,16 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, > if (!cpu_supports_sysreg_trace()) > return false; > > + /* > + * Some Qualcomm implementations require skipping powering up the trace unit, > + * as the ETMs are in the same power domain as their CPU cores. > + * > + * Since the 'skip_power_up' flag is used inside 'etm4_init_arch_data' function, > + * initialize it before the function is called. > + */ > + if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) > + drvdata->skip_power_up = true; > + I personally think this sentence should be placed in the function etm4_probe(), you need to move it just before smp call etm4_init_arch_data(), this can allow DT property "qcom,skip-power-up" to be respected. > /* > * ETMs implementing sysreg access must implement TRCDEVARCH. > */ > @@ -1951,8 +1961,7 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > return -EINVAL; > > /* TRCPDCR is not accessible with system instructions. */ > - if (!desc.access.io_mem || > - fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) > + if (!desc.access.io_mem) > drvdata->skip_power_up = true; I prefer to move the condition checking for "desc.access.io_mem" to etm4_init_sysreg_access(), this can make sure the flag skip_power_up is set correctly based on property of system register access. A side topic, in the mainline kernel I found the value "desc.access.io_mem" is always zero (see the initialized value in etm4_probe() and etm4_init_sysreg_access()). Should we initialize desc.access.io_mem to true in etm4_probe()? diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d39660a3e50c..cf2555c50abb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1939,6 +1939,7 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (drvdata->cpu < 0) return drvdata->cpu; + desc.access.io_mem = true; init_arg.drvdata = drvdata; init_arg.csa = &desc.access; init_arg.pid = etm_pid; Thanks, Leo > major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); > -- > 2.35.3 >

2 years, 1 month

[PATCH 0/9] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This series applies to coresight/next https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git?h=next This patch series depends on patch series "[v12,0/9] Coresight: Add support for TPDM and TPDA" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220905065357.… Tao Zhang (9): dt-bindings: arm: Add support for DSB element coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb element creation coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request .../bindings/arm/qcom,coresight-tpda.yaml | 9 + drivers/hwtracing/coresight/coresight-tpda.c | 62 ++ drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 625 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 60 ++ 5 files changed, 756 insertions(+), 4 deletions(-) -- 2.7.4

2 years, 1 month

[PATCH v9 00/13] perf: test: Add trace data quality tests for CoreSight

by carsten.haitzler＠foss.arm.com

From: Carsten Haitzler <carsten.haitzler(a)arm.com> This series adds more test cases to perf test as well as new infrastructure for testing coresight data quality to ensure the data coming out of the kernel via perf actually contains useful information. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (13): perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 158 ++++++++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- .../perf/Documentation/perf-arm-coresight.txt | 5 + tools/perf/Makefile.config | 2 + tools/perf/Makefile.perf | 15 +- tools/perf/tests/shell/coresight/Makefile | 29 ++++ .../tests/shell/coresight/Makefile.miniconfig | 14 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 ++++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 ++++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 ++++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 ++++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 +++ .../coresight/thread_loop_check_tid_2.sh | 19 +++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 ++++ .../unroll_loop_thread/unroll_loop_thread.c | 74 ++++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++++++ 26 files changed, 854 insertions(+), 4 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/perf-arm-coresight.txt create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 2 months

[PATCH v3 00/13] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Applies to coresight/next [4d45bc82df66] Tested on DB410c Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +-- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 92 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 79 ++++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 266 ++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 78 +++++ include/linux/coresight-pmu.h | 35 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 331 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 933 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 2 months

Re: [PATCH linux-next] coresight: use sysfs_emit() to instead of scnprintf()

by James Clark

On 27/09/2022 12:51, zhangsongyi.cgel(a)gmail.com wrote: > From: zhang songyi <zhang.songyi(a)zte.com.cn> > > Follow the advice of the Documentation/filesystems/sysfs.rst and show() > should only use sysfs_emit() or sysfs_emit_at() when formatting the value > to be returned to user space. > > Reported-by: Zeal Robot <zealci(a)zte.com.cn> > Signed-off-by: zhang songyi <zhang.songyi(a)zte.com.cn> > --- > drivers/hwtracing/coresight/coresight-stm.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > Reviewed-by: James Clark <james.clark(a)arm.com> > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index 463f449cfb79..3a1b07217932 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -466,7 +466,7 @@ static ssize_t hwevent_enable_show(struct device *dev, > struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); > unsigned long val = drvdata->stmheer; > > - return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > + return sysfs_emit(buf, "%#lx\n", val); > } > > static ssize_t hwevent_enable_store(struct device *dev, > @@ -495,7 +495,7 @@ static ssize_t hwevent_select_show(struct device *dev, > struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); > unsigned long val = drvdata->stmhebsr; > > - return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > + return sysfs_emit(buf, "%#lx\n", val); > } > > static ssize_t hwevent_select_store(struct device *dev, > @@ -530,7 +530,7 @@ static ssize_t port_select_show(struct device *dev, > spin_unlock(&drvdata->spinlock); > } > > - return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > + return sysfs_emit(buf, "%#lx\n", val); > } > > static ssize_t port_select_store(struct device *dev, > @@ -577,7 +577,7 @@ static ssize_t port_enable_show(struct device *dev, > spin_unlock(&drvdata->spinlock); > } > > - return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > + return sysfs_emit(buf, "%#lx\n", val); > } > > static ssize_t port_enable_store(struct device *dev,

2 years, 2 months

[PATCH v2 0/1] arm64: defconfig: Add Coresight as module

by James Clark

I'm still leaving out CONFIG_CORESIGHT_SOURCE_ETM4X because it depends on the outcome of the investigation into CONFIG_PID_IN_CONTEXTIDR, but I think we should enable these ones for now and start getting some of the benefits sooner. Changes since v1: * Remove CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y which shouldn't be enabled by default ----- As suggested by Catalin here's the change to add Coresight to defconfig. Unfortunately I don't think we should add CONFIG_CORESIGHT_SOURCE_ETM4X which builds a few files until [1] is merged because of the overhead of CONFIG_PID_IN_CONTEXTIDR. [1]: https://lore.kernel.org/lkml/20211021134530.206216-1-leo.yan@linaro.org/T/ applies to arm64/for-next/core (e99db032d186) James Clark (1): arm64: defconfig: Add Coresight as module arch/arm64/configs/defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.28.0

2 years, 3 months

Re: [PATCH 0/1] arm64: defconfig: Add Coresight as module

by James Clark

On 22/09/2022 11:52, Catalin Marinas wrote: > On Thu, Sep 22, 2022 at 10:34:45AM +0100, James Clark wrote: >> On 21/09/2022 16:08, Catalin Marinas wrote: >>> 2. Always on CONFIG_PID_IN_CONTEXTIDR (we might as well remove the >>> Kconfig entry). This would write the root pid namespace value >>> (task_pid_nr()). >> >> If we're not worried about the overhead after all, this would be the >> easiest solution. And then SPE or Coresight already decide whether they >> want to use the value or not, so no further changes are needed. >> >> From Leo's patch there is a table that shows a 1% overhead with it >> enabled permanently, and I've heard a figure like that mentioned before. >> So I could also resurrect that patch to use static keys? Although it's a >> bit more complicated, that would be my preference. And then we can have >> that mode always on. > > I don't think we should bother with static keys, just always enable it > but try to reduce/group the ISBs from all the functions called on the > __switch_to() path. We may actually get a speed-up. > Ok thanks I will take a look at this

2 years, 3 months

Re: [PATCH 0/1] arm64: defconfig: Add Coresight as module

by James Clark

On 21/09/2022 16:08, Catalin Marinas wrote: > On Wed, Sep 21, 2022 at 03:05:34PM +0100, James Clark wrote: >> As suggested by Catalin here's the change to add Coresight to defconfig. >> >> Unfortunately I don't think we should add CONFIG_CORESIGHT_SOURCE_ETM4X >> which builds a few files until [1] is merged because of the overhead >> of CONFIG_PID_IN_CONTEXTIDR. >> >> [1]: https://lore.kernel.org/lkml/20211021134530.206216-1-leo.yan@linaro.org/T/ > > I thought the overhead wasn't the problem, it's mostly negligible. We > can probably save a few more cycles on the __switch_to() path by > replacing several isb()s in those functions with a single one just > before cpu_switch_to(). > > IIRC the issue is that unless a process runs in the root pid namespace, > the actual pid written to contextidr is meaningless. This is true, and Leo has recently disabled it in that scenario in aab473867fed. > > Now that you reminded me of that thread, I see three options (sorry, not > entirely related to the defconfig updates): > > 1. Remove CONFIG_PID_IN_CONTEXTIDR and corresponding code completely, > find other events to correlate the task with the trace. Unfortunately when tracing per core we would need kernel timestamps in the trace to correlate to the switch records. At the moment Coresight is using a different clock source so it's not possible and we're still using the context ID to correlate samples. With FEAT_TRF in v8.4 it will be possible to do this and we've started working towards that here: 0f00b223ea22. But we'd still have to support older hardware too, so CONFIG_PID_IN_CONTEXTIDR can't be removed completely. For SPE it's not required because we already have the right timestamps in the samples and we've added support for no context IDs in the decoder here: 27d113cfe892 > > 2. Always on CONFIG_PID_IN_CONTEXTIDR (we might as well remove the > Kconfig entry). This would write the root pid namespace value > (task_pid_nr()). If we're not worried about the overhead after all, this would be the easiest solution. And then SPE or Coresight already decide whether they want to use the value or not, so no further changes are needed. From Leo's patch there is a table that shows a 1% overhead with it enabled permanently, and I've heard a figure like that mentioned before. So I could also resurrect that patch to use static keys? Although it's a bit more complicated, that would be my preference. And then we can have that mode always on. > > 3. Similar to (2) but instead write task_pid_nr_ns(). An alternative > here is to write -1 if the task is not in the root pid namespace. > > Strong preference for (1). >

2 years, 3 months

Re: [PATCH 1/1] arm64: defconfig: Add Coresight as module

by James Clark

On 21/09/2022 17:46, Mathieu Poirier wrote: > On Wed, Sep 21, 2022 at 04:26:59PM +0100, Mark Brown wrote: >> On Wed, Sep 21, 2022 at 03:05:35PM +0100, James Clark wrote: >> >>> +CONFIG_CORESIGHT_CTI=m >>> +CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y >> > > I agree - integration registers should not be enabled by default. > >> Do we want this turned on by default? According to the >> description it's a bit dangerous and it's exposed via sysfs >> rather than debugfs. > > Should I disable just CONFIG_CORESIGHT_CTI_INTEGRATION_REGS or CONFIG_CORESIGHT_CTI as well? There are other writable registers exposed via sysfs outside of these two options, so I wanted to check if it's just the integration registers that are the issue.

2 years, 3 months

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CoreSight September 2022