CoreSight January 2023

coresight@lists.linaro.org

10 participants
48 discussions

[PATCH v3 0/3] coresight: cti: Add PM runtime call in enable_store

by James Clark

Changes since v2: * Reword first commit message and add fixes tag * Pickup Jinlong's tested-by tags ---- This should be a slight improvement on Jinlong's previous version. Now it's not possible to trigger the error message from pm_runtime_put() by calling disable twice. It's also similar to the original pre-breaking change version where pm_runtime_put() was only called if the device was actually disabled, but with one difference: Previously pm_runtime_put() was only called once for the last disable call, but because of the reference counting in pm_runtime, it should have been called once for each enable call. This meant that the clock would have never been disabled if there were ever multiple enable calls. This is now fixed. The third commit is a refactor and doesn't need to be backported. I removed one of the atomic types because it didn't appear to be required. Maybe it was added for a reason which I'm not aware of, if so it should be pretty easy to drop that change. James Clark (2): coresight: cti: Prevent negative values of enable count coresight: cti: Remove atomic type from enable_req_count Mao Jinlong (1): coresight: cti: Add PM runtime call in enable_store .../hwtracing/coresight/coresight-cti-core.c | 23 ++++++++++++------- .../hwtracing/coresight/coresight-cti-sysfs.c | 15 +++++++++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) base-commit: 88603b6dc419445847923fcb7fe5080067a30f98 -- 2.25.1

1 year, 3 months

[PATCH] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR

by Junhao He

The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. Signed-off-by: Junhao He <hejunhao3(a)huawei.com> --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..c7a65d1524fc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { -- 2.33.0

1 year, 3 months

Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready

by James Clark

On 09/01/2023 23:43, Yabin Cui wrote: > Otherwise, it may cause error in AXI bus and result in a kernel panic. Hi Yabin, Thanks for the fix. Do you have a reproducer for this or some more info? For example is it a regression or has it always been there? And on which platform. Thanks James > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 4 +++- > .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++--- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > 3 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 07abf28ad725..c106d142e632 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > struct csdev_access *csa = &csdev->access; > @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { > dev_err(&csdev->dev, > "timeout while waiting for TMC to be Ready\n"); > + return -EBUSY; > } > + return 0; > } > > void tmc_flush_and_stop(struct tmc_drvdata *drvdata) > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 867ad8bb9b0c..2da99dd41ed6 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) > etr_buf->ops->sync(etr_buf, rrp, rwp); > } > > -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > { > u32 axictl, sts; > struct etr_buf *etr_buf = drvdata->etr_buf; > + int rc = 0; > > CS_UNLOCK(drvdata->base); > > /* Wait for TMCSReady bit to be set */ > - tmc_wait_for_tmcready(drvdata); > + rc = tmc_wait_for_tmcready(drvdata); > + if (rc) { > + dev_err(&drvdata->csdev->dev, "not ready ETR isn't enabled\n"); > + CS_LOCK(drvdata->base); > + return rc; > + } > > writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); > writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); > @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > tmc_enable_hw(drvdata); > > CS_LOCK(drvdata->base); > + return rc; > } > > static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > rc = coresight_claim_device(drvdata->csdev); > if (!rc) { > drvdata->etr_buf = etr_buf; > - __tmc_etr_enable_hw(drvdata); > + rc = __tmc_etr_enable_hw(drvdata); > + if (rc) { > + drvdata->etr_buf = NULL; > + coresight_disclaim_device(drvdata->csdev); > + tmc_etr_disable_catu(drvdata); > + } > } > > return rc; > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 66959557cf39..01c0382a29c0 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -255,7 +255,7 @@ struct tmc_sg_table { > }; > > /* Generic functions */ > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > void tmc_flush_and_stop(struct tmc_drvdata *drvdata); > void tmc_enable_hw(struct tmc_drvdata *drvdata); > void tmc_disable_hw(struct tmc_drvdata *drvdata);

1 year, 3 months

[PATCH v2 0/3] coresight: cti: Add PM runtime call in enable_store

by James Clark

This should be a slight improvement on Jinlong's previous version. Now it's not possible to trigger the error message from pm_runtime_put() by calling disable twice. It's also similar to the original pre-breaking change version where pm_runtime_put() was only called if the device was actually disabled, but with one difference: Previously pm_runtime_put() was only called once for the last disable call, but because of the reference counting in pm_runtime, it should have been called once for each enable call. This meant that the clock would have never been disabled if there were ever multiple enable calls. This is now fixed. The third commit is a refactor and doesn't need to be backported. I removed one of the atomic types because it didn't appear to be required. Maybe it was added for a reason which I'm not aware of, if so it should be pretty easy to drop that change. James Clark (2): coresight: cti: Prevent negative values of enable count coresight: cti: Remove atomic type from enable_req_count Mao Jinlong (1): coresight: cti: Add PM runtime call in enable_store .../hwtracing/coresight/coresight-cti-core.c | 23 ++++++++++++------- .../hwtracing/coresight/coresight-cti-sysfs.c | 15 +++++++++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) base-commit: c767c34740132ffc478226864a7461493cdc2413 -- 2.25.1

1 year, 3 months

Re: [PATCH v16 0/8] Coresight: Add support for TPDM and TPDA

by Suzuki K Poulose

On 06/01/2023 20:50, Trilok Soni wrote: > On 1/6/2023 1:21 AM, Mao Jinlong wrote: >> This patch series depends on patch series: >> "[v6,00/14] coresight: Add new API to allocate trace source ID values" >> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221123195010.… > > Do we know now when these patches will get revived and accepted to > unblock us? This is all reviewed, and awaiting Peter's Ack for the perf generic change. Once we have that, it will be pushed to coresight tree. Suzuki

1 year, 3 months

[PATCH v6 00/14] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Appies to coresight/next Changes since v5: (requested by suzuki) 1) Prefer odd ID values for system IDs to avoid overlap with legacy CPU IDs 2) Some style changes Changes since v4: 1) update to ensure that compiling after each individual patch added still works - ie. git bisect not broken through the patchset.. 2) Revision to some of the now redundant code in cs-etm (James) 3) Comments and other minor fixes requested by Suzuki. Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (14): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: perf: traceid: Add perf ID allocation and notifiers coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: trace id: Remove legacy get trace ID function. perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 45 --- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 93 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 73 +++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 298 ++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 156 +++++++++ include/linux/coresight-pmu.h | 34 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 328 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 1024 insertions(+), 231 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

1 year, 3 months

[PATCH] coresight: cti: Add PM runtime call in enable_store

by Mao Jinlong

In commit 6746eae4bbad ("coresight: cti: Fix hang in cti_disable_hw()") PM runtime calls are removed from cti_enable_hw/cti_disable_hw. When enabling CTI by writing enable sysfs node, clock for accessing CTI register won't be enabled. Device will crash due to register access issue. Add PM runtime call in enable_store to fix this issue. Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6d59c815ecf5..b1ed424ae043 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -108,10 +108,17 @@ static ssize_t enable_store(struct device *dev, if (ret) return ret; - if (val) + if (val) { + ret = pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; ret = cti_enable(drvdata->csdev); - else + if (ret) + pm_runtime_put(dev->parent); + } else { ret = cti_disable(drvdata->csdev); + pm_runtime_put(dev->parent); + } if (ret) return ret; return size; -- 2.17.1

1 year, 3 months

[PATCH v2 0/7] perf cs_etm: Basic support for virtual/kernel timestamps

by James Clark

Changes since v1: * Add 3 refactor commits for sysfs reading around pmu.c as suggested by Arnaldo here [1] * The dependency on [2] has now reached mainline so is no longer blocking * Rebase on perf/core [1]: https://lore.kernel.org/all/YnqVqq5QW%2Fb14oPZ@kernel.org/ [2]: https://lore.kernel.org/all/20220503123537.1003035-1-german.gomez@arm.com/ German Gomez (4): perf pmu: Add function to check if a pmu file exists perf cs_etm: Keep separate symbols for ETMv4 and ETE parameters perf cs_etm: Record ts_source in AUXTRACE_INFO for ETMv4 and ETE perf cs_etm: Set the time field in the synthetic samples James Clark (3): perf: Remove duplication around EVENT_SOURCE_DEVICE_PATH perf: Use perf_pmu__open_file() and perf_pmu__scan_file() perf: Remove remaining duplication of bus/event_source/devices/... tools/perf/arch/arm/util/auxtrace.c | 5 +- tools/perf/arch/arm/util/cs-etm.c | 91 +++++++++++- tools/perf/arch/x86/util/pmu.c | 12 +- tools/perf/tests/evsel-roundtrip-name.c | 3 +- tools/perf/tests/parse-events.c | 3 +- tools/perf/util/cputopo.c | 9 +- tools/perf/util/cs-etm-base.c | 34 +++-- tools/perf/util/cs-etm.c | 86 +++++++++-- tools/perf/util/cs-etm.h | 13 +- tools/perf/util/pmu-hybrid.c | 27 +--- tools/perf/util/pmu-hybrid.h | 2 +- tools/perf/util/pmu.c | 183 ++++++++++-------------- tools/perf/util/pmu.h | 10 +- 13 files changed, 292 insertions(+), 186 deletions(-) base-commit: 573de010917836f198a4e579d40674991659668b -- 2.25.1

1 year, 4 months

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CoreSight January 2023