CoreSight October 2024

coresight@lists.linaro.org

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[PATCH v10 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.12. Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. *** SUBJECT HERE *** *** BLURB HERE *** Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 356 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 +++ .../hwtracing/coresight/coresight-tmc-core.c | 296 ++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 124 +++++- .../hwtracing/coresight/coresight-tmc-etr.c | 231 +++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 106 ++++++ include/linux/coresight.h | 24 ++ 12 files changed, 1282 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

1 day, 11 hours

Re: [PATCH] perf: cs-etm: Fix the assert() to handle captured and unprocessed cpu trace

by Arnaldo Carvalho de Melo

On Wed, Sep 25, 2024 at 04:04:55PM -0700, Namhyung Kim wrote: > On Wed, Sep 25, 2024 at 10:54:31AM +0100, James Clark wrote: > > > > > > On 25/09/2024 12:39 am, Ilkka Koskinen wrote: > > > If one builds perf with DEBUG=1, captures data on multiple CPUs and > > > finally runs 'perf report -C <cpu>' for only one of the cpus, assert() > > > aborts the program. This happens because there are empty queues with > > > format set. This patch changes the condition to abort only if a queue > > > is not empty and if the format is unset. > > > > > > $ make -C tools/perf DEBUG=1 CORESIGHT=1 CSLIBS=/usr/lib CSINCLUDES=/usr/include install > > > $ perf record -o kcore --kcore -e cs_etm/timestamp/k -s -C 0-1 dd if=/dev/zero of=/dev/null bs=1M count=1 > > > $ perf report --input kcore/data --vmlinux=/home/ikoskine/projects/linux/vmlinux -C 1 > > > Aborted (core dumped) > > > > > > Fixes: 57880a7966be ("perf: cs-etm: Allocate queues for all CPUs") > > > Signed-off-by: Ilkka Koskinen <ilkka(a)os.amperecomputing.com> > > > --- > > > tools/perf/util/cs-etm.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > > > index 90f32f327b9b..40f047baef81 100644 > > > --- a/tools/perf/util/cs-etm.c > > > +++ b/tools/perf/util/cs-etm.c > > > @@ -3323,7 +3323,7 @@ static int cs_etm__create_decoders(struct cs_etm_auxtrace *etm) > > > * Don't create decoders for empty queues, mainly because > > > * etmq->format is unknown for empty queues. > > > */ > > > - assert(empty == (etmq->format == UNSET)); > > > + assert(empty || etmq->format != UNSET); > > > if (empty) > > > continue; > > > > Oops I didn't realize you could filter on CPU in report mode. Thanks for the > > fix. Adding a test to the end of test_arm_coresight.sh might be quite > > useful. Either way: > > > > Reviewed-by: James Clark <james.clark(a)linaro.org> > > Thanks, it should go to the perf-tool. Arnaldo, please pick up. Right, picking it now. Thanks, - Arnaldo

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CoreSight October 2024