CoreSight December 2024

coresight@lists.linaro.org

9 participants
48 discussions

Re: [PATCH v6 1/2] dt-bindings: arm: Add label in the coresight components

by Mike Leach

On Wed, 18 Dec 2024 at 09:21, Krzysztof Kozlowski <krzk(a)kernel.org> wrote: > > On Tue, Dec 17, 2024 at 02:33:23PM +0800, Mao Jinlong wrote: > > Current name of coresight component's folder consists of prefix of > > the device and the id in the device list. When run 'ls' command, > > we can get the register address of the device. Take CTI for example, > > if we want to set the config for modem CTI, but we can't know which > > CTI is modem CTI from all current information. > > > > cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 > > cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 > > > > Add label to show hardware context information of each coresight > > device. There will be a sysfs node label in each device folder. > > > > cat /sys/bus/coresight/devices/cti_sys0/label > > > > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > > Best regards, > Krzysztof > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months, 1 week

[PATCH v2 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Changes in V2: 1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) || tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support. 2. Embed mcmb_dataset struct into cmb struct. 3. Update the date and version in sysfs-bus-coresight-devices-tpdm Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 7 +- drivers/hwtracing/coresight/coresight-tpdm.c | 124 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++-- 4 files changed, 158 insertions(+), 21 deletions(-) -- 2.17.1

3 months, 2 weeks

[PATCH v7 0/4] source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V7: 1. Correct the use of incorrect characters. -- Suzuki K Poulose 2. Rebase the series on v6.13-rc1 -- Suzuki K Poulose Changes in V6: 1. Optimize the prompt content of the warning log when the filter handle is not a trace source. -- Suzuki K Poulose 2. Reset the filter device and fwnode if it is not a trace source. -- Suzuki K Poulose Changes in V5: 1. Replace "filter-src" with "filter-source" in the dt-binding document. -- Suzuki K Poulose 2. Optimize the comments of the patch "coresight: Add support for trace filtering by source" due to bad example. -- Suzuki K Poulose 3. Correct spelling errors in the patch "coresight: Add support for trace filtering by source". -- Suzuki K Poulose 4. Optimize the function "coresight_blocks_source". -- Suzuki K Poulose 5. Add { } in the function "of_coresight_parse_endpoint". -- Suzuki K Poulose 6. Adjust the order of the patches. -- Suzuki K Poulose 7. Adjust the alignment in "coresight-platform.c". -- Suzuki K Poulose Changes in V4: 1. Use "coresight_get_source(path)" in the function "coresight_disable_path_from" instead of explicitly passing the source. -- Suzuki K Poulose 2. Optimize the order of the input parameters for "_coresight_build_path". -- Suzuki K Poulose 3. Reuse the method "coresight_block_source" in "_coresight_build_path". -- Suzuki K Poulose 4. Remove the unnecessary () in "coresight_build_path". -- Suzuki K Poulose 5. Add a helper to check if a device is SOURCE. -- Suzuki K Poulose 6. Adjust the posistion of setting "still_orphan" in "coresight_build_path". -- Suzuki K Poulose Changes in V3: 1. Rename the function "coresight_source_filter" to "coresight_block_source". And refine this function. -- Suzuki K Poulose 2. Rename the parameters of the function "coresight_find_out_connection" to avoid confusion. -- Suzuki K Poulose 3. Get the source of path in "coresight_enable_path" and "coresight_disable_path". -- Suzuki K Poulose 4. Fix filter source device before skip the port in "coresight_orphan_match". -- Suzuki K Poulose 5. Make sure the device still orphan if whter is a filter source firmware node but the filter source device is null. -- Suzuki K Poulose 6. Walk through the entire coresight bus and fixup the "filter_src_dev" if the source is being removed. -- Suzuki K Poulose 7. Refine the commit description of patch#2. -- Suzuki K Poulose 8. Fix the warning reported by kernel test robot. -- kernel test robot. 9. Use the source device directly if the port has a hardcoded filter in "tpda_get_element_size". -- Suzuki K Poulose Changes in V2: 1. Change the reference for endpoint property in dt-binding. -- Krzysztof Kozlowski 2. Change the property name "filter_src" to "filter-src". -- Krzysztof Kozlowski 3. Fix the errors in running 'make dt_binding_check'. -- Rob Herring 4. Pass in the source parameter instead of path. -- Suzuki K Poulose 5. Reset the "filter_src_dev" if the "src" csdev is being removed. -- Suzuki K Poulose 6. Add a warning if the "filter_src_dev" is of not the type DEV_TYPE_SOURCE. -- Suzuki K Poulose 7. Optimize the procedure for handling all possible cases. -- Suzuki K Poulose Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (4): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add a helper to check if a device is source coresight: Add support for trace filtering by source coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 19 ++- drivers/hwtracing/coresight/coresight-core.c | 113 +++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 21 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 13 +- include/linux/coresight.h | 12 +- 5 files changed, 155 insertions(+), 23 deletions(-) -- 2.17.1

3 months, 2 weeks

[PATCH v2 0/3] Extend logging on TMC start / stop errors

by Mike Leach

Extend logging on TMC start / stop errors Recent issues with trying to debug TMC timeouts and flush issues shows a general lack of logging and context around the possible errors Add logging to general wait for stop coresight routines and return values of watched registers. Update TMC to use this logging. Changes since v1: Rebase to coresight/next (kernel 6.13-rc2) Mike Leach (3): coresight: Update timeout functions to allow return of test register value coresight: tmc: Update error logging in tmc common functions coresight: etf: etr: Update logging around flush_and_stop() errors drivers/hwtracing/coresight/coresight-core.c | 50 +++++++++++++++---- .../hwtracing/coresight/coresight-tmc-core.c | 37 +++++++++++--- .../hwtracing/coresight/coresight-tmc-etf.c | 12 +++-- .../hwtracing/coresight/coresight-tmc-etr.c | 8 ++- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- include/linux/coresight.h | 2 + 6 files changed, 86 insertions(+), 25 deletions(-) -- 2.25.1

3 months, 2 weeks

[PATCH v1 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Mao Jinlong (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 14 ++ .../hwtracing/coresight/coresight-cti-core.c | 75 +++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 123 +++++++++++------ 5 files changed, 253 insertions(+), 99 deletions(-) -- 2.41.0

3 months, 2 weeks

[PATCH] selftests: arm coresight: sysfsmode testing

by Linu Cherian

Add sysfs mode selftest for ARM Coresight hardware tracer. Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- .../drivers/hwtracing/coresight/Makefile | 5 + .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 tools/testing/selftests/drivers/hwtracing/coresight/Makefile create mode 100755 tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile new file mode 100644 index 000000000000..7dc68ae1c0a9 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +TEST_PROGS = sysfs_test_trace.sh + +include ../../../lib.mk diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh new file mode 100755 index 000000000000..0d6307fff1d2 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh @@ -0,0 +1,144 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2024 Marvell. + +# Test Arm CoreSight trace capture in sysfs mode +# Based on tools/perf/tests/shell/test_arm_coresight.sh + +glb_err=0 + +arm_cs_report() { + if [ $2 != 0 ]; then + echo "$1: FAIL" + glb_err=$2 + else + echo "$1: PASS" + fi +} + +is_device_sink() { + # If the node of "enable_sink" is existed under the device path, this + # means the device is a sink device. + + if [ -e "$1/enable_sink" ]; then + + return 0 + else + return 1 + fi +} + +# Configure sink for buffer mode +cfg_sink_buf_mode() { + sink_dev=$1 + mode=$2 + # Set buffer mode if supported + if [ -e "$sink_dev/buf_modes_available" ]; then + cat $sink_dev/buf_modes_available | grep -E -q $mode + if [ $? -eq 0 ]; then + echo $mode > $sink_dev/buf_mode_preferred + return 0 + fi + fi + + return 1 +} + +run_app() { + + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 +} + +sysfs_trace() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Enable sink device + echo 1 > $sink_dev/enable_sink + # Enable source device + echo 1 > $src_dev/enable_source + + # Run app to be traced + run_app $cpu + + # Read back trace data + dd if=/dev/$sink_dev_name of=/tmp/tracedata + + # Verify if read is successful + err=$? + + # Disable source device + echo 0 > $src_dev/enable_source + + # Diskable sink device + echo 0 > $sink_dev/enable_sink + + arm_cs_report "CoreSight path testing (CPU$cpu -> $sink_dev_name)" $err +} + +try_sysfs_trace_resrv_buf() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Configure the resrved buffer mode if available + cfg_sink_buf_mode $sink_dev "resrv" + if [ $? -eq 0 ]; then + echo "Running sysfs trace with resrv buf mode" + sysfs_trace $src_dev $sink_dev $cpu + # Restore buffer mode + cfg_sink_buf_mode $sink_dev "auto" + if [ $? -eq 1 ]; then + echo "Failed to restore default buf mode" + fi + fi +} + +arm_cs_iterate_devices() { + src_dev=$1 + cpu=$3 + for cdev in $2/connections/out\:*; do + + # Skip testing if it's not a directory + ! [ -d $cdev ] && continue; + + # Read out its symbol link file name + sink_dev=`readlink -f $cdev` + + # Extract device name from path, e.g. + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' + # `> sink_dev_name = 'tmc_etf0' + sink_dev_name=$(basename $sink_dev) + + if is_device_sink $sink_dev; then + # Run trace with resrv buf mode (if available) + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu + + # Run the default mode + echo "Running sysfs trace with default settings" + sysfs_trace $src_dev $sink_dev $cpu + fi + + arm_cs_iterate_devices $src_dev $cdev $cpu + + done +} + +arm_cs_etm_traverse_path_test() { + # Iterate for every ETM device + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do + # Canonicalize the path + dev=`readlink -f $dev` + + # Find the ETM device belonging to which CPU + cpu=`cat $dev/cpu` + + # Use depth-first search (DFS) to iterate outputs + arm_cs_iterate_devices $dev $dev $cpu + done +} + +arm_cs_etm_traverse_path_test + +exit $glb_err -- 2.34.1

3 months, 2 weeks

Re: [PATCH] selftests: arm coresight: sysfsmode testing

by Linu Cherian

Hi, On 2024-12-04 at 05:53:56, Shuah Khan (skhan(a)linuxfoundation.org) wrote: > On 11/29/24 01:38, Linu Cherian wrote: > > Add sysfs mode selftest for ARM Coresight hardware tracer. > > Please add details on what this test does in here. Include > the output from the test? Ack. Will add test descripion here. > > Does this test have dependencies on config? If it does, does > this test detect and skip if config isn't enabled? Will add dependency. Thanks. > > > > > Signed-off-by: Linu Cherian <lcherian(a)marvell.com> > > --- > > .../drivers/hwtracing/coresight/Makefile | 5 + > > .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ > > 2 files changed, 149 insertions(+) > > create mode 100644 tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > create mode 100755 tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > > > diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > new file mode 100644 > > index 000000000000..7dc68ae1c0a9 > > --- /dev/null > > +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile > > @@ -0,0 +1,5 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > + > > +TEST_PROGS = sysfs_test_trace.sh > > + > > +include ../../../lib.mk > > diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > new file mode 100755 > > index 000000000000..0d6307fff1d2 > > --- /dev/null > > +++ b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh > > @@ -0,0 +1,144 @@ > > +#!/bin/sh > > +# SPDX-License-Identifier: GPL-2.0 > > +# Copyright (C) 2024 Marvell. > > + > > +# Test Arm CoreSight trace capture in sysfs mode > > +# Based on tools/perf/tests/shell/test_arm_coresight.sh > > + > > +glb_err=0 > > + > > +arm_cs_report() { > > + if [ $2 != 0 ]; then > > + echo "$1: FAIL" > > + glb_err=$2 > > + else > > + echo "$1: PASS" > > + fi > > +} > > + > > +is_device_sink() { > > + # If the node of "enable_sink" is existed under the device path, this > > + # means the device is a sink device. > > + > > + if [ -e "$1/enable_sink" ]; then > > + > > + return 0 > > + else > > + return 1 > > + fi > > +} > > + > > +# Configure sink for buffer mode > > +cfg_sink_buf_mode() { > > + sink_dev=$1 > > + mode=$2 > > + # Set buffer mode if supported > > + if [ -e "$sink_dev/buf_modes_available" ]; then > > + cat $sink_dev/buf_modes_available | grep -E -q $mode > > + if [ $? -eq 0 ]; then > > + echo $mode > $sink_dev/buf_mode_preferred > > + return 0 > > + fi > > + fi > > + > > + return 1 > > +} > > + > > +run_app() { > > + > > + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 > > +} > > + > > +sysfs_trace() { > > + src_dev=$1 > > + sink_dev=$2 > > + cpu=$3 > > + > > + # Enable sink device > > + echo 1 > $sink_dev/enable_sink > > + # Enable source device > > + echo 1 > $src_dev/enable_source > > + > > + # Run app to be traced > > + run_app $cpu > > + > > + # Read back trace data > > + dd if=/dev/$sink_dev_name of=/tmp/tracedata > > + > > + # Verify if read is successful > > + err=$? > > + > > + # Disable source device > > + echo 0 > $src_dev/enable_source > > + > > + # Diskable sink device > > + echo 0 > $sink_dev/enable_sink > > + > > + arm_cs_report "CoreSight path testing (CPU$cpu -> $sink_dev_name)" $err > > +} > > + > > +try_sysfs_trace_resrv_buf() { > > + src_dev=$1 > > + sink_dev=$2 > > + cpu=$3 > > + > > + # Configure the resrved buffer mode if available > > + cfg_sink_buf_mode $sink_dev "resrv" > > + if [ $? -eq 0 ]; then > > + echo "Running sysfs trace with resrv buf mode" > > + sysfs_trace $src_dev $sink_dev $cpu > > + # Restore buffer mode > > + cfg_sink_buf_mode $sink_dev "auto" > > + if [ $? -eq 1 ]; then > > + echo "Failed to restore default buf mode" > > + fi > > + fi > > +} > > + > > +arm_cs_iterate_devices() { > > + src_dev=$1 > > + cpu=$3 > > + for cdev in $2/connections/out\:*; do > > + > > + # Skip testing if it's not a directory > > + ! [ -d $cdev ] && continue; > > + > > + # Read out its symbol link file name > > + sink_dev=`readlink -f $cdev` > > + > > + # Extract device name from path, e.g. > > + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' > > + # `> sink_dev_name = 'tmc_etf0' > > + sink_dev_name=$(basename $sink_dev) > > + > > + if is_device_sink $sink_dev; then > > + # Run trace with resrv buf mode (if available) > > + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu > > + > > + # Run the default mode > > + echo "Running sysfs trace with default settings" > > + sysfs_trace $src_dev $sink_dev $cpu > > + fi > > + > > + arm_cs_iterate_devices $src_dev $cdev $cpu > > + > > + done > > +} > > + > > +arm_cs_etm_traverse_path_test() { > > + # Iterate for every ETM device > > + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do > > + # Canonicalize the path > > + dev=`readlink -f $dev` > > + > > + # Find the ETM device belonging to which CPU > > + cpu=`cat $dev/cpu` > > + > > + # Use depth-first search (DFS) to iterate outputs > > + arm_cs_iterate_devices $dev $dev $cpu > > + done > > +} > > + > > +arm_cs_etm_traverse_path_test > > + > > +exit $glb_err > > thanks, > -- Shuah >

3 months, 2 weeks

Re: [PATCH v2] coresight-etm4x: add isb() before reading the TRCSTATR

by Yuanfang Zhang

On 12/4/2024 11:16 PM, Leo Yan wrote: > Hi Yuanfang, > > Recently I just acrossed this part, so some comments. > > On Wed, Dec 04, 2024 at 07:23:32PM +0800, yuanfang zhang wrote: >> >> From: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> >> As recommended by section 4.3.7 ("Synchronization when using system >> instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> self-hosted trace analyzer must perform a Context synchronization >> event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> >> Fixes: ebddaad09e10 ("coresight: etm4x: Add missing single-shot control API to sysfs") >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> --- >> Change in V2: >> Added comments in the code. >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 66d44a404ad0..decb3a87e27e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -906,6 +906,13 @@ static void etm4_disable_hw(void *info) >> tsb_csync(); >> etm4x_relaxed_write32(csa, control, TRCPRGCTLR); >> >> + /* >> + * As recommended by section 4.3.7 ("Synchronization when using system >> + * instructions to progrom the trace unit") of ARM IHI 0064H.b, the >> + * self-hosted trace analyzer must perform a Context synchronization >> + * event between writing to the TRCPRGCTLR and reading the TRCSTATR. >> + */ >> + isb(); > > As described in the doc, the "isb" is only required for system > instructions case. It is good to only apply the ISB on system > register case: > > if (!csa->io_mem) > isb(); > updated in PATCH V3. >> /* wait for TRCSTATR.PMSTABLE to go to '1' */ >> if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) >> dev_err(etm_dev, > > As mentioned in system register case: "Arm recommends that the > self-hosted trace analyzer always executes an ISB instruction after > programming the trace unit registers, to ensure that all updates are > committed to the trace unit before normal code execution resumes." > > And for MMIO case: > > "When the memory is marked as Device-nGnRE or stronger. > ... > - Poll TRCSTATR to ensure the previous write has completed. > — Execute an ISB operation." > > Thus we need to add an ISB after polling. > > isb(); > updated in PATCH V3. > For consistent behaviour, a relevant thing is the dsb(sy) in > etm4_enable_hw(). I do not think the dsb(sy) is necessary, as the > driver uses the sequence "write TRCPRGCTLR + polling TRCSTATR" to > ensure the data has been populated to trace unit, the polling > operations somehow act as a read back. And the ETM manual does not > mention the requirement for DSB when enabling trace unit. Thus, we > should remove dsb(sy) (maybe use a separte patch). > updated in PATCH V3. > Mike / Suzuki / James, please confirm if my conclusions are valid. > > Thanks, > Leo

3 months, 2 weeks

[PATCH v12 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.12.rc4 * Patches 1 & 2 adds support for allocation of trace buffer pages from reserved RAM * Patches 3 & 4 adds support for saving metadata at the time of kernel panic * Patch 5 adds support for reading trace data captured at the time of panic * Patches 6 & 7 adds support for disabling coresight blocks at the time of panic * Patch 8: Gives the full description about this feature as part of documentation V11 is posted here, https://lore.kernel.org/linux-arm-kernel/20241111124746.2210378-1-lcherian@… Changelog from v11: Convert all commands to literal code blocks, that was missed out in v11. No other code changes. Changelog from v10: * Converted all csdev_access_* to readl functions in tmc_panic_sync_* * Added "tmc" prefix for register snapshots in struct tmc_crash_metadata * Converted dev_info to dev_dbg in panic handlers * Converted dsb to dmb in panic handlers * Fixed marking metadata as invalid when a user is trying to use the reserved buffer. Earlier this was wrongly set at the time of reading reserved trace buffer. * Moved common validation checks to is_tmc_crashdata_valid and minor code rearrangements for efficiency * Got rid of sink specific prepare/unprepare invocations * Got rid of full from struct tmc_resrv_buf * While reading crashdata, size is now calculated from metdata instead of relying on reserved buffer size populated by dtb * Minor documenation fixes Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 362 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 ++ .../hwtracing/coresight/coresight-tmc-core.c | 326 +++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 181 ++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 104 +++++ include/linux/coresight.h | 12 + 12 files changed, 1222 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

3 months, 2 weeks

Re: [PATCH v5 0/2] coresight: Add label sysfs node support

by Jinlong Mao

On 2024/12/11 16:46, Krzysztof Kozlowski wrote: > On Tue, Dec 10, 2024 at 08:22:51PM +0800, Mao Jinlong wrote: >> With current design, the name of the non-cpu bounded coresight >> component is the device type with the number. And with 'ls' command >> we can get the register address of the component. But from these >> information, we can't know what the HW or system the component belongs >> to. Add label in DT and show the hw information by reading label sysfs >> node. >> >> cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 >> cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 >> tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0 >> tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1 >> tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2 >> >> /sys/bus/coresight/devices # cat cti*/label >> cti_dlct_0 >> cti_dlct_1 >> cti_apss_0 >> cti_apss_1 >> cti_apss_2 >> >> Change since V4: >> 1. Add label in DT and add label sysfs node for each coresight device. > > This is v5, no links to previous versions (I really suggest to start > using b4 if you want to make your process easier for you), no other > changes so subject is obviously the same and looking for this patchset > previous versions gives me 0 results: > > https://lore.kernel.org/all/?q=%22coresight%3A+Add+label+sysfs+node+support… > > OK, let's try b4 diff: > > b4 diff '20241210122253.31926-1-quic_jinlmao(a)quicinc.com' > Grabbing thread from lore.kernel.org/all/20241210122253.31926-1-quic_jinlmao@quicinc.com/t.mbox.… > Checking for older revisions > Grabbing search results from lore.kernel.org > Nothing matching that query. > --- > Analyzing 3 messages in the thread > Could not find lower series to compare against. > > > So how do you expect us to do any meaningful review? > > Best regards, > Krzysztof I will resend the patches with the links of lower series. >

3 months, 2 weeks

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CoreSight December 2024