CoreSight December 2024

coresight@lists.linaro.org

9 participants
48 discussions

Re: [PATCH] coresight: Fix dsb_mode_store() unsigned val is never less than zero

by Suzuki K Poulose

On Thu, 21 Nov 2024 10:40:03 +0800, Pei Xiao wrote: > dsb_mode_store() warn: unsigned 'val' is never less than zero. > > Applied, thanks! [1/1] coresight: Fix dsb_mode_store() unsigned val is never less than zero https://git.kernel.org/coresight/c/d4276259f3a57131291d879b53fc05863c6b59fa Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 months, 1 week

[PATCH v7 0/3] coresight: Add static trace id support

by Mao Jinlong

Some HW has static trace id which cannot be changed via software programming. For this case, configure the trace id in device tree with "arm,static-trace-id = <xxx>", and call coresight_trace_id_get_static_system_id with the trace id value in device probe function. The id will be reserved for the HW all the time if the device is probed. Changes since V6: 1. Add code to handle a case where the preferred_id is not valid when use static id. 2. Returen busy when static id is not freed. Changes since V5: 1. Remove the warn for staic id not available. 2. Drop the system_id if registering the coresight device fails. 3. Return busy when static id is not available in dummy driver. Changes since V4: 1. Use fwnode_property_read_u32 in fwnode_property_read_u32. 2. Update date and version in sysfs-bus-coresight-devices-dummy-source Changes since V3: 1. Adda new API function int coresight_trace_id_get_system_static_id(int trace_id). 2. Use the term "static trace id" for these devices where the hardware sets a non-programmable trace ID. Changes since V2: 1. Change "trace-id" to "arm,trace-id". 2. Add trace id flag for getting preferred id or ODD id. Changes since V1: 1. Add argument to coresight_trace_id_get_system_id for preferred id instead of adding new function coresight_trace_id_reserve_system_id. 2. Add constraint to trace-id in dt-binding file. Mao Jinlong (3): dt-bindings: arm: Add arm,static-trace-id for coresight dummy source coresight: Add support to get static id for system trace sources coresight: dummy: Add static trace id support for dummy source .../sysfs-bus-coresight-devices-dummy-source | 15 ++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++ drivers/hwtracing/coresight/coresight-dummy.c | 81 ++++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 6 ++ .../hwtracing/coresight/coresight-trace-id.c | 43 +++++++--- .../hwtracing/coresight/coresight-trace-id.h | 9 +++ include/linux/coresight.h | 1 + 7 files changed, 140 insertions(+), 21 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source -- 2.17.1

4 months, 1 week

[PATCH] coresight: Drop atomics in connection refcounts

by James Clark

These belong to the device being enabled or disabled and are only ever used inside the device's spinlock. Remove the atomics to not imply that there are any other concurrent accesses. If atomics were necessary I don't think they would have been enough anyway. There would be nothing to prevent an enable or disable running concurrently if not for the spinlock. Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-funnel.c | 6 +++--- drivers/hwtracing/coresight/coresight-replicator.c | 6 +++--- drivers/hwtracing/coresight/coresight-tpda.c | 6 +++--- include/linux/coresight.h | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 5a819c8970fb..bd32f74cbdae 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -86,14 +86,14 @@ static int funnel_enable(struct coresight_device *csdev, bool first_enable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_read(&in->dest_refcnt) == 0) { + if (in->dest_refcnt == 0) { if (drvdata->base) rc = dynamic_funnel_enable_hw(drvdata, in->dest_port); if (!rc) first_enable = true; } if (!rc) - atomic_inc(&in->dest_refcnt); + in->dest_refcnt++; spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) @@ -130,7 +130,7 @@ static void funnel_disable(struct coresight_device *csdev, bool last_disable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_dec_return(&in->dest_refcnt) == 0) { + if (--in->dest_refcnt == 0) { if (drvdata->base) dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable = true; diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 3e55be9c8418..31322aea19f2 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -126,7 +126,7 @@ static int replicator_enable(struct coresight_device *csdev, bool first_enable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_read(&out->src_refcnt) == 0) { + if (out->src_refcnt == 0) { if (drvdata->base) rc = dynamic_replicator_enable(drvdata, in->dest_port, out->src_port); @@ -134,7 +134,7 @@ static int replicator_enable(struct coresight_device *csdev, first_enable = true; } if (!rc) - atomic_inc(&out->src_refcnt); + out->src_refcnt++; spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) @@ -180,7 +180,7 @@ static void replicator_disable(struct coresight_device *csdev, bool last_disable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_dec_return(&out->src_refcnt) == 0) { + if (--out->src_refcnt == 0) { if (drvdata->base) dynamic_replicator_disable(drvdata, in->dest_port, out->src_port); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index bfca103f9f84..4ec676bea1ce 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -190,10 +190,10 @@ static int tpda_enable(struct coresight_device *csdev, int ret = 0; spin_lock(&drvdata->spinlock); - if (atomic_read(&in->dest_refcnt) == 0) { + if (in->dest_refcnt == 0) { ret = __tpda_enable(drvdata, in->dest_port); if (!ret) { - atomic_inc(&in->dest_refcnt); + in->dest_refcnt++; csdev->refcnt++; dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); } @@ -223,7 +223,7 @@ static void tpda_disable(struct coresight_device *csdev, struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock(&drvdata->spinlock); - if (atomic_dec_return(&in->dest_refcnt) == 0) { + if (--in->dest_refcnt == 0) { __tpda_disable(drvdata, in->dest_port); csdev->refcnt--; } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c13342594278..834029cb9ba2 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -200,8 +200,8 @@ struct coresight_connection { struct coresight_device *dest_dev; struct coresight_sysfs_link *link; struct coresight_device *src_dev; - atomic_t src_refcnt; - atomic_t dest_refcnt; + int src_refcnt; + int dest_refcnt; }; /** -- 2.34.1

4 months, 1 week

[PATCH v5 0/2] coresight: Add label sysfs node support

by Mao Jinlong

With current design, the name of the non-cpu bounded coresight component is the device type with the number. And with 'ls' command we can get the register address of the component. But from these information, we can't know what the HW or system the component belongs to. Add label in DT and show the hw information by reading label sysfs node. cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0 tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1 tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2 /sys/bus/coresight/devices # cat cti*/label cti_dlct_0 cti_dlct_1 cti_apss_0 cti_apss_1 cti_apss_2 Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++++ .../sysfs-bus-coresight-devices-funnel | 6 ++++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++++ .../bindings/arm/arm,coresight-cti.yaml | 6 ++++ .../arm/arm,coresight-dummy-sink.yaml | 6 ++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++++ .../arm/arm,coresight-dynamic-funnel.yaml | 6 ++++ .../arm/arm,coresight-dynamic-replicator.yaml | 6 ++++ .../arm/arm,coresight-static-funnel.yaml | 6 ++++ .../arm/arm,coresight-static-replicator.yaml | 6 ++++ .../bindings/arm/arm,coresight-tmc.yaml | 6 ++++ .../bindings/arm/qcom,coresight-tpda.yaml | 6 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 6 ++++ drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++++++++++++++++++ 14 files changed, 110 insertions(+) -- 2.17.1

4 months, 1 week

[PATCH v6 0/4] source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V6: 1. Optimize the prompt content of the warning log when the filter handle is not a trace source. -- Suzuki K Poulose 2. Reset the filter device and fwnode if it is not a trace source. -- Suzuki K Poulose Changes in V5: 1. Replace "filter-src" with "filter-source" in the dt-binding document. -- Suzuki K Poulose 2. Optimize the comments of the patch "coresight: Add support for trace filtering by source" due to bad example. -- Suzuki K Poulose 3. Correct spelling errors in the patch "coresight: Add support for trace filtering by source". -- Suzuki K Poulose 4. Optimize the function "coresight_blocks_source". -- Suzuki K Poulose 5. Add { } in the function "of_coresight_parse_endpoint". -- Suzuki K Poulose 6. Adjust the order of the patches. -- Suzuki K Poulose 7. Adjust the alignment in "coresight-platform.c". -- Suzuki K Poulose Changes in V4: 1. Use "coresight_get_source(path)" in the function "coresight_disable_path_from" instead of explicitly passing the source. -- Suzuki K Poulose 2. Optimize the order of the input parameters for "_coresight_build_path". -- Suzuki K Poulose 3. Reuse the method "coresight_block_source" in "_coresight_build_path". -- Suzuki K Poulose 4. Remove the unnecessary () in "coresight_build_path". -- Suzuki K Poulose 5. Add a helper to check if a device is SOURCE. -- Suzuki K Poulose 6. Adjust the posistion of setting "still_orphan" in "coresight_build_path". -- Suzuki K Poulose Changes in V3: 1. Rename the function "coresight_source_filter" to "coresight_block_source". And refine this function. -- Suzuki K Poulose 2. Rename the parameters of the function "coresight_find_out_connection" to avoid confusion. -- Suzuki K Poulose 3. Get the source of path in "coresight_enable_path" and "coresight_disable_path". -- Suzuki K Poulose 4. Fix filter source device before skip the port in "coresight_orphan_match". -- Suzuki K Poulose 5. Make sure the device still orphan if whter is a filter source firmware node but the filter source device is null. -- Suzuki K Poulose 6. Walk through the entire coresight bus and fixup the "filter_src_dev" if the source is being removed. -- Suzuki K Poulose 7. Refine the commit description of patch#2. -- Suzuki K Poulose 8. Fix the warning reported by kernel test robot. -- kernel test robot. 9. Use the source device directly if the port has a hardcoded filter in "tpda_get_element_size". -- Suzuki K Poulose Changes in V2: 1. Change the reference for endpoint property in dt-binding. -- Krzysztof Kozlowski 2. Change the property name "filter_src" to "filter-src". -- Krzysztof Kozlowski 3. Fix the errors in running 'make dt_binding_check'. -- Rob Herring 4. Pass in the source parameter instead of path. -- Suzuki K Poulose 5. Reset the "filter_src_dev" if the "src" csdev is being removed. -- Suzuki K Poulose 6. Add a warning if the "filter_src_dev" is of not the type DEV_TYPE_SOURCE. -- Suzuki K Poulose 7. Optimize the procedure for handling all possible cases. -- Suzuki K Poulose Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (4): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add a helper to check if a device is source coresight: Add support for trace filtering by source coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 19 ++- drivers/hwtracing/coresight/coresight-core.c | 113 +++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 21 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 13 +- include/linux/coresight.h | 12 +- 5 files changed, 155 insertions(+), 23 deletions(-) -- 2.17.1

4 months, 1 week

Re: [PATCH] selftests: arm coresight: sysfsmode testing

by James Clark

On 04/12/2024 12:23 am, Shuah Khan wrote: > On 11/29/24 01:38, Linu Cherian wrote: >> Add sysfs mode selftest for ARM Coresight hardware tracer. > > Please add details on what this test does in here. Include > the output from the test? > > Does this test have dependencies on config? If it does, does > this test detect and skip if config isn't enabled? > Without the config the test won't find any devices and it will still pass. But yes it would still be good to explicitly mark the dependency. >> >> Signed-off-by: Linu Cherian <lcherian(a)marvell.com> >> --- >> .../drivers/hwtracing/coresight/Makefile | 5 + >> .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ >> 2 files changed, 149 insertions(+) >> create mode 100644 tools/testing/selftests/drivers/hwtracing/ >> coresight/Makefile >> create mode 100755 tools/testing/selftests/drivers/hwtracing/ >> coresight/sysfs_test_trace.sh >> >> diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/ >> Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile >> new file mode 100644 >> index 000000000000..7dc68ae1c0a9 >> --- /dev/null >> +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile >> @@ -0,0 +1,5 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> + >> +TEST_PROGS = sysfs_test_trace.sh >> + >> +include ../../../lib.mk >> diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/ >> sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/ >> coresight/sysfs_test_trace.sh >> new file mode 100755 >> index 000000000000..0d6307fff1d2 >> --- /dev/null >> +++ b/tools/testing/selftests/drivers/hwtracing/coresight/ >> sysfs_test_trace.sh >> @@ -0,0 +1,144 @@ >> +#!/bin/sh >> +# SPDX-License-Identifier: GPL-2.0 >> +# Copyright (C) 2024 Marvell. >> + >> +# Test Arm CoreSight trace capture in sysfs mode >> +# Based on tools/perf/tests/shell/test_arm_coresight.sh >> + >> +glb_err=0 >> + >> +arm_cs_report() { >> + if [ $2 != 0 ]; then >> + echo "$1: FAIL" >> + glb_err=$2 >> + else >> + echo "$1: PASS" >> + fi >> +} >> + >> +is_device_sink() { >> + # If the node of "enable_sink" is existed under the device path, >> this >> + # means the device is a sink device. >> + >> + if [ -e "$1/enable_sink" ]; then >> + >> + return 0 >> + else >> + return 1 >> + fi >> +} >> + >> +# Configure sink for buffer mode >> +cfg_sink_buf_mode() { >> + sink_dev=$1 >> + mode=$2 >> + # Set buffer mode if supported >> + if [ -e "$sink_dev/buf_modes_available" ]; then >> + cat $sink_dev/buf_modes_available | grep -E -q $mode >> + if [ $? -eq 0 ]; then >> + echo $mode > $sink_dev/buf_mode_preferred >> + return 0 >> + fi >> + fi >> + >> + return 1 >> +} >> + >> +run_app() { >> + >> + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 >> +} >> + >> +sysfs_trace() { >> + src_dev=$1 >> + sink_dev=$2 >> + cpu=$3 >> + >> + # Enable sink device >> + echo 1 > $sink_dev/enable_sink >> + # Enable source device >> + echo 1 > $src_dev/enable_source >> + >> + # Run app to be traced >> + run_app $cpu >> + >> + # Read back trace data >> + dd if=/dev/$sink_dev_name of=/tmp/tracedata >> + >> + # Verify if read is successful >> + err=$? >> + >> + # Disable source device >> + echo 0 > $src_dev/enable_source >> + >> + # Diskable sink device >> + echo 0 > $sink_dev/enable_sink >> + >> + arm_cs_report "CoreSight path testing (CPU$cpu -> >> $sink_dev_name)" $err >> +} >> + >> +try_sysfs_trace_resrv_buf() { >> + src_dev=$1 >> + sink_dev=$2 >> + cpu=$3 >> + >> + # Configure the resrved buffer mode if available >> + cfg_sink_buf_mode $sink_dev "resrv" >> + if [ $? -eq 0 ]; then >> + echo "Running sysfs trace with resrv buf mode" >> + sysfs_trace $src_dev $sink_dev $cpu >> + # Restore buffer mode >> + cfg_sink_buf_mode $sink_dev "auto" >> + if [ $? -eq 1 ]; then >> + echo "Failed to restore default buf mode" >> + fi >> + fi >> +} >> + >> +arm_cs_iterate_devices() { >> + src_dev=$1 >> + cpu=$3 >> + for cdev in $2/connections/out\:*; do >> + >> + # Skip testing if it's not a directory >> + ! [ -d $cdev ] && continue; >> + >> + # Read out its symbol link file name >> + sink_dev=`readlink -f $cdev` >> + >> + # Extract device name from path, e.g. >> + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' >> + # `> sink_dev_name = 'tmc_etf0' >> + sink_dev_name=$(basename $sink_dev) >> + >> + if is_device_sink $sink_dev; then >> + # Run trace with resrv buf mode (if available) >> + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu >> + >> + # Run the default mode >> + echo "Running sysfs trace with default settings" >> + sysfs_trace $src_dev $sink_dev $cpu >> + fi >> + >> + arm_cs_iterate_devices $src_dev $cdev $cpu >> + >> + done >> +} >> + >> +arm_cs_etm_traverse_path_test() { >> + # Iterate for every ETM device >> + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do >> + # Canonicalize the path >> + dev=`readlink -f $dev` >> + >> + # Find the ETM device belonging to which CPU >> + cpu=`cat $dev/cpu` >> + >> + # Use depth-first search (DFS) to iterate outputs >> + arm_cs_iterate_devices $dev $dev $cpu >> + done >> +} >> + >> +arm_cs_etm_traverse_path_test >> + >> +exit $glb_err > > thanks, > -- Shuah >

4 months, 2 weeks

Re: [PATCH] coresight-etm4x: add isb() before reading the TRCSTATR

by Suzuki K Poulose

Hi On 04/12/2024 10:13, yuanfang zhang wrote: > From: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> > > As recommended by section 4.3.7 ("Synchronization when using system > instructions to progrom the trace unit") of ARM IHI 0064H.b, the > self-hosted trace analyzer must perform a Context synchronization > event between writing to the TRCPRGCTLR and reading the TRCSTATR. > Thanks for the patch. Please could you add the above in a comment in the changes below ? Also, add Fixes tag ? (It may go all the way back to initial support) Otherwise looks sensible to me. Suzuki > Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 66d44a404ad0..5da2c523c30a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -906,6 +906,7 @@ static void etm4_disable_hw(void *info) > tsb_csync(); > etm4x_relaxed_write32(csa, control, TRCPRGCTLR); > > + isb(); > /* wait for TRCSTATR.PMSTABLE to go to '1' */ > if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) > dev_err(etm_dev,

4 months, 2 weeks

Re: [PATCH 3/4] coresight: tmc-etr: Fix race condition between sysfs and perf mode

by Suzuki K Poulose

Hi Yicong On 02/12/2024 09:24, Yicong Yang wrote: > From: Yicong Yang <yangyicong(a)hisilicon.com> > > When trying to run perf and sysfs mode simultaneously, the WARN_ON() > in tmc_etr_enable_hw() is triggered sometimes: > > WARNING: CPU: 42 PID: 3911571 at drivers/hwtracing/coresight/coresight-tmc-etr.c:1060 tmc_etr_enable_hw+0xc0/0xd8 [coresight_tmc] > [..snip..] > Call trace: > tmc_etr_enable_hw+0xc0/0xd8 [coresight_tmc] (P) > tmc_enable_etr_sink+0x11c/0x250 [coresight_tmc] (L) > tmc_enable_etr_sink+0x11c/0x250 [coresight_tmc] > coresight_enable_path+0x1c8/0x218 [coresight] > coresight_enable_sysfs+0xa4/0x228 [coresight] > enable_source_store+0x58/0xa8 [coresight] > dev_attr_store+0x20/0x40 > sysfs_kf_write+0x4c/0x68 > kernfs_fop_write_iter+0x120/0x1b8 > vfs_write+0x2c8/0x388 > ksys_write+0x74/0x108 > __arm64_sys_write+0x24/0x38 > el0_svc_common.constprop.0+0x64/0x148 > do_el0_svc+0x24/0x38 > el0_svc+0x3c/0x130 > el0t_64_sync_handler+0xc8/0xd0 > el0t_64_sync+0x1ac/0x1b0 > ---[ end trace 0000000000000000 ]--- > > Since the enablement of sysfs mode is separeted into two critical regions, > one for sysfs buffer allocation and another for hardware enablement, it's > possible to race with the perf mode. Fix this by double check whether > the perf mode's been used before enabling the hardware in sysfs mode. Thanks for the fix. Some minor comments below. It needs a Fixes tag. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > .../hwtracing/coresight/coresight-tmc-etr.c | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index ad83714ca4dc..d382d95da5ff 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1230,6 +1230,36 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) > > spin_lock_irqsave(&drvdata->spinlock, flags); > > + /* > + * Since the sysfs buffer allocation and the hardware enablement is not > + * in the same critical region, it's possible to race with the perf > + * mode: > + * [sysfs mode] [perf mode] > + * tmc_etr_get_sysfs_buffer() > + * spin_lock(&drvdata->spinlock) > + * [sysfs buffer allocation] > + * spin_unlock(&drvdata->spinlock) > + * spin_lock(&drvdata->spinlock) > + * tmc_etr_enable_hw() > + * drvdata->etr_buf = etr_perf->etr_buf > + * spin_unlock(&drvdata->spinlock) > + * spin_lock(&drvdata->spinlock) > + * tmc_etr_enable_hw() > + * WARN_ON(drvdata->etr_buf) // WARN sicne etr_buf initialized at > + * the perf side > + * spin_unlock(&drvdata->spinlock) > + * > + * So check here before continue. > + */ > + if (coresight_get_mode(csdev) == CS_MODE_PERF) { > + drvdata->sysfs_buf = NULL; > + spin_unlock_irqrestore(&drvdata->spinlock, flags); > + > + /* Free allocated memory out side of the spinlock */ > + tmc_etr_free_sysfs_buf(sysfs_buf); > + return -EBUSY; > + } With this in place, I think we should remove the check for CS_MODE_PERF in get_etr_sysfs_buf() to avoid confusion (which I believe opened up this race) Suzuki > + > /* > * In sysFS mode we can have multiple writers per sink. Since this > * sink is already enabled no memory is needed and the HW need not be

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CoreSight December 2024