CoreSight August 2024

coresight@lists.linaro.org

9 participants
48 discussions

Re: [PATCH v3 1/3] dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering

by Suzuki K Poulose

On 22/08/2024 08:08, Krzysztof Kozlowski wrote: > On Wed, Aug 21, 2024 at 11:38:55AM +0100, Suzuki K Poulose wrote: >> On 21/08/2024 04:13, Tao Zhang wrote: >>> The is some "magic" hard coded filtering in the replicators, >>> which only passes through trace from a particular "source". Add >>> a new property "filter-src" to label a phandle to the coresight >>> trace source device matching the hard coded filtering for the port. >> >> Minor nit: Please do not use abbreviate "source" in the bindings. >> I am not an expert on other changes below and will leave it to >> Rob/Krzysztof to comment. >> >> Rob, Krzysztof, >> >> We need someway to "link" (add a phandle) from a "port". The patch below >> is extending "standard" port to add a phandle. Please let us know if >> there is a better way. >> >> e.g.: >> >> filters = list of tuples of port, phandle. ? >> >> e.g.: >> >> filters = < 0, <&tpdm_video>, >> 1, <&tpdm_mdss> >> > >> > > Current solution feels like band-aid - what if next time you need some > second filter? Or "wall"? Or whatever? Next property? > > Isn't filter just one endpoint in the graph? > > A <--> filter <--> B To be more precise, "Filter" is a "port (p0, p1, p2 below)" (among a multi output ports). For clearer example: A0 <--> .. <--> ..\ p0 / --> Filtered for (A1) <--> B1 A1 <--> .. <--> .. - < L(filters> p1 - --> Filtered for (A2) <--> B2 A2 <--> .. <--> ../ p2 \ --> Unfiltered <--> B0 > Instead of > > A <----through-filter----> B? The problem is we need to know the components in the path from A0 to X through, (Not just A0 and L). And also we need to know "which port (p0 vs p1 vs p2)" does the traffic take from a source (A0/A1/A2) out of the link "L". So ideally, we need a way to tie p0 -> A1, p1 -> A2. would we need something else in the future ? I don't know for sure. People could design their own things ;-). But this was the first time ever in the last 12yrs since we supported coresight in the kernel. (there is always a first time). Fundamentally, the "ports" cannot have additional properties today. Not sure if there are other usecases (I don't see why). So, we have to manually extend like above, which I think is not nice. Happy to proceed with anything that seems acceptable for you folks. Suzuki > > Best regards, > Krzysztof >

2 months

[PATCH v4 0/3] coresight: Add static trace id support

by Mao Jinlong

Some HW has static trace id which cannot be changed via software programming. For this case, configure the trace id in device tree with "arm,static-trace-id = <xxx>", and call coresight_trace_id_get_static_system_id with the trace id value in device probe function. The id will be reserved for the HW all the time if the device is probed. Changes since V3: 1. Adda new API function int coresight_trace_id_get_system_static_id(int trace_id). 2. Use the term "static trace id" for these devices where the hardware sets a non-programmable trace ID. Changes since V2: 1. Change "trace-id" to "arm,trace-id". 2. Add trace id flag for getting preferred id or ODD id. Changes since V1: 1. Add argument to coresight_trace_id_get_system_id for preferred id instead of adding new function coresight_trace_id_reserve_system_id. 2. Add constraint to trace-id in dt-binding file. Mao Jinlong (3): dt-bindings: arm: Add arm,trace-id for coresight dummy source coresight: Add support to get static id for system trace sources coresight: dummy: Add static trace id support for dummy source .../sysfs-bus-coresight-devices-dummy-source | 15 +++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++ drivers/hwtracing/coresight/coresight-dummy.c | 59 +++++++++++++++++-- .../hwtracing/coresight/coresight-platform.c | 26 ++++++++ .../hwtracing/coresight/coresight-trace-id.c | 38 ++++++++---- .../hwtracing/coresight/coresight-trace-id.h | 9 +++ include/linux/coresight.h | 1 + 7 files changed, 140 insertions(+), 14 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source -- 2.41.0

2 months

[PATCH v6 00/17] coresight: Use per-sink trace ID maps for Perf sessions

by James Clark

This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs as long as there are fewer than that many ETMs connected to each sink. Each sink owns its own trace ID map, and any Perf session connecting to that sink will allocate from it, even if the sink is currently in use by other users. This is similar to the existing behavior where the dynamic trace IDs are constant as long as there is any concurrent Perf session active. It's not completely optimal because slightly more IDs will be used than necessary, but the optimal solution involves tracking the PIDs of each session and allocating ID maps based on the session owner. This is difficult to do with the combination of per-thread and per-cpu modes and some scheduling issues. The complexity of this isn't likely to worth it because even with multiple users they'd just see a difference in the ordering of ID allocations rather than hitting any limits (unless the hardware does have too many ETMs connected to one sink). Per-thread mode works but only until there are any overlapping IDs, at which point Perf will error out. Both per-thread mode and sysfs mode are left to future changes, but both can be added on top of this initial implementation and only sysfs mode requires further driver changes. The HW_ID version field hasn't been bumped in order to not break Perf which already has an error condition for other values of that field. Instead a new minor version has been added which signifies that there are new fields but the old fields are backwards compatible. Changes since v5: * Hide queue number printout behind -v option * Style change in cs_etm__process_aux_output_hw_id() * Move new format enum to an earlier commit to reduce churn Changes since v4: * Fix compilation failure when TRACE_ID_DEBUG is set * Expand comment about not freeing individual trace IDs in free_event_data() Changes since v3: * Fix issue where trace IDs were overwritten by possibly invalid ones by Perf in unformatted mode. Now the HW_IDs are also used for unformatted mode unless the kernel didn't emit any. * Add a commit to check the OpenCSD version. * Add a commit to not save invalid IDs in the Perf header. * Replace cs_etm_queue's formatted and formatted_set members with a single enum which is easier to use. * Drop CORESIGHT_TRACE_ID_UNUSED_FLAG as it's no longer needed. * Add a commit to print the queue number in the raw dump. * Don't assert on the number of unformatted decoders if decoders == 0. Changes since v2: * Rebase on coresight-next 6.10-rc2 (b9b25c8496). * Fix double free of csdev if device registration fails. * Fix leak of coresight_trace_id_perf_start() if trace ID allocation fails. * Don't resend HW_ID for sink changes in per-thread mode. The existing CPU field on AUX records can be used to track this instead. * Tidy function doc for coresight_trace_id_release_all() * Drop first two commits now that they are in coresight-next * Add a commit to make the trace ID spinlock local to the map Changes since V1: * Rename coresight_device.perf_id_map to perf_sink_id_map. * Instead of outputting a HW_ID for each reachable ETM, output the sink ID and continue to output only the HW_ID once for each mapping. * Keep the first two Perf patches so that it applies cleanly on coresight-next, although they have been applied on perf-tools-next * Add new *_map() functions to the trace ID public API instead of modifying existing ones. * Collapse "coresight: Pass trace ID map into source enable" into "coresight: Use per-sink trace ID maps for Perf sessions" because the first commit relied on the default map being accessible which is no longer necessary due to the previous bullet point. James Clark (17): perf: cs-etm: Create decoders after both AUX and HW_ID search passes perf: cs-etm: Allocate queues for all CPUs perf: cs-etm: Move traceid_list to each queue perf: cs-etm: Create decoders based on the trace ID mappings perf: cs-etm: Only save valid trace IDs into files perf: cs-etm: Support version 0.1 of HW_ID packets perf: cs-etm: Print queue number in raw trace dump perf: cs-etm: Add runtime version check for OpenCSD coresight: Remove unused ETM Perf stubs coresight: Clarify comments around the PID of the sink owner coresight: Move struct coresight_trace_id_map to common header coresight: Expose map arguments in trace ID API coresight: Make CPU id map a property of a trace ID map coresight: Use per-sink trace ID maps for Perf sessions coresight: Remove pending trace ID release mechanism coresight: Emit sink ID in the HW_ID packets coresight: Make trace ID map spinlock local to the map drivers/hwtracing/coresight/coresight-core.c | 37 +- drivers/hwtracing/coresight/coresight-dummy.c | 3 +- .../hwtracing/coresight/coresight-etm-perf.c | 43 +- .../hwtracing/coresight/coresight-etm-perf.h | 18 - .../coresight/coresight-etm3x-core.c | 9 +- .../coresight/coresight-etm4x-core.c | 9 +- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-stm.c | 3 +- drivers/hwtracing/coresight/coresight-sysfs.c | 3 +- .../hwtracing/coresight/coresight-tmc-etr.c | 5 +- drivers/hwtracing/coresight/coresight-tmc.h | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 3 +- .../hwtracing/coresight/coresight-trace-id.c | 138 ++-- .../hwtracing/coresight/coresight-trace-id.h | 70 +- include/linux/coresight-pmu.h | 17 +- include/linux/coresight.h | 21 +- tools/build/feature/test-libopencsd.c | 4 +- tools/include/linux/coresight-pmu.h | 17 +- tools/perf/Makefile.config | 2 +- tools/perf/arch/arm/util/cs-etm.c | 11 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 49 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 3 +- .../util/cs-etm-decoder/cs-etm-min-version.h | 13 + tools/perf/util/cs-etm.c | 629 +++++++++++------- tools/perf/util/cs-etm.h | 12 +- 25 files changed, 650 insertions(+), 475 deletions(-) create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-min-version.h -- 2.34.1

3 months, 2 weeks

[GIT PULL] coresight: Updates for Linux v6.12

by Suzuki K Poulose

Greg, Please find the updates for CoreSight/hwtracing subsystem for v6.12. Kindly pull Suzuki The following changes since commit 47ac09b91befbb6a235ab620c32af719f8208399: Linux 6.11-rc4 (2024-08-18 13:17:27 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.12 for you to fetch changes up to 988d40a4d4e7d671305bea501562a5d1a1d479fa: coresight: Make trace ID map spinlock local to the map (2024-08-20 15:02:38 +0100) ---------------------------------------------------------------- coresight: updates for Linux v6.12 CoreSight/hwtracing subsystem updates targeting Linux v6.12: - Miscellaneous fixes and cleanups - TraceID allocation per sink, allowing system with > 110 cores for perf tracing. Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- James Clark (9): coresight: Remove unused ETM Perf stubs coresight: Clarify comments around the PID of the sink owner coresight: Move struct coresight_trace_id_map to common header coresight: Expose map arguments in trace ID API coresight: Make CPU id map a property of a trace ID map coresight: Use per-sink trace ID maps for Perf sessions coresight: Remove pending trace ID release mechanism coresight: Emit sink ID in the HW_ID packets coresight: Make trace ID map spinlock local to the map Javier Carrasco (1): coresight: cti: use device_* to iterate over device child nodes Jie Gan (2): Coresight: Set correct cs_mode for TPDM to fix disable issue Coresight: Set correct cs_mode for dummy source to fix disable issue Suzuki K Poulose (1): coresight: tmc: sg: Do not leak sg_table drivers/hwtracing/coresight/coresight-core.c | 37 ++++-- .../hwtracing/coresight/coresight-cti-platform.c | 10 +- drivers/hwtracing/coresight/coresight-dummy.c | 7 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 43 ++++--- drivers/hwtracing/coresight/coresight-etm-perf.h | 18 --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 9 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-stm.c | 3 +- drivers/hwtracing/coresight/coresight-sysfs.c | 3 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 +- drivers/hwtracing/coresight/coresight-tmc.h | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 9 +- drivers/hwtracing/coresight/coresight-trace-id.c | 138 +++++++++------------ drivers/hwtracing/coresight/coresight-trace-id.h | 70 +++++------ include/linux/coresight-pmu.h | 17 ++- include/linux/coresight.h | 21 +++- 17 files changed, 219 insertions(+), 188 deletions(-)

3 months, 2 weeks

RFC: Add Qualcomm extended CTI support

by Jinlong Mao

Hi Suzuki & Mike & James, We have new CTI HW component called Qcom Extended CTI. The main difference of extended CTI to the normal CTI is that the address mapping is changed and it supports a max of 128 trigger signals. For the changes to CTI driver, I want to define the address mapping like below. Could you please help to provide your comments how can we make the changes to the different address mappings of Qcom extended CTI ? /* CTI programming registers */ +#define CTIINTACK(drvdata, n) ((drvdata->is_extended ? 0x020 : 0x010) + (4 * n)) +#define CTIAPPSET(drvdata) (drvdata->is_extended ? 0x004 : 0x014) +#define CTIAPPCLEAR(drvdata) (drvdata->is_extended ? 0x008 : 0x018) +#define CTIAPPPULSE(drvdata) (drvdata->is_extended ? 0x00C : 0x01C) +#define CTIINEN(drvdata, n) ((drvdata->is_extended ? 0x400 : 0x020) + (4 * n)) +#define CTIOUTEN(drvdata, n) ((drvdata->is_extended ? 0x800 : 0x0A0) + (4 * n)) +#define CTITRIGINSTATUS(drvdata, n) ((drvdata->is_extended ? 0x040 : 0x130) + (4 * n)) +#define CTITRIGOUTSTATUS(drvdata, n) ((drvdata->is_extended ? 0x060 : 0x134) + (4 * n)) +#define CTICHINSTATUS(drvdata) (drvdata->is_extended ? 0x080 : 0x138) +#define CTICHOUTSTATUS(drvdata) (drvdata->is_extended ? 0x084 : 0x13C) +#define CTIGATE(drvdata) (drvdata->is_extended ? 0x088 : 0x140) +#define ASICCTL(drvdata) (drvdata->is_extended ? 0x08C : 0x144) /* Integration test registers */ +#define ITCHINACK(drvdata) (drvdata->is_extended ? 0xE70 : 0xEDC) /* WO CTI CSSoc 400 only*/ +#define ITTRIGINACK(drvdata, n) ((drvdata->is_extended ? 0xE80 : 0xEE0) + (4 * n)) /* WO CTI CSSoc 400 only*/ +#define ITCHOUT(drvdata) (drvdata->is_extended ? 0xE74 : 0xEE4) /* WO RW-600 */ +#define ITTRIGOUT(drvdata, n) ((drvdata->is_extended ? 0xEA : 0xEE8) + (4 * n)) /* WO RW-600 */ +#define ITCHOUTACK(drvdata) (drvdata->is_extended ? 0xE78 : 0xEEC) /* RO CTI CSSoc 400 only*/ +#define ITTRIGOUTACK(drvdata, n) ((drvdata->is_extended ? 0xEC0 : 0xEF0) + (4 * n))/* RO CTI CSSoc 400 only*/ +#define ITCHIN(drvdata) (drvdata->is_extended ? 0xE7C : 0xEF4) /* RO */ +#define ITTRIGIN(drvdata, n) ((drvdata->is_extended ? 0xEE0 : 0xEF8) + (4 * n))/* RO */ Thanks Jinlong Mao

3 months, 2 weeks

Re: [PATCH V5 0/4] arm-cs-trace-disasm.py/perf must accommodate non-zero DSO text offset

by Steve Clevenger

On 8/30/2024 12:20 AM, Leo Yan wrote: > On 8/29/24 18:39, Steve Clevenger wrote:> >> On 8/29/2024 12:55 AM, Leo Yan wrote: >>> On 8/29/2024 12:17 AM, Steve Clevenger wrote: >>>> >>>> Changes in V5: >>>> - In symbol-elf.c, branch to exit_close label if open file. >>>> - In trace_event_python.c, correct indentation. set_sym_in_dict >>>> call parameter "map_pgoff" renamed as "addr_map_pgoff" to >>>> match local naming. >>> >>> For the series: >>> >>> Reviewed-by: Leo Yan <leo.yan(a)arm.com> >>> >>> Hi Steve, >>> >>> Later when you respin a new version patches, it is better to amend >>> the review >>> and ACK tags you have received. (Just remind, b4 is your friend for >>> helping do >>> these things). >>> >>> Thanks, >>> Leo >> >> Got it. Thanks, Leo. By the way, I noticed when I rebased to >> perf-tools-next the kernel version was 6.11-rc3. Is there any chance >> this patch gets into 6.11? > > Linus' master branch now is 6.11-rc5, it is not far away from the 6.11. > > I think we still have much chance to get it done before it. Added > maintainers > in case any missing. > > Thanks, > Leo Hi Leo, That's great. Unfortuantely, I need to submit a V6 for patch 4/4, which is the arm-cs-trace-disasm.py script. Kernel instruction trace requires zeroing map_pgoff. perf makes most offset decisions, but this one is in the script. It's a one liner. I know you're a b4 fan, but I've never used it. If I'm able to make progress with it I'll use it to resubmit. Otherwise more of the same. Steve Steve

3 months, 3 weeks

Re: [PATCH] perf scripts python arm-cs-trace-disasm.py: Skip disasm if address continuity is broken

by James Clark

On 23/08/2024 10:57 am, Ganapatrao Kulkarni wrote: > > Hi James/Mike, > > On 23-08-2024 02:33 pm, James Clark wrote: >> >> >> On 19/08/2024 11:59 am, Mike Leach wrote: >>> Hi, >>> >>> A new branch of OpenCSD is available - ocsd-consistency-checks-1.5.4-rc1 >>> >>> Testing I managed to do confirms the N atom on unconditional branches >>> appear to work. I do not have a test case for the range >>> discontinuities. >>> >>> The checks are enabled using operation flags on decoder creation. See >>> the docs for details. >>> >>> Mike >>> >> >> Hi Mike, >> >> I tested the new OpenCSD and I don't see the error anymore in the >> disassembly script. I'm not sure if we need to go any further and add >> the backwards check, it looks like just a later symptom and the checks >> that you've added already prevent it. >> >> If you release a new version I can send the perf patch. I was going to >> use these flags if that looks right to you? As far as I know that's the >> set that can be always on and won't fail on bad hardware? >> >> I also assumed that ETM4_OPFLG_PKTDEC_AA64_OPCODE_CHK can be given even >> for etmv3 and it's just a nop? >> >> diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> index e917985bbbe6..90967fd807e6 100644 >> --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c >> @@ -685,9 +685,14 @@ cs_etm_decoder__create_etm_decoder(struct >> cs_etm_decoder_params *d_params, >> return 0; >> >> if (d_params->operation == CS_ETM_OPERATION_DECODE) { >> + int decode_flags = OCSD_CREATE_FLG_FULL_DECODER; >> +#ifdef OCSD_OPFLG_N_UNCOND_DIR_BR_CHK >> + decode_flags |= OCSD_OPFLG_N_UNCOND_DIR_BR_CHK | >> OCSD_OPFLG_CHK_RANGE_CONTINUE | >> + ETM4_OPFLG_PKTDEC_AA64_OPCODE_CHK; >> +#endif >> if (ocsd_dt_create_decoder(decoder->dcd_tree, >> decoder->decoder_name, >> - OCSD_CREATE_FLG_FULL_DECODER, >> + decode_flags, >> trace_config, &csid)) >> return -1; >> > > I tried Mike's branch with above James's patch and still the segfault is > happening to us. > Looks like the Perf bug is only on the timestamped decode path, you can force timeless as a workaround. Timestamps aren't used by the disassembly script anyway: --itrace=Zb Full command: perf script -i ./kcore -s python:tools/perf/scripts/python/arm-cs-\ trace-disasm.py --itrace=Zb -- -k ./kcore/kcore_dir/kcore You can also disable timestamps when recording then you don't need the itrace option. This will save you a lot of data anyway. But I'm still working on the proper fix.

3 months, 3 weeks

Re: [PATCH V5 0/4] arm-cs-trace-disasm.py/perf must accommodate non-zero DSO text offset

by Steve Clevenger

On 8/29/2024 12:55 AM, Leo Yan wrote: > On 8/29/2024 12:17 AM, Steve Clevenger wrote: >> >> Changes in V5: >> - In symbol-elf.c, branch to exit_close label if open file. >> - In trace_event_python.c, correct indentation. set_sym_in_dict >> call parameter "map_pgoff" renamed as "addr_map_pgoff" to >> match local naming. > > For the series: > > Reviewed-by: Leo Yan <leo.yan(a)arm.com> > > Hi Steve, > > Later when you respin a new version patches, it is better to amend the review > and ACK tags you have received. (Just remind, b4 is your friend for helping do > these things). > > Thanks, > Leo Got it. Thanks, Leo. By the way, I noticed when I rebased to perf-tools-next the kernel version was 6.11-rc3. Is there any chance this patch gets into 6.11? Steve

3 months, 3 weeks

New version of OpenCSD released

by Mike Leach

OpenCSD version 1.5.4 is now released. This update contains a number of optional consistency checks that the client can enable in the library to detect incorrect memory images or corrupt trace being supplied to the decoder by the client. Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months, 3 weeks

Re: [PATCH] perf scripts python arm-cs-trace-disasm.py: Skip disasm if address continuity is broken

by James Clark

On 07/08/2024 5:48 pm, Leo Yan wrote: > Hi all, > > On 8/7/2024 3:53 PM, James Clark wrote: > > A minor suggestion: if the discussion is too long, please delete the > irrelevant message ;) > > [...] > >>> --- a/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> +++ b/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> @@ -257,6 +257,11 @@ def process_event(param_dict): >>> print("Stop address 0x%x is out of range [ 0x%x .. 0x%x >>> ] for dso %s" % (stop_addr, int(dso_start), int(dso_end), dso)) >>> return >>> >>> + if (stop_addr < start_addr): >>> + if (options.verbose == True): >>> + print("Packet Dropped, Discontinuity detected >>> [stop_add:0x%x start_addr:0x%x ] for dso %s" % (stop_addr, start_addr, >>> dso)) >>> + return >>> + >> >> I suppose my only concern with this is that it hides real errors and >> Perf shouldn't be outputting samples that go backwards. Considering that >> fixing this in OpenCSD and Perf has a much wider benefit I think that >> should be the ultimate goal. I'm putting this on my todo list for now >> (including Steve's merging idea). > > In the perf's util/cs-etm.c file, it handles DISCONTINUITY with: > > case CS_ETM_DISCONTINUITY: > /* > * The trace is discontinuous, if the previous packet is > * instruction packet, set flag PERF_IP_FLAG_TRACE_END > * for previous packet. > */ > if (prev_packet->sample_type == CS_ETM_RANGE) > prev_packet->flags |= PERF_IP_FLAG_BRANCH | > PERF_IP_FLAG_TRACE_END; > > I am wandering if OpenCSD has passed the correct info so Perf decoder can > detect the discontinuity. If yes, then the flag 'PERF_IP_FLAG_TRACE_END' will > be set (it is a general flag in branch sample), then we can consider use it in > the python script to handle discontinuous data. No OpenCSD isn't passing the correct info here. Higher up in the thread I suggested an OpenCSD patch that makes it detect the error earlier and fixes the issue. It also needs to output a discontinuity when the address goes backwards. So two fixes and then the script works without modifications. > >> >> But in the mean time what about having a force option? >> >>> + if (stop_addr < start_addr): >>> + if (options.verbose == True or not options.force): >>> + print("Packet Dropped, Discontinuity detected >>> [stop_add:0x%x start_addr:0x%x ] for dso %s" % (stop_addr, start_addr, >>> dso)) >>> + if (not options.force): >>> + return > > If the stop address is less than the start address, it must be something > wrong. In this case, we can report a warning for discontinuity and directly > return (also need to save the `addr` into global variable for next parsing). > > I prefer to not add force option for this case - eventually, this will consume > much time for reporting this kind of failure and need to root causing it. A > better way is we just print out the reasoning in the log and continue to dump. But in this case we've identified all the known issues that would cause the script to fail and we can fix them in Perf and OpenCSD. There may not even be any more issues that will cause the script to fail in the future so there's no point in softening the error IMO. That will only hide future issues (of which there may be none) and make root causing harder when it hits some other tool.

3 months, 3 weeks

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CoreSight August 2024