CoreSight February 2025

coresight@lists.linaro.org

8 participants
45 discussions

[PATCH] arm: coresight: Finish removal of Coresight support in arch/arm/kernel

by James Clark

Commit 184901a06a36 ("ARM: removing support for etb/etm in "arch/arm/kernel/"") removed asm/hardware/coresight.h which is included by this file. Therefore this is dead code so delete it. Signed-off-by: James Clark <james.clark(a)linaro.org> --- arch/arm/include/asm/cti.h | 160 ------------------------------------- 1 file changed, 160 deletions(-) delete mode 100644 arch/arm/include/asm/cti.h diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h deleted file mode 100644 index f8500e5d6ea8..000000000000 --- a/arch/arm/include/asm/cti.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASMARM_CTI_H -#define __ASMARM_CTI_H - -#include <asm/io.h> -#include <asm/hardware/coresight.h> - -/* The registers' definition is from section 3.2 of - * Embedded Cross Trigger Revision: r0p0 - */ -#define CTICONTROL 0x000 -#define CTISTATUS 0x004 -#define CTILOCK 0x008 -#define CTIPROTECTION 0x00C -#define CTIINTACK 0x010 -#define CTIAPPSET 0x014 -#define CTIAPPCLEAR 0x018 -#define CTIAPPPULSE 0x01c -#define CTIINEN 0x020 -#define CTIOUTEN 0x0A0 -#define CTITRIGINSTATUS 0x130 -#define CTITRIGOUTSTATUS 0x134 -#define CTICHINSTATUS 0x138 -#define CTICHOUTSTATUS 0x13c -#define CTIPERIPHID0 0xFE0 -#define CTIPERIPHID1 0xFE4 -#define CTIPERIPHID2 0xFE8 -#define CTIPERIPHID3 0xFEC -#define CTIPCELLID0 0xFF0 -#define CTIPCELLID1 0xFF4 -#define CTIPCELLID2 0xFF8 -#define CTIPCELLID3 0xFFC - -/* The below are from section 3.6.4 of - * CoreSight v1.0 Architecture Specification - */ -#define LOCKACCESS 0xFB0 -#define LOCKSTATUS 0xFB4 - -/** - * struct cti - cross trigger interface struct - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out_for_irq: triger out number which will cause - * the @irq happen - * - * cti struct used to operate cti registers. - */ -struct cti { - void __iomem *base; - int irq; - int trig_out_for_irq; -}; - -/** - * cti_init - initialize the cti instance - * @cti: cti instance - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out: triger out number which will cause - * the @irq happen - * - * called by machine code to pass the board dependent - * @base, @irq and @trig_out to cti. - */ -static inline void cti_init(struct cti *cti, - void __iomem *base, int irq, int trig_out) -{ - cti->base = base; - cti->irq = irq; - cti->trig_out_for_irq = trig_out; -} - -/** - * cti_map_trigger - use the @chan to map @trig_in to @trig_out - * @cti: cti instance - * @trig_in: trigger in number - * @trig_out: trigger out number - * @channel: channel number - * - * This function maps one trigger in of @trig_in to one trigger - * out of @trig_out using the channel @chan. - */ -static inline void cti_map_trigger(struct cti *cti, - int trig_in, int trig_out, int chan) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINEN + trig_in * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIINEN + trig_in * 4); - - val = __raw_readl(base + CTIOUTEN + trig_out * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIOUTEN + trig_out * 4); -} - -/** - * cti_enable - enable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_enable(struct cti *cti) -{ - __raw_writel(0x1, cti->base + CTICONTROL); -} - -/** - * cti_disable - disable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_disable(struct cti *cti) -{ - __raw_writel(0, cti->base + CTICONTROL); -} - -/** - * cti_irq_ack - clear the cti irq - * @cti: cti instance - * - * clear the cti irq - */ -static inline void cti_irq_ack(struct cti *cti) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINTACK); - val |= BIT(cti->trig_out_for_irq); - __raw_writel(val, base + CTIINTACK); -} - -/** - * cti_unlock - unlock cti module - * @cti: cti instance - * - * unlock the cti module, or else any writes to the cti - * module is not allowed. - */ -static inline void cti_unlock(struct cti *cti) -{ - __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); -} - -/** - * cti_lock - lock cti module - * @cti: cti instance - * - * lock the cti module, so any writes to the cti - * module will be not allowed. - */ -static inline void cti_lock(struct cti *cti) -{ - __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); -} -#endif -- 2.34.1

3 weeks, 6 days

Re: [PATCH 05/27] ABI: sysfs-bus-coresight-*: fix kernelversion tags

by Suzuki K Poulose

On 10/02/2025 10:17, Mauro Carvalho Chehab wrote: > Some kernelversion tags are missing colons. Add them to comply with > ABI description and produce right results when converted to html/pdf. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> > --- > .../testing/sysfs-bus-coresight-devices-cti | 78 +++++++++---------- > .../testing/sysfs-bus-coresight-devices-tpdm | 52 ++++++------- > 2 files changed, 65 insertions(+), 65 deletions(-) Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > index bf2869c413e7..a97b70f588da 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > @@ -1,241 +1,241 @@ > What: /sys/bus/coresight/devices/<cti-name>/enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable/Disable the CTI hardware. > > What: /sys/bus/coresight/devices/<cti-name>/powered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Indicate if the CTI hardware is powered. > > What: /sys/bus/coresight/devices/<cti-name>/ctmid > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Display the associated CTM ID > > What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Number of devices connected to triggers on this CTI > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Name of connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Input trigger signals from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the input trigger signals > from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Output trigger signals to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the output trigger signals > to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Select the index for inen and outen registers. > > What: /sys/bus/coresight/devices/<cti-name>/regs/inen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIINEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/outen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIOUTEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/gate > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write CTIGATE register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/asicctl > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write ASICCTL register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/intack > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write the INTACK register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Set CTIAPPSET register to activate channel. Read back to > determine current value of register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appclear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPCLEAR register to deactivate channel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/apppulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPPULSE to pulse a channel active for one clock > cycle. > > What: /sys/bus/coresight/devices/<cti-name>/regs/chinstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read current status of channel inputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/choutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of channel outputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of input trigger signals > > What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of output trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI input trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI input trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI output trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI output trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable CTIGATE for single channel (Write) or list enabled > channels through the gate (R). > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_disable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Disable CTIGATE for single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_set > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Activate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_clear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Deactivate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_pulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Pulse a single channel - activate for a single clock cycle. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_filtered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) List of output triggers filtered across all connections. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trig_filter_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable or disable trigger output signal filtering. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_inuse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with at least one attached trigger signal. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_free > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with no attached trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Write channel number to select a channel to view, read to > see selected channel number. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_in > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see input triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_out > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see output triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_reset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Clear all channel / trigger programming. > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index bf710ea6e0ef..53cb454b60d0 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -1,6 +1,6 @@ > What: /sys/bus/coresight/devices/<tpdm-name>/integration_test > Date: January 2023 > -KernelVersion 6.2 > +KernelVersion: 6.2 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Run integration test for tpdm. Integration test > @@ -14,7 +14,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Reset the dataset of the tpdm. > @@ -24,7 +24,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger type of the DSB for tpdm. > @@ -35,7 +35,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the DSB for tpdm. > @@ -46,7 +46,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the programming mode of the DSB for tpdm. > @@ -60,7 +60,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the index number of the edge detection for the DSB > @@ -69,7 +69,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to control the edge detection corresponding to > @@ -85,7 +85,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to mask the edge detection corresponding to the index > @@ -97,21 +97,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control value of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control mask of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the DSB > @@ -119,7 +119,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the DSB > @@ -127,21 +127,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of DSB tpdm. Read > @@ -153,7 +153,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern type of DSB tpdm. Read > @@ -165,7 +165,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the DSB subunit > @@ -173,7 +173,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: (Write) Set the data collection mode of CMB tpdm. Continuous > change creates CMB data set elements on every CMBCLK edge. > @@ -187,7 +187,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the CMB > @@ -195,7 +195,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the CMB > @@ -203,21 +203,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of CMB tpdm. Read > @@ -229,7 +229,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the CMB for tpdm. > @@ -240,7 +240,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Read or write the status of timestamp upon all interface. > @@ -252,7 +252,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the CMB subunit

3 weeks, 6 days

Re: [PATCH 1/3] coresight: Don't save handle in path

by James Clark

On 06/02/2025 3:02 am, Jie Gan wrote: > > > On 2/1/2025 12:36 AM, James Clark wrote: >> Signed-off-by: James Clark <james.clark(a)linaro.org> >> --- >> drivers/hwtracing/coresight/coresight-core.c | 10 +++++----- >> drivers/hwtracing/coresight/coresight-dummy.c | 2 +- >> drivers/hwtracing/coresight/coresight-etb10.c | 8 +++----- >> drivers/hwtracing/coresight/coresight-etm-perf.c | 3 +-- >> drivers/hwtracing/coresight/coresight-priv.h | 4 ++-- >> drivers/hwtracing/coresight/coresight-sysfs.c | 2 +- >> drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 ++++----- >> drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +++++-------- >> drivers/hwtracing/coresight/coresight-tmc.h | 2 +- >> drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- >> drivers/hwtracing/coresight/coresight-trbe.c | 4 +--- >> drivers/hwtracing/coresight/ultrasoc-smb.c | 8 +++----- >> include/linux/coresight.h | 2 +- >> 13 files changed, 29 insertions(+), 40 deletions(-) >> > > Hi James > > I removed the handle from coresight_path and placed these codes in a > separate patch. However, I believe this change is not related to the > CTCU driver or coresight_path. Therefore, I suggest we submit it > independently. > > Thanks, > Jie > > Yeah if you've removed the handle from the path then we can do the other void* changes separately. Makes sense. >> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/ >> hwtracing/coresight/coresight-core.c >> index 11d5d5320b1a..253ef02fde12 100644 >> --- a/drivers/hwtracing/coresight/coresight-core.c >> +++ b/drivers/hwtracing/coresight/coresight-core.c >> @@ -272,9 +272,9 @@ void coresight_add_helper(struct coresight_device >> *csdev, >> EXPORT_SYMBOL_GPL(coresight_add_helper); >> static int coresight_enable_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> - return sink_ops(csdev)->enable(csdev, mode, data); >> + return sink_ops(csdev)->enable(csdev, mode, handle); >> } >> static void coresight_disable_sink(struct coresight_device *csdev) >> @@ -448,7 +448,8 @@ static int coresight_enable_helpers(struct >> coresight_device *csdev, >> return 0; >> } >> -int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode) >> +int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode, >> + struct perf_output_handle *handle) >> { >> int ret = 0; >> u32 type; >> @@ -479,7 +480,7 @@ int coresight_enable_path(struct coresight_path >> *cs_path, enum cs_mode mode) >> switch (type) { >> case CORESIGHT_DEV_TYPE_SINK: >> - ret = coresight_enable_sink(csdev, mode, cs_path); >> + ret = coresight_enable_sink(csdev, mode, handle); >> /* >> * Sink is the first component turned on. If we >> * failed to enable the sink, there are no components >> @@ -807,7 +808,6 @@ void coresight_release_path(struct coresight_path >> *cs_path) >> kfree(nd); >> } >> - cs_path->handle = NULL; >> kfree(cs_path->path); >> kfree(cs_path); >> } >> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/ >> hwtracing/coresight/coresight-dummy.c >> index dfcf24e9c49a..6f86d33efef4 100644 >> --- a/drivers/hwtracing/coresight/coresight-dummy.c >> +++ b/drivers/hwtracing/coresight/coresight-dummy.c >> @@ -54,7 +54,7 @@ static int dummy_source_trace_id(struct >> coresight_device *csdev, enum cs_mode mo >> } >> static int dummy_sink_enable(struct coresight_device *csdev, enum >> cs_mode mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> dev_dbg(csdev->dev.parent, "Dummy sink enabled\n"); >> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/ >> hwtracing/coresight/coresight-etb10.c >> index 05430d8931d1..e373b0f590bf 100644 >> --- a/drivers/hwtracing/coresight/coresight-etb10.c >> +++ b/drivers/hwtracing/coresight/coresight-etb10.c >> @@ -167,14 +167,12 @@ static int etb_enable_sysfs(struct >> coresight_device *csdev) >> return ret; >> } >> -static int etb_enable_perf(struct coresight_device *csdev, void *data) >> +static int etb_enable_perf(struct coresight_device *csdev, struct >> perf_output_handle *handle) >> { >> int ret = 0; >> pid_t pid; >> unsigned long flags; >> struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -225,7 +223,7 @@ static int etb_enable_perf(struct coresight_device >> *csdev, void *data) >> } >> static int etb_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> int ret; >> @@ -234,7 +232,7 @@ static int etb_enable(struct coresight_device >> *csdev, enum cs_mode mode, >> ret = etb_enable_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = etb_enable_perf(csdev, data); >> + ret = etb_enable_perf(csdev, handle); >> break; >> default: >> ret = -EINVAL; >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/ >> drivers/hwtracing/coresight/coresight-etm-perf.c >> index b6765abb0a26..0fad9968c2c0 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >> @@ -501,9 +501,8 @@ static void etm_event_start(struct perf_event >> *event, int flags) >> if (WARN_ON_ONCE(!sink)) >> goto fail_end_stop; >> - cs_path->handle = handle; >> /* Nothing will happen without a path */ >> - if (coresight_enable_path(cs_path, CS_MODE_PERF)) >> + if (coresight_enable_path(cs_path, CS_MODE_PERF, handle)) >> goto fail_end_stop; >> /* Finally enable the tracer */ >> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/ >> hwtracing/coresight/coresight-priv.h >> index 8e02a222b9f8..7bd43304f461 100644 >> --- a/drivers/hwtracing/coresight/coresight-priv.h >> +++ b/drivers/hwtracing/coresight/coresight-priv.h >> @@ -112,7 +112,6 @@ struct cs_buffers { >> * @trace_id: trace_id of the whole path. >> */ >> struct coresight_path { >> - struct perf_output_handle *handle; >> struct list_head *path; >> u8 trace_id; >> }; >> @@ -142,7 +141,8 @@ static inline void CS_UNLOCK(void __iomem *addr) >> } >> void coresight_disable_path(struct coresight_path *cs_path); >> -int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode); >> +int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode, >> + struct perf_output_handle *handle); >> struct coresight_device *coresight_get_sink(struct list_head *path); >> struct coresight_device *coresight_get_sink_by_id(u32 id); >> struct coresight_device * >> diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/ >> hwtracing/coresight/coresight-sysfs.c >> index 04e76cc1bfdf..f9a6b838726c 100644 >> --- a/drivers/hwtracing/coresight/coresight-sysfs.c >> +++ b/drivers/hwtracing/coresight/coresight-sysfs.c >> @@ -209,7 +209,7 @@ int coresight_enable_sysfs(struct coresight_device >> *csdev) >> goto out; >> } >> - ret = coresight_enable_path(cs_path, CS_MODE_SYSFS); >> + ret = coresight_enable_path(cs_path, CS_MODE_SYSFS, NULL); >> if (ret) >> goto err_path; >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/ >> drivers/hwtracing/coresight/coresight-tmc-etf.c >> index e6b07f917556..fdf1c2511d67 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> @@ -244,14 +244,13 @@ static int tmc_enable_etf_sink_sysfs(struct >> coresight_device *csdev) >> return ret; >> } >> -static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, >> void *data) >> +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, >> + struct perf_output_handle *handle) >> { >> int ret = 0; >> pid_t pid; >> unsigned long flags; >> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path= (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -303,7 +302,7 @@ static int tmc_enable_etf_sink_perf(struct >> coresight_device *csdev, void *data) >> } >> static int tmc_enable_etf_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> int ret; >> @@ -312,7 +311,7 @@ static int tmc_enable_etf_sink(struct >> coresight_device *csdev, >> ret = tmc_enable_etf_sink_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = tmc_enable_etf_sink_perf(csdev, data); >> + ret = tmc_enable_etf_sink_perf(csdev, handle); >> break; >> /* We shouldn't be here */ >> default: >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/ >> drivers/hwtracing/coresight/coresight-tmc-etr.c >> index 82a872882e24..2d0bd06bab2a 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> @@ -1252,10 +1252,8 @@ static int tmc_enable_etr_sink_sysfs(struct >> coresight_device *csdev) >> } >> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct etr_perf_buffer *etr_perf; >> switch (mode) { >> @@ -1643,14 +1641,13 @@ tmc_update_etr_buffer(struct coresight_device >> *csdev, >> return size; >> } >> -static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, >> void *data) >> +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, >> + struct perf_output_handle *handle) >> { >> int rc = 0; >> pid_t pid; >> unsigned long flags; >> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -1698,13 +1695,13 @@ static int tmc_enable_etr_sink_perf(struct >> coresight_device *csdev, void *data) >> } >> static int tmc_enable_etr_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> switch (mode) { >> case CS_MODE_SYSFS: >> return tmc_enable_etr_sink_sysfs(csdev); >> case CS_MODE_PERF: >> - return tmc_enable_etr_sink_perf(csdev, data); >> + return tmc_enable_etr_sink_perf(csdev, handle); >> default: >> return -EINVAL; >> } >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/ >> hwtracing/coresight/coresight-tmc.h >> index 2671926be62a..e991afd43742 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc.h >> +++ b/drivers/hwtracing/coresight/coresight-tmc.h >> @@ -336,7 +336,7 @@ struct coresight_device >> *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); >> void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); >> void tmc_etr_remove_catu_ops(void); >> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, >> - enum cs_mode mode, void *data); >> + enum cs_mode mode, struct perf_output_handle >> *handle); >> extern const struct attribute_group coresight_etr_group; >> #endif >> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/ >> hwtracing/coresight/coresight-tpiu.c >> index 97ef36f03ec2..ccf463ac7bf5 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpiu.c >> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c >> @@ -75,7 +75,7 @@ static void tpiu_enable_hw(struct csdev_access *csa) >> } >> static int tpiu_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *__unused) >> + struct perf_output_handle *__unused) >> { >> struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/ >> hwtracing/coresight/coresight-trbe.c >> index 5005efd88a66..997d5976d2d2 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -1009,12 +1009,10 @@ static int __arm_trbe_enable(struct trbe_buf >> *buf, >> } >> static int arm_trbe_enable(struct coresight_device *csdev, enum >> cs_mode mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct trbe_buf *buf = etm_perf_sink_config(handle); >> WARN_ON(cpudata->cpu != smp_processor_id()); >> diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/ >> hwtracing/coresight/ultrasoc-smb.c >> index 9be88394b3bb..1574b5067206 100644 >> --- a/drivers/hwtracing/coresight/ultrasoc-smb.c >> +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c >> @@ -213,11 +213,9 @@ static void smb_enable_sysfs(struct >> coresight_device *csdev) >> coresight_set_mode(csdev, CS_MODE_SYSFS); >> } >> -static int smb_enable_perf(struct coresight_device *csdev, void *data) >> +static int smb_enable_perf(struct coresight_device *csdev, struct >> perf_output_handle *handle) >> { >> struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> pid_t pid; >> @@ -241,7 +239,7 @@ static int smb_enable_perf(struct coresight_device >> *csdev, void *data) >> } >> static int smb_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> int ret = 0; >> @@ -262,7 +260,7 @@ static int smb_enable(struct coresight_device >> *csdev, enum cs_mode mode, >> smb_enable_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = smb_enable_perf(csdev, data); >> + ret = smb_enable_perf(csdev, handle); >> break; >> default: >> ret = -EINVAL; >> diff --git a/include/linux/coresight.h b/include/linux/coresight.h >> index 87f9baa7fefe..a859fc00eef9 100644 >> --- a/include/linux/coresight.h >> +++ b/include/linux/coresight.h >> @@ -353,7 +353,7 @@ enum cs_mode { >> */ >> struct coresight_ops_sink { >> int (*enable)(struct coresight_device *csdev, enum cs_mode mode, >> - void *data); >> + struct perf_output_handle *handle); >> int (*disable)(struct coresight_device *csdev); >> void *(*alloc_buffer)(struct coresight_device *csdev, >> struct perf_event *event, void **pages, >

1 month

[PATCH] coresight-tmc: stop disabling tmc when flush timeout

by Yuanfang Zhang

When multiple ETMs are enabled simultaneously, the time required to complete a flush in the process of reading the TMC device node may exceed the default wait time of 100us. If the TMC capture is stopped while any ETM has not completed its flush, it can cause the corresponding CPU to hang. Fix the by checking the TMCReady bit after the flush. If TMCReady bit is set, TraceCaptEn bit can be clear; otherwise, return directly and stop the TMC read. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++----- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63ebdbed6719133 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) return; } -static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); + + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) tmc_disable_hw(drvdata); CS_LOCK(drvdata->base); + return 0; } static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) @@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) ret = -EINVAL; goto out; } - __tmc_etb_disable_hw(drvdata); + ret = __tmc_etb_disable_hw(drvdata); + if (ret) + goto out; } drvdata->reading = true; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53dce4d82842bec3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata) } } -static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); + + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) tmc_disable_hw(drvdata); CS_LOCK(drvdata->base); - + return 0; } void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) @@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) } /* Disable the TMC if we are trying to read from a running session. */ - if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) - __tmc_etr_disable_hw(drvdata); - + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) { + ret = __tmc_etr_disable_hw(drvdata); + if (ret) + goto out; + } drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); --- base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 change-id: 20250103-fix_cpu_hung-b5a95179ada4 Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 month

Re: [RFC v2 08/38] ABI: sysfs-bus-coresight-*: fix kernelversion tags

by Suzuki K Poulose

On 28/01/2025 00:05, Mauro Carvalho Chehab wrote: > Some kernelversion tags are missing colons. Add them to comply with > ABI description and produce right results when converted to html/pdf. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > .../testing/sysfs-bus-coresight-devices-cti | 78 +++++++++---------- > .../testing/sysfs-bus-coresight-devices-tpdm | 52 ++++++------- > 2 files changed, 65 insertions(+), 65 deletions(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > index bf2869c413e7..a97b70f588da 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > @@ -1,241 +1,241 @@ > What: /sys/bus/coresight/devices/<cti-name>/enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable/Disable the CTI hardware. > > What: /sys/bus/coresight/devices/<cti-name>/powered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Indicate if the CTI hardware is powered. > > What: /sys/bus/coresight/devices/<cti-name>/ctmid > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Display the associated CTM ID > > What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Number of devices connected to triggers on this CTI > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Name of connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Input trigger signals from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the input trigger signals > from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Output trigger signals to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the output trigger signals > to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Select the index for inen and outen registers. > > What: /sys/bus/coresight/devices/<cti-name>/regs/inen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIINEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/outen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIOUTEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/gate > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write CTIGATE register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/asicctl > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write ASICCTL register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/intack > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write the INTACK register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Set CTIAPPSET register to activate channel. Read back to > determine current value of register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appclear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPCLEAR register to deactivate channel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/apppulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPPULSE to pulse a channel active for one clock > cycle. > > What: /sys/bus/coresight/devices/<cti-name>/regs/chinstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read current status of channel inputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/choutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of channel outputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of input trigger signals > > What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of output trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI input trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI input trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI output trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI output trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable CTIGATE for single channel (Write) or list enabled > channels through the gate (R). > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_disable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Disable CTIGATE for single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_set > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Activate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_clear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Deactivate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_pulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Pulse a single channel - activate for a single clock cycle. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_filtered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) List of output triggers filtered across all connections. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trig_filter_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable or disable trigger output signal filtering. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_inuse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with at least one attached trigger signal. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_free > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with no attached trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Write channel number to select a channel to view, read to > see selected channel number. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_in > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see input triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_out > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see output triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_reset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Clear all channel / trigger programming. > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index bf710ea6e0ef..53cb454b60d0 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -1,6 +1,6 @@ > What: /sys/bus/coresight/devices/<tpdm-name>/integration_test > Date: January 2023 > -KernelVersion 6.2 > +KernelVersion: 6.2 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Run integration test for tpdm. Integration test > @@ -14,7 +14,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Reset the dataset of the tpdm. > @@ -24,7 +24,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger type of the DSB for tpdm. > @@ -35,7 +35,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the DSB for tpdm. > @@ -46,7 +46,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the programming mode of the DSB for tpdm. > @@ -60,7 +60,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the index number of the edge detection for the DSB > @@ -69,7 +69,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to control the edge detection corresponding to > @@ -85,7 +85,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to mask the edge detection corresponding to the index > @@ -97,21 +97,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control value of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control mask of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the DSB > @@ -119,7 +119,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the DSB > @@ -127,21 +127,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of DSB tpdm. Read > @@ -153,7 +153,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern type of DSB tpdm. Read > @@ -165,7 +165,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the DSB subunit > @@ -173,7 +173,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: (Write) Set the data collection mode of CMB tpdm. Continuous > change creates CMB data set elements on every CMBCLK edge. > @@ -187,7 +187,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the CMB > @@ -195,7 +195,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the CMB > @@ -203,21 +203,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of CMB tpdm. Read > @@ -229,7 +229,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the CMB for tpdm. > @@ -240,7 +240,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Read or write the status of timestamp upon all interface. > @@ -252,7 +252,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the CMB subunit

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