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CoreSight September 2025

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Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by Suzuki K Poulose

On Tue, 12 Aug 2025 01:24:45 -0700, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > The patch looks good to me. May be we could expose this via sysfs, like we do for the other fields. That can be a separate patch without the Fixes tag. I have applied this patch to -next, thanks! [1/1] coresight-etm4x: Conditionally access register TRCEXTINSELR https://git.kernel.org/coresight/c/fa71e9cb4cfa Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

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