CoreSight

coresight@lists.linaro.org

5 participants
2620 discussions

[PATCH] coresight: tmc: Prevent sysfs parameter changes if sink in use

by Mike Leach

The sysfs files that change the operational parameters for TMC buffer_size, stop_on_flush and trigger_cntr are writable when the TMC is in use. The new values will have no effect and be silently ignored. Alter the sysfs functions to return -EBUSY if the TMC is currently in use, and also protect the write values using the spinlock. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- .../hwtracing/coresight/coresight-tmc-core.c | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 36599c431be6..a1216a1f9681 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -489,15 +489,24 @@ static ssize_t trigger_cntr_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtoul(buf, 16, &val); if (ret) return ret; + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->trigger_cntr = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(trigger_cntr); @@ -514,7 +523,7 @@ static ssize_t buffer_size_store(struct device *dev, const char *buf, size_t size) { int ret; - unsigned long val; + unsigned long val, flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); /* Only permitted for TMC-ETRs */ @@ -527,8 +536,18 @@ static ssize_t buffer_size_store(struct device *dev, /* The buffer size should be page aligned */ if (val & (PAGE_SIZE - 1)) return -EINVAL; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } drvdata->size = val; - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(buffer_size); @@ -547,17 +566,27 @@ static ssize_t stop_on_flush_store(struct device *dev, { int ret; u8 val; + unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = kstrtou8(buf, 0, &val); if (ret) return ret; + + /* do not permit write if the sink is currently in use */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED) { + ret = -EBUSY; + goto out; + } if (val) drvdata->stop_on_flush = true; else drvdata->stop_on_flush = false; - - return size; + ret = size; +out: + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; } static DEVICE_ATTR_RW(stop_on_flush); -- 2.32.0

2 months, 3 weeks

Re: [subset] [PATCH v4 0/3] coresight: add static TPDM support

by Suzuki K Poulose

On Tue, 28 Oct 2025 18:11:39 +0800, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > [...] Applied, thanks! [1/3] dt-bindings: arm: document the static TPDM compatible https://git.kernel.org/coresight/c/8d204b6f1f7a [2/3] coresight: tpdm: add static tpdm support https://git.kernel.org/coresight/c/14ae052f7947 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 months, 3 weeks

Re: [PATCH v4 3/3] arm64: dts: qcom: lemans: enable static TPDM

by Suzuki K Poulose

On 28/10/2025 10:11, Jie Gan wrote: > Enable static TPDM device for lemans. > > Reviewed-by: Konrad Dybcio <konrad.dybcio(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> Assuming this goes via some other tree: Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > arch/arm64/boot/dts/qcom/lemans.dtsi | 105 +++++++++++++++++++++++++++++++++++ > 1 file changed, 105 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > index 0b154d57ba24..8a93b353d11c 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -2961,6 +2961,14 @@ funnel1_in4: endpoint { > <&apss_funnel1_out>; > }; > }; > + > + port@5 { > + reg = <5>; > + > + funnel1_in5: endpoint { > + remote-endpoint = <&dlct0_funnel_out>; > + }; > + }; > }; > }; > > @@ -3118,6 +3126,60 @@ etr1_out: endpoint { > }; > }; > > + tpda@4ad3000 { > + compatible = "qcom,coresight-tpda", "arm,primecell"; > + reg = <0x0 0x4ad3000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@10 { > + reg = <16>; > + dlct0_tpda_in16: endpoint { > + remote-endpoint = <&turing0_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + dlct0_tpda_out: endpoint { > + remote-endpoint = > + <&dlct0_funnel_in0>; > + }; > + }; > + }; > + > + }; > + > + funnel@4ad4000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0x0 0x4ad4000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + dlct0_funnel_in0: endpoint { > + remote-endpoint = <&dlct0_tpda_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + dlct0_funnel_out: endpoint { > + remote-endpoint = <&funnel1_in5>; > + }; > + }; > + }; > + }; > + > funnel@4b04000 { > compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > reg = <0x0 0x4b04000 0x0 0x1000>; > @@ -3390,6 +3452,35 @@ aoss_cti: cti@4b13000 { > clock-names = "apb_pclk"; > }; > > + funnel@4b83000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0x0 0x4b83000 0x0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + turing0_funnel_in1: endpoint { > + remote-endpoint = <&turing_llm_tpdm_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + turing0_funnel_out: endpoint { > + remote-endpoint = <&dlct0_tpda_in16>; > + }; > + }; > + }; > + }; > + > etm@6040000 { > compatible = "arm,primecell"; > reg = <0x0 0x6040000 0x0 0x1000>; > @@ -8269,6 +8360,20 @@ arch_timer: timer { > <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > }; > > + turing-llm-tpdm { > + compatible = "qcom,coresight-static-tpdm"; > + > + qcom,cmb-element-bits = <32>; > + > + out-ports { > + port { > + turing_llm_tpdm_out: endpoint { > + remote-endpoint = <&turing0_funnel_in1>; > + }; > + }; > + }; > + }; > + > pcie0: pcie@1c00000 { > compatible = "qcom,pcie-sa8775p"; > reg = <0x0 0x01c00000 0x0 0x3000>, >

2 months, 3 weeks

Re: [PATCH v4 2/3] coresight: tpdm: add static tpdm support

by Suzuki K Poulose

On 28/10/2025 10:11, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 7 -- > drivers/hwtracing/coresight/coresight-tpdm.c | 174 ++++++++++++++++++++++----- > drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++ > 3 files changed, 154 insertions(+), 39 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 333b3cb23685..3a3825d27f86 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -22,13 +22,6 @@ > > DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); > > -static bool coresight_device_is_tpdm(struct coresight_device *csdev) > -{ > - return (coresight_is_device_source(csdev)) && > - (csdev->subtype.source_subtype == > - CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); > -} > - > static void tpda_clear_element_size(struct coresight_device *csdev) > { > struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 7214e65097ec..0e3896c12f07 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -470,6 +470,9 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) > */ > static void __tpdm_enable(struct tpdm_drvdata *drvdata) > { > + if (coresight_is_static_tpdm(drvdata->csdev)) > + return; > + > CS_UNLOCK(drvdata->base); > > tpdm_enable_dsb(drvdata); > @@ -532,6 +535,9 @@ static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) > /* TPDM disable operations */ > static void __tpdm_disable(struct tpdm_drvdata *drvdata) > { > + if (coresight_is_static_tpdm(drvdata->csdev)) > + return; > + > CS_UNLOCK(drvdata->base); > > tpdm_disable_dsb(drvdata); > @@ -595,6 +601,30 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) > return 0; > } > > +static int static_tpdm_datasets_setup(struct tpdm_drvdata *drvdata, struct device *dev) > +{ > + /* setup datasets for static TPDM */ > + if (fwnode_property_present(dev->fwnode, "qcom,dsb-element-bits") && > + (!drvdata->dsb)) { > + drvdata->dsb = devm_kzalloc(drvdata->dev, > + sizeof(*drvdata->dsb), GFP_KERNEL); > + > + if (!drvdata->dsb) > + return -ENOMEM; > + } > + > + if (fwnode_property_present(dev->fwnode, "qcom,cmb-element-bits") && > + (!drvdata->cmb)) { > + drvdata->cmb = devm_kzalloc(drvdata->dev, > + sizeof(*drvdata->cmb), GFP_KERNEL); > + > + if (!drvdata->cmb) > + return -ENOMEM; > + } > + > + return 0; > +} > + > static ssize_t reset_dataset_store(struct device *dev, > struct device_attribute *attr, > const char *buf, > @@ -1342,10 +1372,9 @@ static const struct attribute_group *tpdm_attr_grps[] = { > NULL, > }; > > -static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > +static int tpdm_probe(struct device *dev, struct resource *res) > { > void __iomem *base; > - struct device *dev = &adev->dev; > struct coresight_platform_data *pdata; > struct tpdm_drvdata *drvdata; > struct coresight_desc desc = { 0 }; > @@ -1354,32 +1383,37 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > pdata = coresight_get_platform_data(dev); > if (IS_ERR(pdata)) > return PTR_ERR(pdata); > - adev->dev.platform_data = pdata; > + dev->platform_data = pdata; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > return -ENOMEM; > - drvdata->dev = &adev->dev; > + drvdata->dev = dev; > dev_set_drvdata(dev, drvdata); > > - base = devm_ioremap_resource(dev, &adev->res); > - if (IS_ERR(base)) > - return PTR_ERR(base); > + if (res) { > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > > - drvdata->base = base; > + drvdata->base = base; > + ret = tpdm_datasets_setup(drvdata); > + if (ret) > + return ret; > > - ret = tpdm_datasets_setup(drvdata); > - if (ret) > - return ret; > - > - if (drvdata && tpdm_has_dsb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > + if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > > - if (drvdata && tpdm_has_cmb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > + if (drvdata && tpdm_has_cmb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); minor nit: drvdata is guranteed to be !NULL, as we err out if it was. This can be fixed up as separate patch. Suzuki > + } else { > + ret = static_tpdm_datasets_setup(drvdata, dev); > + if (ret) > + return ret; > + } > > /* Set up coresight component description */ > desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > @@ -1388,34 +1422,51 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > desc.type = CORESIGHT_DEV_TYPE_SOURCE; > desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; > desc.ops = &tpdm_cs_ops; > - desc.pdata = adev->dev.platform_data; > - desc.dev = &adev->dev; > + desc.pdata = dev->platform_data; > + desc.dev = dev; > desc.access = CSDEV_ACCESS_IOMEM(base); > - desc.groups = tpdm_attr_grps; > + if (res) > + desc.groups = tpdm_attr_grps; > drvdata->csdev = coresight_register(&desc); > if (IS_ERR(drvdata->csdev)) > return PTR_ERR(drvdata->csdev); > > spin_lock_init(&drvdata->spinlock); > > - /* Decrease pm refcount when probe is done.*/ > - pm_runtime_put(&adev->dev); > - > return 0; > } > > -static void tpdm_remove(struct amba_device *adev) > +static int tpdm_remove(struct device *dev) > { > - struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev); > > coresight_unregister(drvdata->csdev); > + > + return 0; > +} > + > +static int dynamic_tpdm_probe(struct amba_device *adev, > + const struct amba_id *id) > +{ > + int ret; > + > + ret = tpdm_probe(&adev->dev, &adev->res); > + if (!ret) > + pm_runtime_put(&adev->dev); > + > + return ret; > +} > + > +static void dynamic_tpdm_remove(struct amba_device *adev) > +{ > + tpdm_remove(&adev->dev); > } > > /* > * Different TPDM has different periph id. > * The difference is 0-7 bits' value. So ignore 0-7 bits. > */ > -static const struct amba_id tpdm_ids[] = { > +static const struct amba_id dynamic_tpdm_ids[] = { > { > .id = 0x001f0e00, > .mask = 0x00ffff00, > @@ -1423,17 +1474,76 @@ static const struct amba_id tpdm_ids[] = { > { 0, 0, NULL }, > }; > > -static struct amba_driver tpdm_driver = { > +MODULE_DEVICE_TABLE(amba, dynamic_tpdm_ids); > + > +static struct amba_driver dynamic_tpdm_driver = { > .drv = { > .name = "coresight-tpdm", > .suppress_bind_attrs = true, > }, > - .probe = tpdm_probe, > - .id_table = tpdm_ids, > - .remove = tpdm_remove, > + .probe = dynamic_tpdm_probe, > + .id_table = dynamic_tpdm_ids, > + .remove = dynamic_tpdm_remove, > }; > > -module_amba_driver(tpdm_driver); > +static int tpdm_platform_probe(struct platform_device *pdev) > +{ > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + int ret; > + > + pm_runtime_get_noresume(&pdev->dev); > + pm_runtime_set_active(&pdev->dev); > + pm_runtime_enable(&pdev->dev); > + > + ret = tpdm_probe(&pdev->dev, res); > + pm_runtime_put(&pdev->dev); > + if (ret) > + pm_runtime_disable(&pdev->dev); > + > + return ret; > +} > + > +static void tpdm_platform_remove(struct platform_device *pdev) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&pdev->dev); > + > + if (WARN_ON(!drvdata)) > + return; > + > + tpdm_remove(&pdev->dev); > + pm_runtime_disable(&pdev->dev); > +} > + > +static const struct of_device_id static_tpdm_match[] = { > + {.compatible = "qcom,coresight-static-tpdm"}, > + {} > +}; > + > +MODULE_DEVICE_TABLE(of, static_tpdm_match); > + > +static struct platform_driver static_tpdm_driver = { > + .probe = tpdm_platform_probe, > + .remove = tpdm_platform_remove, > + .driver = { > + .name = "coresight-static-tpdm", > + .of_match_table = static_tpdm_match, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init tpdm_init(void) > +{ > + return coresight_init_driver("tpdm", &dynamic_tpdm_driver, &static_tpdm_driver, > + THIS_MODULE); > +} > + > +static void __exit tpdm_exit(void) > +{ > + coresight_remove_driver(&dynamic_tpdm_driver, &static_tpdm_driver); > +} > + > +module_init(tpdm_init); > +module_exit(tpdm_exit); > > MODULE_LICENSE("GPL"); > MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index b11754389734..2867f3ab8186 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -343,4 +343,16 @@ struct tpdm_dataset_attribute { > enum dataset_mem mem; > u32 idx; > }; > + > +static inline bool coresight_device_is_tpdm(struct coresight_device *csdev) > +{ > + return (coresight_is_device_source(csdev)) && > + (csdev->subtype.source_subtype == > + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM); > +} > + > +static inline bool coresight_is_static_tpdm(struct coresight_device *csdev) > +{ > + return (coresight_device_is_tpdm(csdev) && !csdev->access.base); > +} > #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ >

2 months, 3 weeks

Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

by Mike Leach

Hi, On Mon, 3 Nov 2025 at 08:46, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > >Hi, > > > >This set is looking good now and appears to be getting close to being ready. > > > >There are a few minor issues in the second patch and a few items that > >need to be confirmed. > >1) I note that you removed the code to prevent calling claim/disclaim. > >Does this mean that you confirm that you have tested the patch update > >for claim tags I posted works on your system? > > I just tested this patch, the default value of qcom_cti's CLAIMSET register is 0xf, > and unlike the standard CTI (write 0 is no effect), it can be written with 0. > So, is it acceptable to write 0 to the claimset register of qcom_cti after reading the > devarch register during the probe phase? > > devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > drvdata->subtype = QCOM_CTI; > drvdata->offsets = cti_extended_offset; > writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); > } else { > drvdata->subtype = ARM_STD_CTI; > drvdata->offsets = cti_normal_offset; > } > OK - if you look at v2 of the cliam tag set you will see we introduce a "claim_tag_info" attribute to the coresight_device structure. This is initially set to CS_CLAIM_TAG_UNKNOWN, and on the first claim/disclaim API call the claim tags validity will be tested and a value of CS_CLAIM_TAG_STD_PROTOCOL or CS_CLAIM_TAG_NOT_IMPL set, skipping the test on all subsequent claim calls. if you set this in the probe function i.e. csdev->claim_tag_info = CS_CLAIM_TAG_NOT_IMPL, then the claim tags will not be used. whichever method you use, please ensure a comment appears in the code describing why the workaround is necessary. Regards Mike > >2) In patch 2 I made some comments in regard to ARCH values - please > >confirm that these are accurate and have been tested as working on > >your system > > Yes, the bits 31:20 in qcom_cti's DEVARCH register are 0x8EF. > > >3) As mentioned in the comments to patch 2 - you need to update the > >docs for the new sysfs selection file you have added > > Will update in v6. > > Thanks > Yingchao > > > > >Thanks and Regards > > > >Mike > > > >On Mon, 20 Oct 2025 at 08:12, Yingchao Deng > ><yingchao.deng(a)oss.qualcomm.com> wrote: > >> > >> The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > >> It allows a debugger to send to trigger events to a processor or to send > >> a trigger event to one or more processors when a trigger event occurs on > >> another processor on the same SoC, or even between SoCs. > >> > >> QCOM extended CTI supports up to 128 triggers. And some of the register > >> offsets are changed. > >> > >> The commands to configure CTI triggers are the same as ARM's CTI. > >> > >> Changes in v5: > >> 1. Move common part in qcom-cti.h to coresight-cti.h. > >> 2. Convert trigger usage fields to dynamic bitmaps and arrays. > >> 3. Fix holes in struct cti_config to save some space. > >> 4. Revert the previous changes related to the claim tag in > >> cti_enable/disable_hw. > >> Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b4… > >> > >> Changes in v4: > >> 1. Read the DEVARCH registers to identify Qualcomm CTI. > >> 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and > >> coresight_cti_reg_store() functions accordingly. > >> 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. > >> Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao… > >> > >> Changes in v3: > >> 1. Rename is_extended_cti() to of_is_extended_cti(). > >> 2. Add the missing 'i' when write the CTI trigger registers. > >> 3. Convert the multi-line output in sysfs to single line. > >> 4. Initialize offset arrays using designated initializer. > >> Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… > >> > >> Changes in V2: > >> 1. Add enum for compatible items. > >> 2. Move offset arrays to coresight-cti-core > >> > >> Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > >> Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > >> --- > >> Yingchao Deng (2): > >> coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays > >> coresight: cti: Add Qualcomm extended CTI support > >> > >> drivers/hwtracing/coresight/coresight-cti-core.c | 144 +++++++++++++--- > >> .../hwtracing/coresight/coresight-cti-platform.c | 16 +- > >> drivers/hwtracing/coresight/coresight-cti-sysfs.c | 184 +++++++++++++++------ > >> drivers/hwtracing/coresight/coresight-cti.h | 60 ++++++- > >> drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > >> 5 files changed, 346 insertions(+), 87 deletions(-) > >> --- > >> base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229 > >> change-id: 20251016-extended_cti-2a426c8894b1 > >> > >> Best regards, > >> -- > >> Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > >> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 months, 3 weeks

Re: [PATCH v3] coresight: ETR: Fix ETR buffer use-after-free issue

by Leo Yan

On Tue, Oct 21, 2025 at 04:45:25PM +0800, Xiaoqi Zhuang wrote: > When ETR is enabled as CS_MODE_SYSFS, if the buffer size is changed > and enabled again, currently sysfs_buf will point to the newly > allocated memory(buf_new) and free the old memory(buf_old). But the > etr_buf that is being used by the ETR remains pointed to buf_old, not > updated to buf_new. In this case, it will result in a memory > use-after-free issue. > > Fix this by checking ETR's mode before updating and releasing buf_old, > if the mode is CS_MODE_SYSFS, then skip updating and releasing it. > > Fixes: bd2767ec3df2 ("coresight: Fix run time warnings while reusing ETR buffer") > Signed-off-by: Xiaoqi Zhuang <xiaoqi.zhuang(a)oss.qualcomm.com> Tested on my Juno board with below steps: 1) Enable the first path: ETM2 -> ETR0 echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink echo 1 > /sys/bus/coresight/devices/etm2/enable_source 2) Enlarge buffer size from 1MiB to 4MiB cat /sys/bus/coresight/devices/tmc_etr0/buffer_size 0x100000 echo 0x400000 > /sys/bus/coresight/devices/tmc_etr0/buffer_size 3) Enable the second path: ETM0 -> ETR0 echo 1 > /sys/bus/coresight/devices/etm0/enable_source 4) Disable paths echo 0 > /sys/bus/coresight/devices/etm0/enable_source echo 0 > /sys/bus/coresight/devices/etm2/enable_source Without this patch, the oops will be triggered when disable paths. I can confirm this patch does dismiss the issue. Tested-by: Leo Yan <leo.yan(a)arm.com> > --- > Changes in v3: > - Add a fix tag for the fix patch. > - Link to v2: https://lore.kernel.org/r/20251021-fix_etr_issue-v2-1-80c40c9cac8c@oss.qual… > > Changes in v2: > - Exit earlier to avoid allocating memory unnecessarily. > - Link to v1: https://lore.kernel.org/r/20251020-fix_etr_issue-v1-1-902ab51770b4@oss.qual… > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index b07fcdb3fe1a..800be06598c1 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1250,6 +1250,13 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) > * with the lock released. > */ > raw_spin_lock_irqsave(&drvdata->spinlock, flags); > + > + /* > + * If the ETR is already enabled, continue with the existing buffer. > + */ > + if (coresight_get_mode(csdev) == CS_MODE_SYSFS) > + goto out; > + > sysfs_buf = READ_ONCE(drvdata->sysfs_buf); > if (!sysfs_buf || (sysfs_buf->size != drvdata->size)) { > raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); > > --- > base-commit: 98ac9cc4b4452ed7e714eddc8c90ac4ae5da1a09 > change-id: 20251020-fix_etr_issue-02c706dbc899 > > Best regards, > -- > Xiaoqi Zhuang <xiaoqi.zhuang(a)oss.qualcomm.com> > >

2 months, 3 weeks

[PATCH v4 00/11] CoreSight: Refactor power management for ETMv3/4

by Leo Yan

This series is extracted from the CoreSight power management fixes and refactoring [1], focusing on ETMv3/4 power management. The remaining parts will be sent out separately. Hopefully, this makes things easier for us to review and merge. Compared to the previous version, only one new patch has been added — to retain the sequencer state for ETMv4. No other changes are included. This series has been verified on Juno-r2 platform. [1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag… --- Changes in v4: - Added patch 10 for retaining sequencer state in ETMv4 driver (Mike). - Added Mike's review tags. - Added James' test tags. - Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-… Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (11): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Ensure context synchronization is not ignored coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Retain sequencer state coresight: etm4x: Reuse normal enable and disable logic in CPU idle drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 372 +++++++-------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---- include/linux/coresight.h | 25 +- 4 files changed, 175 insertions(+), 343 deletions(-) --- base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 months, 4 weeks

Re: [PATCH v5 0/2] Add Qualcomm extended CTI support

by Mike Leach

Hi, This set is looking good now and appears to be getting close to being ready. There are a few minor issues in the second patch and a few items that need to be confirmed. 1) I note that you removed the code to prevent calling claim/disclaim. Does this mean that you confirm that you have tested the patch update for claim tags I posted works on your system? 2) In patch 2 I made some comments in regard to ARCH values - please confirm that these are accurate and have been tested as working on your system 3) As mentioned in the comments to patch 2 - you need to update the docs for the new sysfs selection file you have added Thanks and Regards Mike On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs on > another processor on the same SoC, or even between SoCs. > > QCOM extended CTI supports up to 128 triggers. And some of the register > offsets are changed. > > The commands to configure CTI triggers are the same as ARM's CTI. > > Changes in v5: > 1. Move common part in qcom-cti.h to coresight-cti.h. > 2. Convert trigger usage fields to dynamic bitmaps and arrays. > 3. Fix holes in struct cti_config to save some space. > 4. Revert the previous changes related to the claim tag in > cti_enable/disable_hw. > Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b4… > > Changes in v4: > 1. Read the DEVARCH registers to identify Qualcomm CTI. > 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and > coresight_cti_reg_store() functions accordingly. > 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. > Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao… > > Changes in v3: > 1. Rename is_extended_cti() to of_is_extended_cti(). > 2. Add the missing 'i' when write the CTI trigger registers. > 3. Convert the multi-line output in sysfs to single line. > 4. Initialize offset arrays using designated initializer. > Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.c… > > Changes in V2: > 1. Add enum for compatible items. > 2. Move offset arrays to coresight-cti-core > > Signed-off-by: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > Yingchao Deng (2): > coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays > coresight: cti: Add Qualcomm extended CTI support > > drivers/hwtracing/coresight/coresight-cti-core.c | 144 +++++++++++++--- > .../hwtracing/coresight/coresight-cti-platform.c | 16 +- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 184 +++++++++++++++------ > drivers/hwtracing/coresight/coresight-cti.h | 60 ++++++- > drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > 5 files changed, 346 insertions(+), 87 deletions(-) > --- > base-commit: 1fdbb3ff1233e204e26f9f6821ae9c125a055229 > change-id: 20251016-extended_cti-2a426c8894b1 > > Best regards, > -- > Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

[PATCH 00/12] coresight: Add CPU cluster funnel/replicator/tmc support

by Yuanfang Zhang

This patch series introduces support for CPU cluster local CoreSight components, including funnel, replicator, and TMC, which reside inside CPU cluster power domains. These components require special handling due to power domain constraints. Unlike system-level CoreSight devices, CPU cluster local components share the power domain of the CPU cluster. When the cluster enters low-power mode (LPM), the registers of these components become inaccessible. Importantly, `pm_runtime_get` calls alone are insufficient to bring the CPU cluster out of LPM, making standard register access unreliable in such cases. To address this, the series introduces: - Device tree bindings for CPU cluster local funnel, replicator, and TMC. - Introduce a cpumask to record the CPUs belonging to the cluster where the cpu cluster local component resides. - Safe register access via smp_call_function_single() on CPUs within the associated cpumask, ensuring the cluster is power-resident during access. - Delayed probe support for CPU cluster local components when all CPUs of this CPU cluster are offline, re-probe the component when any CPU in the cluster comes online. - Introduce `cs_mode` to link enable interfaces to avoid the use smp_call_function_single() under perf mode. Patch summary: Patch 1: Adds device tree bindings for CPU cluster funnel/replicator/TMC devices. Patches 2–3: Add support for CPU cluster funnel. Patches 4-6: Add support for CPU cluster replicator. Patches 7-10: Add support for CPU cluster TMC. Patch 11: Add 'cs_mode' to link enable functions. Patches 12-13: Add Coresight nodes for APSS debug block for x1e80100 and fix build issue. Verification: This series has been verified on sm8750. Test steps for delay probe: 1. limit the system to enable at most 6 CPU cores during boot. 2. echo 1 >/sys/bus/cpu/devices/cpu6/online. 3. check whether ETM6 and ETM7 have been probed. Test steps for sysfs mode: echo 1 >/sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 >/sys/bus/coresight/devices/etm0/enable_source echo 1 >/sys/bus/coresight/devices/etm6/enable_source echo 0 >/sys/bus/coresight/devices/etm0/enable_source echo 0 >/sys/bus/coresight/devicse/etm6/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 >/sys/bus/coresight/devices/tmc_etf1/enable_sink echo 1 >/sys/bus/coresight/devcies/etm0/enable_source cat /dev/tmc_etf1 >/tmp/etf1.bin echo 0 >/sys/bus/coresight/devices/etm0/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf1/enable_sink echo 1 >/sys/bus/coresight/devices/tmc_etf2/enable_sink echo 1 >/sys/bus/coresight/devices/etm6/enable_source cat /dev/tmc_etf2 >/tmp/etf2.bin echo 0 >/sys/bus/coresight/devices/etm6/enable_source echo 0 >/sys/bus/coresight/devices/tmc_etf2/enable_sink Test steps for sysfs node: cat /sys/bus/coresight/devices/tmc_etf*/mgmt/* cat /sys/bus/coresight/devices/funnel*/funnel_ctrl cat /sys/bus/coresight/devices/replicator*/mgmt/* Test steps for perf mode: perf record -a -e cs_etm//k -- sleep 5 Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Yuanfang Zhang (12): dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support coresight-funnel: Add support for CPU cluster funnel coresight-funnel: Handle delay probe for CPU cluster funnel coresight-replicator: Add support for CPU cluster replicator coresight-replicator: Handle delayed probe for CPU cluster replicator coresight-replicator: Update mgmt_attrs for CPU cluster replicator compatibility coresight-tmc: Add support for CPU cluster ETF and refactor probe flow coresight-tmc-etf: Refactor enable function for CPU cluster ETF support coresight-tmc: Update tmc_mgmt_attrs for CPU cluster TMC compatibility coresight-tmc: Handle delayed probe for CPU cluster TMC coresight: add 'cs_mode' to link enable functions arm64: dts: qcom: x1e80100: add Coresight nodes for APSS debug block .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +- .../arm/arm,coresight-dynamic-replicator.yaml | 22 +- .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 885 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1p42100.dtsi | 12 + drivers/hwtracing/coresight/coresight-core.c | 7 +- drivers/hwtracing/coresight/coresight-funnel.c | 260 +++++- drivers/hwtracing/coresight/coresight-replicator.c | 343 +++++++- drivers/hwtracing/coresight/coresight-tmc-core.c | 396 +++++++-- drivers/hwtracing/coresight/coresight-tmc-etf.c | 105 ++- drivers/hwtracing/coresight/coresight-tmc.h | 10 + drivers/hwtracing/coresight/coresight-tnoc.c | 3 +- drivers/hwtracing/coresight/coresight-tpda.c | 3 +- include/linux/coresight.h | 3 +- 14 files changed, 1912 insertions(+), 182 deletions(-) --- base-commit: 01f96b812526a2c8dcd5c0e510dda37e09ec8bcd change-id: 20251016-cpu_cluster_component_pm-ce518f510433 Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

3 months

Re: [PATCH v5 2/2] coresight: cti: Add Qualcomm extended CTI support

by Mike Leach

Hi, On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. Qualcomm CTI > implementation differs from the standard CTI in the following aspects: > > 1. The number of supported triggers is extended to 128. > 2. Several register offsets differ from the CoreSight specification. > > Signed-off-by: Jinlong Mao <jinglong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 86 +++++++++-- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 174 +++++++++++++++++----- > drivers/hwtracing/coresight/coresight-cti.h | 43 +++++- > drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > 4 files changed, 281 insertions(+), 51 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8c9cec832898..5330db7eecf1 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -21,6 +21,55 @@ > > #include "coresight-priv.h" > #include "coresight-cti.h" > +#include "qcom-cti.h" > + > +static const u32 cti_normal_offset[] = { > + [INDEX_CTIINTACK] = CTIINTACK, > + [INDEX_CTIAPPSET] = CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = CTIAPPPULSE, > + [INDEX_CTIINEN] = CTIINEN(0), > + [INDEX_CTIOUTEN] = CTIOUTEN(0), > + [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, > + [INDEX_CTIGATE] = CTIGATE, > + [INDEX_ASICCTL] = ASICCTL, > + [INDEX_ITCHINACK] = ITCHINACK, > + [INDEX_ITTRIGINACK] = ITTRIGINACK, > + [INDEX_ITCHOUT] = ITCHOUT, > + [INDEX_ITTRIGOUT] = ITTRIGOUT, > + [INDEX_ITCHOUTACK] = ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, > + [INDEX_ITCHIN] = ITCHIN, > + [INDEX_ITTRIGIN] = ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > + > +static const u32 cti_extended_offset[] = { > + [INDEX_CTIINTACK] = QCOM_CTIINTACK, > + [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, > + [INDEX_CTIINEN] = QCOM_CTIINEN, > + [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, > + [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, > + [INDEX_CTIGATE] = QCOM_CTIGATE, > + [INDEX_ASICCTL] = QCOM_ASICCTL, > + [INDEX_ITCHINACK] = QCOM_ITCHINACK, > + [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, > + [INDEX_ITCHOUT] = QCOM_ITCHOUT, > + [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, > + [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, > + [INDEX_ITCHIN] = QCOM_ITCHIN, > + [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > > /* > * CTI devices can be associated with a PE, or be connected to CoreSight > @@ -70,15 +119,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) > > /* write the CTI trigger registers */ > for (i = 0; i < config->nr_trig_max; i++) { > - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); > + writel_relaxed(config->ctiinen[i], > + drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); > writel_relaxed(config->ctiouten[i], > - drvdata->base + CTIOUTEN(i)); > + drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); > } > > /* other regs */ > - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); > - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); > - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); > + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); > + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); > + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); > > /* re-enable CTI */ > writel_relaxed(1, drvdata->base + CTICONTROL); > @@ -214,6 +264,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -394,8 +447,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > > /* update the local register values */ > chan_bitmask = BIT(channel_idx); > - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : > - CTIOUTEN(trigger_idx)); > + reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : > + cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); > > raw_spin_lock(&drvdata->spinlock); > > @@ -479,19 +532,19 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, > case CTI_CHAN_SET: > config->ctiappset |= chan_bitmask; > reg_value = config->ctiappset; > - reg_offset = CTIAPPSET; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPSET, 0); > break; > > case CTI_CHAN_CLR: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPCLEAR; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPCLEAR, 0); > break; > > case CTI_CHAN_PULSE: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPPULSE; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPPULSE, 0); > break; > > default: > @@ -894,6 +947,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -980,9 +1034,19 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > drvdata->csdev_release = drvdata->csdev->dev.release; > drvdata->csdev->dev.release = cti_device_release; > > + /* qcom_cti*/ perhaps this comment could be "check architect value"? > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > + drvdata->subtype = QCOM_CTI; > + drvdata->offsets = cti_extended_offset; > + } else { > + drvdata->subtype = ARM_STD_CTI; > + drvdata->offsets = cti_normal_offset; > + } > + > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, "CTI initialized %d\n", drvdata->subtype); Here extend string to "CTI Intialized; subtype=%d\n" > return 0; > > pm_release: > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index a9df77215141..88fd1c9c0101 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -172,9 +172,8 @@ static struct attribute *coresight_cti_attrs[] = { > > /* register based attributes */ > > -/* Read registers with power check only (no enable check). */ > -static ssize_t coresight_cti_reg_show(struct device *dev, > - struct device_attribute *attr, char *buf) > +static ssize_t coresight_cti_mgmt_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > @@ -189,6 +188,39 @@ static ssize_t coresight_cti_reg_show(struct device *dev, > return sysfs_emit(buf, "0x%x\n", val); > } > > +/* Read registers with power check only (no enable check). */ > +static ssize_t coresight_cti_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > + u32 val = 0, idx = drvdata->config.regs_idx; This needs to be inside the spin lock > + > + pm_runtime_get_sync(dev->parent); > + raw_spin_lock(&drvdata->spinlock); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_CTITRIGINSTATUS: > + case INDEX_CTITRIGOUTSTATUS: > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + case INDEX_ITTRIGOUTACK: > + case INDEX_ITTRIGIN: > + val = readl_relaxed(drvdata->base + > + cti_offset(drvdata, cti_attr->off, idx)); > + break; > + > + default: > + val = readl_relaxed(drvdata->base + cti_offset(drvdata, cti_attr->off, 0)); > + break; > + } > + } > + > + raw_spin_unlock(&drvdata->spinlock); > + pm_runtime_put_sync(dev->parent); > + return sysfs_emit(buf, "0x%x\n", val); > +} > + > /* Write registers with power check only (no enable check). */ > static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct device_attribute *attr, > @@ -197,19 +229,38 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > unsigned long val = 0; > + u32 idx = drvdata->config.regs_idx; > this needs to be inside the spinlock > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > > pm_runtime_get_sync(dev->parent); > raw_spin_lock(&drvdata->spinlock); > - if (drvdata->config.hw_powered) > - cti_write_single_reg(drvdata, cti_attr->off, val); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, idx), val); > + break; > + > + default: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, 0), val); > + break; > + } > + } > raw_spin_unlock(&drvdata->spinlock); > pm_runtime_put_sync(dev->parent); > return size; > } > > +#define coresight_cti_mgmt_reg(name, offset) \ > + (&((struct cs_off_attribute[]) { \ > + { \ > + __ATTR(name, 0444, coresight_cti_mgmt_reg_show, NULL), \ > + offset \ > + } \ > + })[0].attr.attr) > + > #define coresight_cti_reg(name, offset) \ > (&((struct cs_off_attribute[]) { \ > { \ > @@ -237,17 +288,17 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > > /* coresight management registers */ > static struct attribute *coresight_cti_mgmt_attrs[] = { > - coresight_cti_reg(devaff0, CTIDEVAFF0), > - coresight_cti_reg(devaff1, CTIDEVAFF1), > - coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS), > - coresight_cti_reg(devarch, CORESIGHT_DEVARCH), > - coresight_cti_reg(devid, CORESIGHT_DEVID), > - coresight_cti_reg(devtype, CORESIGHT_DEVTYPE), > - coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0), > - coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1), > - coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2), > - coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3), > - coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4), > + coresight_cti_mgmt_reg(devaff0, CTIDEVAFF0), > + coresight_cti_mgmt_reg(devaff1, CTIDEVAFF1), > + coresight_cti_mgmt_reg(authstatus, CORESIGHT_AUTHSTATUS), > + coresight_cti_mgmt_reg(devarch, CORESIGHT_DEVARCH), > + coresight_cti_mgmt_reg(devid, CORESIGHT_DEVID), > + coresight_cti_mgmt_reg(devtype, CORESIGHT_DEVTYPE), > + coresight_cti_mgmt_reg(pidr0, CORESIGHT_PERIPHIDR0), > + coresight_cti_mgmt_reg(pidr1, CORESIGHT_PERIPHIDR1), > + coresight_cti_mgmt_reg(pidr2, CORESIGHT_PERIPHIDR2), > + coresight_cti_mgmt_reg(pidr3, CORESIGHT_PERIPHIDR3), > + coresight_cti_mgmt_reg(pidr4, CORESIGHT_PERIPHIDR4), > NULL, > }; > > @@ -258,13 +309,15 @@ static struct attribute *coresight_cti_mgmt_attrs[] = { > * If inaccessible & pcached_val not NULL then show cached value. > */ > static ssize_t cti_reg32_show(struct device *dev, char *buf, > - u32 *pcached_val, int reg_offset) > + u32 *pcached_val, int index) > { > u32 val = 0; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > raw_spin_lock(&drvdata->spinlock); > + reg_offset = cti_offset(drvdata, index, 0); > if ((reg_offset >= 0) && cti_active(config)) { > CS_UNLOCK(drvdata->base); > val = readl_relaxed(drvdata->base + reg_offset); > @@ -284,11 +337,12 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, > * if reg_offset >= 0 then write through if enabled. > */ > static ssize_t cti_reg32_store(struct device *dev, const char *buf, > - size_t size, u32 *pcached_val, int reg_offset) > + size_t size, u32 *pcached_val, int index) > { > unsigned long val; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > @@ -298,6 +352,7 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > if (pcached_val) > *pcached_val = (u32)val; > > + reg_offset = cti_offset(drvdata, index, 0); > /* write through if offset and enabled */ > if ((reg_offset >= 0) && cti_active(config)) > cti_write_single_reg(drvdata, reg_offset, val); > @@ -306,14 +361,14 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > } > > /* Standard macro for simple rw cti config registers */ > -#define cti_config_reg32_rw(name, cfgname, offset) \ > +#define cti_config_reg32_rw(name, cfgname, index) \ > static ssize_t name##_show(struct device *dev, \ > struct device_attribute *attr, \ > char *buf) \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_show(dev, buf, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > \ > static ssize_t name##_store(struct device *dev, \ > @@ -322,7 +377,7 @@ static ssize_t name##_store(struct device *dev, \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_store(dev, buf, size, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > static DEVICE_ATTR_RW(name) > > @@ -356,6 +411,46 @@ static ssize_t inout_sel_store(struct device *dev, > } > static DEVICE_ATTR_RW(inout_sel); > > +/* > + * QCOM CTI supports up to 128 triggers, there are 6 registers need to be > + * expanded to up to 4 instances, and regs_idx can be used to indicate which > + * one is in use. > + * CTITRIGINSTATUS, CTITRIGOUTSTATUS, > + * ITTRIGIN, ITTRIGOUT, > + * ITTRIGINACK, ITTRIGOUTACK. All the other selection indexes are of the form xxx_sel - this should be something along the lines of "ext_reg_sel" for consistency Additionally this information needs to appear as an entry in the documentation file Documentation/ABI/testing/sysfs-bus-coresight-devices-cti so users are aware of which registers this select relates to. > + */ > +static ssize_t regs_idx_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + u32 val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + raw_spin_lock(&drvdata->spinlock); > + val = drvdata->config.regs_idx; > + raw_spin_unlock(&drvdata->spinlock); > + return sprintf(buf, "%d\n", val); > +} > + > +static ssize_t regs_idx_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + unsigned long val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + if (val > ((drvdata->config.nr_trig_max + 31) / 32 - 1)) > + return -EINVAL; > + > + raw_spin_lock(&drvdata->spinlock); > + drvdata->config.regs_idx = val; > + raw_spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(regs_idx); see above - cheange to ..._sel > + > static ssize_t inen_show(struct device *dev, > struct device_attribute *attr, > char *buf) > @@ -389,7 +484,7 @@ static ssize_t inen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIINEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -428,7 +523,7 @@ static ssize_t outen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIOUTEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -448,9 +543,9 @@ static ssize_t intack_store(struct device *dev, > } > static DEVICE_ATTR_WO(intack); > > -cti_config_reg32_rw(gate, ctigate, CTIGATE); > -cti_config_reg32_rw(asicctl, asicctl, ASICCTL); > -cti_config_reg32_rw(appset, ctiappset, CTIAPPSET); > +cti_config_reg32_rw(gate, ctigate, INDEX_CTIGATE); > +cti_config_reg32_rw(asicctl, asicctl, INDEX_ASICCTL); > +cti_config_reg32_rw(appset, ctiappset, INDEX_CTIAPPSET); > > static ssize_t appclear_store(struct device *dev, > struct device_attribute *attr, > @@ -504,6 +599,7 @@ static DEVICE_ATTR_WO(apppulse); > */ > static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_inout_sel.attr, > + &dev_attr_regs_idx.attr, > &dev_attr_inen.attr, > &dev_attr_outen.attr, > &dev_attr_gate.attr, > @@ -512,20 +608,20 @@ static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_appset.attr, > &dev_attr_appclear.attr, > &dev_attr_apppulse.attr, > - coresight_cti_reg(triginstatus, CTITRIGINSTATUS), > - coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), > - coresight_cti_reg(chinstatus, CTICHINSTATUS), > - coresight_cti_reg(choutstatus, CTICHOUTSTATUS), > + coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), > + coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), > + coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), > + coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), > #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS > - coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), > - coresight_cti_reg(ittrigin, ITTRIGIN), > - coresight_cti_reg(itchin, ITCHIN), > - coresight_cti_reg_rw(ittrigout, ITTRIGOUT), > - coresight_cti_reg_rw(itchout, ITCHOUT), > - coresight_cti_reg(itchoutack, ITCHOUTACK), > - coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), > - coresight_cti_reg_wo(ittriginack, ITTRIGINACK), > - coresight_cti_reg_wo(itchinack, ITCHINACK), > + coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), > + coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), > + coresight_cti_reg(itchin, INDEX_ITCHIN), > + coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), > + coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), > + coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), > + coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), > + coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), > + coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), > #endif > NULL, > }; > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 0bd71407ef34..034d6fd1590b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -57,7 +57,38 @@ struct fwnode_handle; > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > + > +/* Qcom CTI supports up to 128 triggers*/ > +enum cti_subtype { > + ARM_STD_CTI, > + QCOM_CTI, > +}; > + > +/* These registers are remapped in Qcom CTI*/ > +enum cti_offset_index { > + INDEX_CTIINTACK, > + INDEX_CTIAPPSET, > + INDEX_CTIAPPCLEAR, > + INDEX_CTIAPPPULSE, > + INDEX_CTIINEN, > + INDEX_CTIOUTEN, > + INDEX_CTITRIGINSTATUS, > + INDEX_CTITRIGOUTSTATUS, > + INDEX_CTICHINSTATUS, > + INDEX_CTICHOUTSTATUS, > + INDEX_CTIGATE, > + INDEX_ASICCTL, > + INDEX_ITCHINACK, > + INDEX_ITTRIGINACK, > + INDEX_ITCHOUT, > + INDEX_ITTRIGOUT, > + INDEX_ITCHOUTACK, > + INDEX_ITTRIGOUTACK, > + INDEX_ITCHIN, > + INDEX_ITTRIGIN, > + INDEX_ITCTRL, > +}; > > /** > * Group of related trigger signals > @@ -149,6 +180,9 @@ struct cti_config { > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > + /* qcom_cti regs' index */ > + u8 regs_idx; rename to ..._sel as per comments above. This value also needs to be reset in the chan_xtrigs_reset_store() function in coresight-cti-sysfs.c > + > /* cti cross trig programmable regs */ > u8 ctiinout_sel; > u32 ctiappset; > @@ -181,6 +215,8 @@ struct cti_drvdata { > struct cti_config config; > struct list_head node; > void (*csdev_release)(struct device *dev); > + enum cti_subtype subtype; > + const u32 *offsets; > }; > > /* > @@ -234,6 +270,11 @@ struct coresight_platform_data * > coresight_cti_get_platform_data(struct device *dev); > const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); > > +static inline u32 cti_offset(struct cti_drvdata *drvdata, int index, int num) > +{ > + return drvdata->offsets[index] + 4 * num; > +} > + > /* cti powered and enabled */ > static inline bool cti_active(struct cti_config *cfg) > { > diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h > new file mode 100644 > index 000000000000..eaa551ff118a > --- /dev/null > +++ b/drivers/hwtracing/coresight/qcom-cti.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#define ARCHITECT_QCOM 0x477 > + This value which is an 11 bit value, in bits 31:21 of the DEVARCH register, is co-incidentally the same as the top 12 bits 31:20 of the ARM DEVARCH register for standard ARM component. Bit 20 of DEVARCH is 1'b1 for present - the 11 bits 31:21 make the archiitect value. ARMs assigned JEDEC architect value 11h'23B which when shifted left by one and ORed with bit 20 gives a value of 12h'477 for bits 31:20. Assuming that your 11 bit JEDEC architect value is 0x477 then the top 12 bits of the qcom devarch register must be 12h'8EF I'd like to be sure that no errors have been made, please confim that bits 31:20 in your DEVARCH register are 0x8EF, and this patch has been tested as working on your system. Thanks and Regards Mike > +/* CTI programming registers */ > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08c > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > > -- > 2.43.0 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months

← Newer
1
...
8
9
10
11
12
13
14
...
262
Older →

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight