CoreSight

coresight@lists.linaro.org

5 participants
2698 discussions

[PATCH v8 00/13] coresight: Update timestamp attribute to be an interval instead of bool

by James Clark

Do some cleanups then expand the timestamp format attribute from 1 bit to 4 bits for ETMv4 in Perf mode. The current interval is too high for most use cases, and particularly on the FVP the number of timestamps generated is excessive. This change not only still allows disabling or enabling timestamps, but also allows the interval to be configured. The old bit is kept deprecated and undocumented for now. There are known broken versions of Perf that don't read the format attribute positions from sysfs and instead hard code the timestamp bit. We can leave the old bit in the driver until we need the bit for another feature or enough time has passed that these old Perfs are unlikely to be used. The interval option is added as an event format attribute, rather than a Coresight config because it's something that the driver is already configuring automatically in Perf mode using any unused counter, so it's not possible to modify this with a config. Applies to coresight/next Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v8: - Handle ts_level attribute outside etm4_config_timestamp_event() (Mike) - Flip commits 11 and 12 so that the new attribute works as soon as it's published to sysfs for bisecting (Suzuki) - Remove some spurious header includes - Link to v7: https://lore.kernel.org/r/20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@lina… Changes in v7: - Change TRCCNTCTLRn and TRCTSCTLR register definitions to use a combined field for TYPE and SEL (EVENT) so that they can be used with the new utilities. - Add utility functions for creating resource selectors that do compile and runtime checking of the resource selector ID. - Link to v6: https://lore.kernel.org/r/20251119-james-cs-syncfreq-v6-0-740d24a29e51@lina… Changes in v6: - #ifdef out format attributes for ETMv3 instead of using is_visible(). Then the same block can be used to define format_attr_contextid_show() which avoids an awkward WARN_ONCE() and comments in arm32 for a function that's never called. - Link to v5: https://lore.kernel.org/r/20251118-james-cs-syncfreq-v5-0-82efd7b1a751@lina… Changes in v5: - Add parens to interval calculation in docs (Randy) - Swap "minimum interval" and "maximum interval" in docs. (Leo) - Add TRCSYNCPR.PERIOD to docs (Leo) - Use CONFIG_ARM64 to avoid is_kernel_in_hyp_mode() (Leo) - Add a comment for hidden ETMv3 format attributes (Leo) - Hide configid for ETMv3 (Leo) - Link to v4: https://lore.kernel.org/r/20251112-james-cs-syncfreq-v4-0-165ba21401dc@lina… Changes in v4: - Add #defines for true and false resources ETM_RES_SEL_TRUE/FALSE - Reword comment about finding a counter to say if there are no resources there are no counters. - Extend existing timestamp format attribute instead of adding a new one - Refactor all the config definitions and parsing to use GEN_PMU_FORMAT_ATTR()/ATTR_CFG_GET_FLD() so we can see where the unused bits are. - Link to v3: https://lore.kernel.org/r/20251002-james-cs-syncfreq-v3-0-fe5df2bf91d1@lina… Changes in v3: - Move the format attr definitions to coresight-etm-perf.h we can compile on arm32 without #ifdefs - (Leo) - Convert the new #ifdefs to a single one in an is_visible() function so that the code is cleaner - (Leo) - Drop the change to remove the holes in struct etmv4_config as they were grouped by function - (Mike) - Link to v2: https://lore.kernel.org/r/20250814-james-cs-syncfreq-v2-0-c76fcb87696d@lina… Changes in v2: - Only show the attribute for ETMv4 to improve usability and fix the arm32 build error. Wrapping everything in IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) isn't ideal, but the -perf.c file is shared between ETMv3 and ETMv4, and there is already precedent for doing it this way. - Link to v1: https://lore.kernel.org/r/20250811-james-cs-syncfreq-v1-0-b001cd6e3404@lina… --- James Clark (13): coresight: Change syncfreq to be a u8 coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Hide unused ETMv3 format attributes coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() coresight: Don't reject unrecognized ETMv3 format attributes coresight: Interpret perf config with ATTR_CFG_GET_FLD() coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() coresight: Remove misleading definitions coresight: Prepare to allow setting the timestamp interval coresight: Extend width of timestamp format attribute coresight: docs: Document etm4x timestamp interval option Documentation/trace/coresight/coresight.rst | 16 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 68 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.h | 38 +++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 39 +++-- drivers/hwtracing/coresight/coresight-etm4x-core.c | 175 ++++++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 92 ++++++++--- include/linux/coresight-pmu.h | 24 --- 7 files changed, 279 insertions(+), 173 deletions(-) --- base-commit: 9e9182cab5ebc3ee7544e60ef08ba19fdf216920 change-id: 20250724-james-cs-syncfreq-7c2257a38ed3 Best regards, -- James Clark <james.clark(a)linaro.org>

3 months, 2 weeks

[PATCH] MAINTAINERS: Change of email address

by Mike Leach

My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..e3974f9f300a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2657,7 +2657,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20476,7 +20476,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.32.0

3 months, 2 weeks

tunning Pakistani Bridal Dresses Online – Imrozia Serene Collection

by tomoka2355＠gamintor.com

Discover the exquisite range of Pakistani bridal dresses online at Imrozia Serene, where timeless elegance meets modern design. From intricately embroidered lehengas to luxurious bridal ensembles, each piece in this collection is crafted to make your special day unforgettable. Shop now for premium quality, beautiful craftsmanship, and styles that celebrate tradition with a contemporary touch — perfect for brides who want to look radiant on their wedding day. Get More Info: https://imroziaserene.com/collections/bridal

3 months, 3 weeks

Elegant Watches for Women in Pakistan – Leather Band Collection

by tomoka2355＠gamintor.com

Explore a stunning range of women’s leather band watches at Ferro.pk, where sophistication meets everyday comfort. These stylish timepieces are designed to add charm and personality to any outfit, offering a perfect blend of elegance, versatility, and comfort for women across Pakistan. Whether you’re dressing up for a special occasion or looking for a chic accessory for daily wear, Ferro.pk’s women’s leather strap watches deliver quality, authenticity, and nationwide delivery right to your doorstep. Get More info:https://ferro.pk/collections/women-leather-band

3 months, 3 weeks

Preparing Yourself Before Choosing a Local Phone Repair Option

by tomoka2355＠gamintor.com

Searching for a phone repair shop near me can feel simple, but being prepared makes the experience smoother and more reliable. Before trusting any phone repair shop near me, it helps to understand your device issue, back up your data, and know your phone model. People often assume every phone repair shop near me offers the same expertise, but experience shows that preparation leads to better outcomes. Services like door2doormobilerepair highlight how informed users communicate problems more clearly. Taking a moment to research what a phone repair shop near me typically handles builds confidence, and door2doormobilerepair reflects how preparation supports trust when choosing a phone repair shop near me. Get More Info: https://door2doormobilerepair.com/smartphone-repair/

3 months, 3 weeks

Preparing Yourself Before Choosing a Local Phone Repair Option

by tomoka2355＠gamintor.com

3 months, 3 weeks

Lumexa Skin Brightening Serum – Glow-Boosting Formula for Clear Skin

by tomoka2355＠gamintor.com

Lumexa Skin Brightening Serum is a lightweight, fast-absorbing formula designed to help enhance your skin’s natural glow and promote a more even-looking tone. Infused with carefully selected brightening and hydrating ingredients, it works to reduce the appearance of dullness while leaving skin feeling smooth, fresh, and radiant. With regular use, Lumexa helps your complexion look clearer, healthier, and visibly luminous without feeling heavy or greasy. Get More info: https://mazton.ae/collections/skin-care/products/lumexa-skin-brightening-se…

3 months, 3 weeks

Lumexa Skin Brightening Serum – Glow-Boosting Formula for Clear Skin

by tomoka2355＠gamintor.com

3 months, 3 weeks

[PATCH v4 0/3] Coresight TMC-ETR: refactor the tmc-etr mode and some cleanups

by Junhao He

This patchset builds upon Yicong's previous patches [1]. Patch 2 introducing fix race issues found by using TMC-ETR. Patch 1 & 3 introducing two cleanups found when debugging the issues. [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… --- Changes in v4: - a) Add comment at the context of set etr to sysfs mode. - b) Move the check on drvdata->read to the start of enable etr. - c) Add checks to prevent multiple sysfs processes from simultaneously competing to enable ETR. - d) Fix the issue with the guard used. Link: https://lore.kernel.org/linux-arm-kernel/20250818080600.418425-1-hejunhao3@… --- Changes in v3: - Patches 1: Additional comment for tmc_drvdata::etr_mode. Update comment for tmc_drvdata::reading with Jonathan's Tag. - Patches 2: Replace scoped_guard with guard with Jonathan's Tag. - Patches 2: Fix spinlock to raw_spinlock, and refactor this code based on Leo's suggested solution. - Patches 3: change the size's type to ssize_t and use max_t to simplify the code with Leo's Tag. Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@… Changes in v2: - Updated the commit of patch2. - Rebase to v6.16-rc1 Junhao He (1): coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions Yicong Yang (2): coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata coresight: tmc: Decouple the perf buffer allocation from sysfs mode .../hwtracing/coresight/coresight-tmc-etr.c | 136 +++++++++--------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + 2 files changed, 66 insertions(+), 72 deletions(-) -- 2.33.0

3 months, 3 weeks

Re: [PATCH v7 3/4] coresight: tpda: add logic to configure TPDA_SYNCR register

by Suzuki K Poulose

On 23/12/2025 08:41, Jie Gan wrote: > From: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > > The TPDA_SYNC counter tracks the number of bytes transferred from the > aggregator. When this count reaches the value programmed in the > TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace > tools to accurately parse each valid packet. > > Signed-off-by: Tao Zhang <tao.zhang(a)oss.qualcomm.com> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Co-developed-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../ABI/testing/sysfs-bus-coresight-devices-tpda | 18 +++++ > drivers/hwtracing/coresight/coresight-tpda.c | 90 ++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpda.h | 10 +++ > 3 files changed, 118 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > index c8bc7b19ab25..c989eea1ef59 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda > @@ -41,3 +41,21 @@ Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qu > Description: > (RW) Set global (all ports) flush request bit. The bit remains set until a > global flush request sequence completes. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_mode > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set mode the of the syncr counter. > + mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests > + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K > + data by writing a value 13 to the COUNT[11:7] field. > + > +What: /sys/bus/coresight/devices/<tpda-name>/syncr_count > +Date: December 2025 > +KernelVersion: 6.19 > +Contact: Jinlong Mao <jinlong.mao(a)oss.qualcomm.com>, Tao Zhang <tao.zhang(a)oss.qualcomm.com>, Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: > + (RW) Set value the of the syncr counter. > + Range: 0-4095 > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index d24a9098f1b1..8283e16ec400 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -163,6 +163,20 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) > */ > if (drvdata->trig_flag_ts) > writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); > + > + /* Initialize with a value of 0 */ > + val = 0; > + if (drvdata->syncr_mode) > + val |= TPDA_SYNCR_MODE_CTRL_MASK; > + > + if (drvdata->syncr_count > 0 && > + drvdata->syncr_count < TPDA_SYNCR_COUNT_MASK) > + val |= drvdata->syncr_count; > + else > + /* Program the count to its MAX value by default */ > + val |= TPDA_SYNCR_COUNT_MASK; > + > + writel_relaxed(val, drvdata->base + TPDA_SYNCR); > } > > static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) > @@ -385,8 +399,84 @@ static ssize_t global_flush_req_store(struct device *dev, > } > static DEVICE_ATTR_RW(global_flush_req); > > +static ssize_t syncr_mode_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val, syncr_val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + syncr_val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val = FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_mode_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + /* set the mode when first enabling the device */ > + drvdata->syncr_mode = !!val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_mode); > + > +static ssize_t syncr_count_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (!drvdata->csdev->refcnt) > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + val = readl_relaxed(drvdata->base + TPDA_SYNCR); > + val &= TPDA_SYNCR_COUNT_MASK; > + > + return sysfs_emit(buf, "%lu\n", val); > +} > + > +static ssize_t syncr_count_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, > + size_t size) > +{ > + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + > + if (val < 0 || val > TPDA_SYNCR_COUNT_MASK) Checking "val < 0" for an unsigned type is invalid. Simply keep the second part. Suzuki > + return -EINVAL; > + > + guard(spinlock)(&drvdata->spinlock); > + drvdata->syncr_count = val; > + > + return size; > +} > +static DEVICE_ATTR_RW(syncr_count); > + > static struct attribute *tpda_attrs[] = { > &dev_attr_global_flush_req.attr, > + &dev_attr_syncr_mode.attr, > + &dev_attr_syncr_count.attr, > tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), > tpda_trig_sysfs_rw(trig_freq_enable, FRIE), > tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), > diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h > index 1cc9253293ec..56d35697303a 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.h > +++ b/drivers/hwtracing/coresight/coresight-tpda.h > @@ -9,6 +9,7 @@ > #define TPDA_CR (0x000) > #define TPDA_Pn_CR(n) (0x004 + (n * 4)) > #define TPDA_FPID_CR (0x084) > +#define TPDA_SYNCR (0x08C) > > /* Cross trigger global (all ports) flush request bit */ > #define TPDA_CR_FLREQ BIT(0) > @@ -36,6 +37,11 @@ > /* Aggregator port DSB data set element size bit */ > #define TPDA_Pn_CR_DSBSIZE BIT(8) > > +/* TPDA_SYNCR count mask */ > +#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0) > +/* TPDA_SYNCR mode control bit */ > +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) > + > #define TPDA_MAX_INPORTS 32 > > /** > @@ -52,6 +58,8 @@ > * @trig_freq: Enable/disable cross trigger FREQ packet request interface. > * @freq_ts: Enable/disable the timestamp for all FREQ packets. > * @cmbchan_mode: Configure the CMB/MCMB channel mode. > + * @syncr_mode: Setting the mode for counting packets. > + * @syncr_count: Setting the value of the count. > */ > struct tpda_drvdata { > void __iomem *base; > @@ -66,6 +74,8 @@ struct tpda_drvdata { > bool trig_freq; > bool freq_ts; > bool cmbchan_mode; > + bool syncr_mode; > + u32 syncr_count; > }; > > /* Enumerate members of global control register(cr) */ >

4 months

← Newer
1
...
8
9
10
11
12
13
14
...
270
Older →

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight