CoreSight

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[PATCH v2 0/8] coresight: Clear self hosted claim tag on probe

by James Clark

I've gotten stuck a few times with unusable Coresight after a warm boot due to lingering claim tags, especially when testing the Coresight panic patchsets. This change does some tidy ups, adds some debug messages and clears the self hosted claim tag on probe. The last two commits are unrelated tidyups but they touch some of the same functions so to avoid extra conflicts I'm including them here. This gets as far as fixing the claim tag issue, but there is some other state not being cleared on probe that results in the following error. This can be fixed up as a later change: coresight tmc_etf0: timeout while waiting for TMC to be Ready coresight tmc_etf0: Failed to enable : TMC is not ready Changes in v2: * Revert most of the interface changes, just call coresight_clear_self_claim_tag() directly. This is possible because we're not doing the read first, so it has fewer knock on effects. * Split out the change to add struct cs_access to etm3x * Add another warning for racing with external debugger -- 2.34.1 --- James Clark (8): coresight: Rename coresight_{set,clear}_claim_tags() coresight: Convert tag clear function to take a struct cs_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: etm3x: Convert raw base pointer to struct coresight access coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations drivers/hwtracing/coresight/coresight-catu.c | 12 +-- drivers/hwtracing/coresight/coresight-core.c | 85 ++++++++++++++-------- drivers/hwtracing/coresight/coresight-cti-core.c | 2 + drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm.h | 6 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 28 +++---- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-platform.c | 26 +++---- drivers/hwtracing/coresight/coresight-priv.h | 20 ++--- drivers/hwtracing/coresight/coresight-replicator.c | 3 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- .../coresight/coresight-syscfg-configfs.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 9 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 16 ++-- drivers/hwtracing/coresight/coresight-trbe.c | 18 ++--- include/linux/coresight.h | 40 +++++----- 19 files changed, 166 insertions(+), 134 deletions(-) --- base-commit: 5442d22da7dbff3ba8c6720fc6f23ea4934d402d change-id: 20250317-james-coresight-claim-tags-ae1461f1f5e0 Best regards, -- James Clark <james.clark(a)linaro.org>

3 months

[PATCH] arm: coresight: Finish removal of Coresight support in arch/arm/kernel

by James Clark

Commit 184901a06a36 ("ARM: removing support for etb/etm in "arch/arm/kernel/"") removed asm/hardware/coresight.h which is included by this file. Therefore this is dead code so delete it. Signed-off-by: James Clark <james.clark(a)linaro.org> --- arch/arm/include/asm/cti.h | 160 ------------------------------------- 1 file changed, 160 deletions(-) delete mode 100644 arch/arm/include/asm/cti.h diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h deleted file mode 100644 index f8500e5d6ea8..000000000000 --- a/arch/arm/include/asm/cti.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASMARM_CTI_H -#define __ASMARM_CTI_H - -#include <asm/io.h> -#include <asm/hardware/coresight.h> - -/* The registers' definition is from section 3.2 of - * Embedded Cross Trigger Revision: r0p0 - */ -#define CTICONTROL 0x000 -#define CTISTATUS 0x004 -#define CTILOCK 0x008 -#define CTIPROTECTION 0x00C -#define CTIINTACK 0x010 -#define CTIAPPSET 0x014 -#define CTIAPPCLEAR 0x018 -#define CTIAPPPULSE 0x01c -#define CTIINEN 0x020 -#define CTIOUTEN 0x0A0 -#define CTITRIGINSTATUS 0x130 -#define CTITRIGOUTSTATUS 0x134 -#define CTICHINSTATUS 0x138 -#define CTICHOUTSTATUS 0x13c -#define CTIPERIPHID0 0xFE0 -#define CTIPERIPHID1 0xFE4 -#define CTIPERIPHID2 0xFE8 -#define CTIPERIPHID3 0xFEC -#define CTIPCELLID0 0xFF0 -#define CTIPCELLID1 0xFF4 -#define CTIPCELLID2 0xFF8 -#define CTIPCELLID3 0xFFC - -/* The below are from section 3.6.4 of - * CoreSight v1.0 Architecture Specification - */ -#define LOCKACCESS 0xFB0 -#define LOCKSTATUS 0xFB4 - -/** - * struct cti - cross trigger interface struct - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out_for_irq: triger out number which will cause - * the @irq happen - * - * cti struct used to operate cti registers. - */ -struct cti { - void __iomem *base; - int irq; - int trig_out_for_irq; -}; - -/** - * cti_init - initialize the cti instance - * @cti: cti instance - * @base: mapped virtual address for the cti base - * @irq: irq number for the cti - * @trig_out: triger out number which will cause - * the @irq happen - * - * called by machine code to pass the board dependent - * @base, @irq and @trig_out to cti. - */ -static inline void cti_init(struct cti *cti, - void __iomem *base, int irq, int trig_out) -{ - cti->base = base; - cti->irq = irq; - cti->trig_out_for_irq = trig_out; -} - -/** - * cti_map_trigger - use the @chan to map @trig_in to @trig_out - * @cti: cti instance - * @trig_in: trigger in number - * @trig_out: trigger out number - * @channel: channel number - * - * This function maps one trigger in of @trig_in to one trigger - * out of @trig_out using the channel @chan. - */ -static inline void cti_map_trigger(struct cti *cti, - int trig_in, int trig_out, int chan) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINEN + trig_in * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIINEN + trig_in * 4); - - val = __raw_readl(base + CTIOUTEN + trig_out * 4); - val |= BIT(chan); - __raw_writel(val, base + CTIOUTEN + trig_out * 4); -} - -/** - * cti_enable - enable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_enable(struct cti *cti) -{ - __raw_writel(0x1, cti->base + CTICONTROL); -} - -/** - * cti_disable - disable the cti module - * @cti: cti instance - * - * enable the cti module - */ -static inline void cti_disable(struct cti *cti) -{ - __raw_writel(0, cti->base + CTICONTROL); -} - -/** - * cti_irq_ack - clear the cti irq - * @cti: cti instance - * - * clear the cti irq - */ -static inline void cti_irq_ack(struct cti *cti) -{ - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + CTIINTACK); - val |= BIT(cti->trig_out_for_irq); - __raw_writel(val, base + CTIINTACK); -} - -/** - * cti_unlock - unlock cti module - * @cti: cti instance - * - * unlock the cti module, or else any writes to the cti - * module is not allowed. - */ -static inline void cti_unlock(struct cti *cti) -{ - __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); -} - -/** - * cti_lock - lock cti module - * @cti: cti instance - * - * lock the cti module, so any writes to the cti - * module will be not allowed. - */ -static inline void cti_lock(struct cti *cti) -{ - __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); -} -#endif -- 2.34.1

3 months

[PATCH 0/7] coresight: Clear self hosted claim tag on probe

by James Clark

I've gotten stuck a few times with unusable Coresight after a warm boot due to lingering claim tags, especially when testing the Coresight panic patchsets. This change does some tidy ups, adds some debug messages and clears the self hosted claim tag on probe. The last two commits are unrelated tidyups but they touch some of the same functions so to avoid extra conflicts I'm including them here. This gets as far as fixing the claim tag issue, but there is some other state not being cleared on probe that results in the following error. This can be fixed up as a later change: coresight tmc_etf0: timeout while waiting for TMC to be Ready coresight tmc_etf0: Failed to enable : TMC is not ready James Clark (7): coresight: Rename coresight_{set,clear}_claim_tags() coresight: Convert disclaim functions to take a struct cs_access coresight: Only check bottom two claim bits coresight: Add claim tag warnings and debug messages coresight: Clear self hosted claim tag on probe coresight: Remove inlines from static function definitions coresight: Remove extern from function declarations drivers/hwtracing/coresight/coresight-catu.c | 14 +- drivers/hwtracing/coresight/coresight-core.c | 132 +++++++++++------- .../hwtracing/coresight/coresight-cti-core.c | 8 +- drivers/hwtracing/coresight/coresight-etb10.c | 6 +- drivers/hwtracing/coresight/coresight-etm.h | 6 +- .../coresight/coresight-etm3x-core.c | 32 ++--- .../coresight/coresight-etm3x-sysfs.c | 8 +- .../coresight/coresight-etm4x-core.c | 12 +- .../coresight/coresight-etm4x-sysfs.c | 4 +- .../hwtracing/coresight/coresight-funnel.c | 4 +- .../hwtracing/coresight/coresight-platform.c | 26 ++-- drivers/hwtracing/coresight/coresight-priv.h | 20 +-- .../coresight/coresight-replicator.c | 7 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- .../coresight/coresight-syscfg-configfs.c | 2 +- .../hwtracing/coresight/coresight-tmc-core.c | 9 +- .../hwtracing/coresight/coresight-tmc-etf.c | 8 +- .../hwtracing/coresight/coresight-tmc-etr.c | 20 ++- drivers/hwtracing/coresight/coresight-trbe.c | 18 +-- include/linux/coresight.h | 32 ++--- 20 files changed, 209 insertions(+), 165 deletions(-) -- 2.34.1

3 months

[GIT PULL] coresight: Updates for v6.15

by Suzuki K Poulose

Hi Greg, Please find the updates for coresight/hwtracing subsystem targeting v6.15. Kindly pull, Suzuki The following changes since commit 0ad2507d5d93f39619fc42372c347d6006b64319: Linux 6.14-rc3 (2025-02-16 14:02:44 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.15 for you to fetch changes up to 5442d22da7dbff3ba8c6720fc6f23ea4934d402d: Coresight: Fix a NULL vs IS_ERR() bug in probe (2025-03-14 12:43:53 +0000) ---------------------------------------------------------------- coresight: updates for Linux v6.15 CoreSight self-hosted tracing driver subsystem update for Linux v6.15. The update includes: - CoreSight trace capture for Panic/Watchdog timeouts - Fixes to ETM4x driver to synchronize register reads as required by the TRM - Support for Qualcomm CoreSight TMC Control Unit driver - Conversion of device locks to raw_spinlock for components that are used by the Perf mode. - Miscellaneous fixes for the subsystem Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Christophe JAILLET (1): coresight: configfs: Constify struct config_item_type Dan Carpenter (1): Coresight: Fix a NULL vs IS_ERR() bug in probe Ilkka Koskinen (1): coresight: catu: Fix number of pages while using 64k pages James Clark (2): Coresight: Use coresight_etm_get_trace_id() in traceid_show() coresight: docs: Remove target sink from examples Jie Gan (9): Coresight: Add support for new APB clock name Coresight: Add trace_id function to retrieving the trace ID Coresight: Introduce a new struct coresight_path Coresight: Allocate trace ID after building the path Coresight: Change to read the trace ID from coresight_path Coresight: Change functions to accept the coresight_path dt-bindings: arm: Add Coresight TMC Control Unit hardware Coresight: Add Coresight TMC Control Unit driver coresight: add verification process for coresight_etm_get_trace_id Krzysztof Kozlowski (5): coresight: catu: Constify amba_id table coresight: tpda: Constify amba_id table coresight: tpdm: Constify amba_id table dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM Wolfram Sang (1): coresight: etm4x: don't include '<linux/pm_wakeup.h>' directly Yeoreum Yun (9): coresight: change coresight_device lock type to raw_spinlock_t coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t coresight: change coresight_trace_id_map's lock type to raw_spinlock_t coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t coresight-funnel: change funnel_drvdata spinlock's type to raw_spinlock_t coresight-replicator: change replicator_drvdata spinlock's type to raw_spinlock_t coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t coresight/ultrasoc: change smb_drv_data spinlock's type to raw_spinlock_t Yuanfang Zhang (1): coresight-etm4x: add isb() before reading the TRCSTATR .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 15 + .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 26 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++ .../bindings/arm/qcom,coresight-tpda.yaml | 3 +- .../bindings/arm/qcom,coresight-tpdm.yaml | 3 +- Documentation/trace/coresight/coresight.rst | 41 +-- Documentation/trace/coresight/panic.rst | 362 +++++++++++++++++++++ Documentation/userspace-api/perf_ring_buffer.rst | 4 +- drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 4 +- drivers/hwtracing/coresight/coresight-catu.c | 4 +- .../hwtracing/coresight/coresight-cfg-preload.c | 2 + .../hwtracing/coresight/coresight-cfg-preload.h | 2 + drivers/hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++ drivers/hwtracing/coresight/coresight-config.c | 8 +- drivers/hwtracing/coresight/coresight-config.h | 2 +- drivers/hwtracing/coresight/coresight-core.c | 192 +++++++++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 326 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-ctcu.h | 39 +++ drivers/hwtracing/coresight/coresight-cti-core.c | 44 +-- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 76 ++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 15 +- drivers/hwtracing/coresight/coresight-etb10.c | 26 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 27 +- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 +- drivers/hwtracing/coresight/coresight-etm.h | 1 - drivers/hwtracing/coresight/coresight-etm3x-core.c | 55 +--- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 3 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 122 +++---- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 254 +++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +- drivers/hwtracing/coresight/coresight-funnel.c | 12 +- drivers/hwtracing/coresight/coresight-priv.h | 14 +- drivers/hwtracing/coresight/coresight-replicator.c | 12 +- drivers/hwtracing/coresight/coresight-stm.c | 13 +- .../coresight/coresight-syscfg-configfs.c | 12 +- drivers/hwtracing/coresight/coresight-syscfg.c | 26 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 327 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 140 ++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 224 +++++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 106 +++++- drivers/hwtracing/coresight/coresight-tpda.c | 20 +- drivers/hwtracing/coresight/coresight-tpdm.c | 124 ++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +- drivers/hwtracing/coresight/coresight-trace-id.c | 22 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 12 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- include/linux/coresight.h | 47 ++- 50 files changed, 2452 insertions(+), 553 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-core.c create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h

3 months

[PATCH v2] coresight: Fixes device's owner field for registered using coresight_init_driver()

by Junhao He

The coresight_init_driver() of the coresight-core module is called from the sub coresgiht device (such as tmc/stm/funnle/...) module. It calls amba_driver_register() and Platform_driver_register(), which are macro functions that use the coresight-core's module to initialize the caller's owner field. Therefore, when the sub coresight device calls coresight_init_driver(), an incorrect THIS_MODULE value is captured. The sub coesgiht modules can be removed while their callbacks are running, resulting in a general protection failure. User a macro to automatically add the THIS_MODULE param to coresight_init_driver() to fix this. Fixes: 075b7cd7ad7d ("coresight: Add helpers registering/removing both AMBA and platform drivers") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> --- Changes in v2: - even a macro to automatically add the THIS_MODULE param for coresight_init_driver(); - Link to v1: https://lore.kernel.org/lkml/c3744062-f7c1-82df-2fa1-591da3b2dc5e@huawei.co… --- drivers/hwtracing/coresight/coresight-core.c | 11 ++++++----- include/linux/coresight.h | 7 +++++-- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 0a9380350fb5..abf2e4fd4de0 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1486,18 +1486,19 @@ static void __exit coresight_exit(void) module_init(coresight_init); module_exit(coresight_exit); -int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, - struct platform_driver *pdev_drv) +int coresight_init_driver_owner(const char *drv, struct amba_driver *amba_drv, + struct platform_driver *pdev_drv, + struct module *owner) { int ret; - ret = amba_driver_register(amba_drv); + ret = __amba_driver_register(amba_drv, owner); if (ret) { pr_err("%s: error registering AMBA driver\n", drv); return ret; } - ret = platform_driver_register(pdev_drv); + ret = __platform_driver_register(pdev_drv, owner); if (!ret) return 0; @@ -1505,7 +1506,7 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, amba_driver_unregister(amba_drv); return ret; } -EXPORT_SYMBOL_GPL(coresight_init_driver); +EXPORT_SYMBOL_GPL(coresight_init_driver_owner); void coresight_remove_driver(struct amba_driver *amba_drv, struct platform_driver *pdev_drv) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 17276965ff1d..b07455956f7a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -689,8 +689,11 @@ coresight_find_output_type(struct coresight_platform_data *pdata, enum coresight_dev_type type, union coresight_dev_subtype subtype); -int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, - struct platform_driver *pdev_drv); +int coresight_init_driver_owner(const char *drv, struct amba_driver *amba_drv, + struct platform_driver *pdev_drv, struct module *owner); + +#define coresight_init_driver(name, amba_drv, pdev_drv) \ + coresight_init_driver_owner(name, amba_drv, pdev_drv, THIS_MODULE) void coresight_remove_driver(struct amba_driver *amba_drv, struct platform_driver *pdev_drv); -- 2.33.0

3 months

Re: [PATCH next] Coresight: Fix a NULL vs IS_ERR() bug in probe

by Suzuki K Poulose

On Fri, 14 Mar 2025 13:55:10 +0300, Dan Carpenter wrote: > The devm_platform_get_and_ioremap_resource() function doesn't > return NULL, it returns error pointers. Update the checking to > match. > > Applied, thanks! [1/1] Coresight: Fix a NULL vs IS_ERR() bug in probe (no commit info) Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 months

Re: [PATCH next] Coresight: Fix a NULL vs IS_ERR() bug in probe

by Anshuman Khandual

On 3/14/25 16:25, Dan Carpenter wrote: > The devm_platform_get_and_ioremap_resource() function doesn't > return NULL, it returns error pointers. Update the checking to > match. > > Fixes: f78d206f3d73 ("Coresight: Add Coresight TMC Control Unit driver") > Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> > --- > drivers/hwtracing/coresight/coresight-ctcu-core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index da35d8b4d579..c6bafc96db96 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -204,8 +204,8 @@ static int ctcu_probe(struct platform_device *pdev) > dev->platform_data = pdata; > > base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); > - if (!base) > - return -ENOMEM; > + if (IS_ERR(base)) > + return PTR_ERR(base); > > drvdata->apb_clk = coresight_get_enable_apb_pclk(dev); > if (IS_ERR(drvdata->apb_clk)) Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com>

3 months

Re: [PATCH v1 3/4] coresight: ctcu: Enable byte-cntr for TMC ETR devices

by Suzuki K Poulose

On 14/03/2025 01:59, Jie Gan wrote: > > > On 3/14/2025 12:24 AM, Suzuki K Poulose wrote: >> On 10/03/2025 09:04, Jie Gan wrote: >>> The byte-cntr function provided by the CTCU device is used to >>> transfer data >>> from the ETR buffer to the userspace. An interrupt is triggered if >>> the data >> >> Why do we need a new device to transfer the data to userspace ? > > Hi Suzuki Mike, > > The purpose of the byte-cntr is for live debugging, allowing trace data > to be read while the ETR is running and preventing the required trace > data from being overwritten before output. > > I realized that I forgot to introduce the function of the BYTECNTRCTL > register. > > There is a big concern that reading the etr_buf while the ETR is running > is unsafe because the etr_buf is not synced, am right? Unsafe to read the buffer, written to by the ETR. > > As I mentioned, we need program a value to the BYTECNTRCTL register. The > hardware will count the bytes of the trace data that are routed to > RAM(etr_buf). > > The interrupt will be trigger once the counted bytes exceed the > programmed value. Based on this concept, we can confirm this part of > trace data is already in the etr_buf and is safe to read. So, it's safe > for the read function only read this part of trace data in one > shot(unlike tmc_read, the whole synced etr_buf). Since the ETR is used in CIRCULAR buffer mode, what is the guarantee that it is not overwritten while you are reading ? > > That's how we expect the byte-cntr to work when reading the trace data > from the etr_buf while the etr is running. We understood the functionality of byte-counter, but we think : 1. What you are doing is not safe. ETR can overwrite while you may be reading. 2. Adding another "character" file to expose the "same" data. What we would like to see : 1. Solve the problem of ETR writing into the etr_buf, while you are copying it. This could be via: a. Stop the ETR while you are copying the buffer OR b. Split the "buffer" available for ETR to two or more parts, limiting the ETR to only allowing writing to one part. On interrupt, disable the interrupt, and modify the ETR to use the next part. Now you can safely expose the "finished" part to the user. 2. Don't add another file. Use the existing one. > > This also explains why we need a separate dev node to manage the read > function for byte-cntr. No, you don't. Suzuki > > Thanks, > Jie > > >> >>> size exceeds the threshold set in the BYTECNTRVAL register. The >>> interrupt >>> handler counts the number of triggered interruptions and the read >>> function >>> will read the data from the ETR buffer if the IRQ count is greater >>> than 0. >>> Each successful read process will decrement the IRQ count by 1. >> >> Having an interrupt is good, but see below. >> >>> >>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>> --- >>> drivers/hwtracing/coresight/Makefile | 2 +- >>> .../coresight/coresight-ctcu-byte-cntr.c | 339 ++++++++++++++++++ >>> .../hwtracing/coresight/coresight-ctcu-core.c | 96 ++++- >>> drivers/hwtracing/coresight/coresight-ctcu.h | 59 ++- >>> .../hwtracing/coresight/coresight-tmc-etr.c | 5 +- >>> drivers/hwtracing/coresight/coresight-tmc.h | 2 + >>> 6 files changed, 493 insertions(+), 10 deletions(-) >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte- >>> cntr.c >>> >>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/ >>> hwtracing/ coresight/Makefile >>> index 8e62c3150aeb..c90a06768a18 100644 >>> --- a/drivers/hwtracing/coresight/Makefile >>> +++ b/drivers/hwtracing/coresight/Makefile >>> @@ -52,4 +52,4 @@ coresight-cti-y := coresight-cti-core.o coresight- >>> cti-platform.o \ >>> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >>> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o >>> obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o >>> -coresight-ctcu-y := coresight-ctcu-core.o >>> +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o >>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>> b/ drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>> new file mode 100644 >>> index 000000000000..0d16385663f5 >>> --- /dev/null >>> +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>> @@ -0,0 +1,339 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights >>> reserved. >>> + */ >>> + >>> +#include <linux/coresight.h> >>> +#include <linux/device.h> >>> +#include <linux/dma-mapping.h> >>> +#include <linux/fs.h> >>> +#include <linux/interrupt.h> >>> +#include <linux/of_irq.h> >>> +#include <linux/property.h> >>> +#include <linux/uaccess.h> >>> + >>> +#include "coresight-ctcu.h" >>> +#include "coresight-priv.h" >>> +#include "coresight-tmc.h" >>> + >>> +#define BYTE_CNTR_CLASS_STR "byte-cntr-class" >>> + >>> +static struct class *byte_cntr_class; >>> +static dev_t byte_cntr_base; >>> + >>> +static irqreturn_t byte_cntr_handler(int irq, void *data) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr >>> *)data; >>> + >>> + atomic_inc(&byte_cntr_data->irq_cnt); >>> + wake_up(&byte_cntr_data->wq); >>> + >>> + return IRQ_HANDLED; >>> +} >>> + >>> +/* Read the data from ETR's DDR buffer. */ >>> +static void __ctcu_byte_cntr_read_etr_bytes(struct ctcu_byte_cntr >>> *byte_cntr_data, >>> + size_t *len, char **bufp) >>> +{ >>> + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data- >>> >sink->dev.parent); >>> + size_t actual, bytes = byte_cntr_data->thresh_val; >>> + struct etr_buf *etr_buf = tmcdrvdata->sysfs_buf; >>> + long r_offset; >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + r_offset = byte_cntr_data->r_offset; >>> + if (*len >= bytes) >>> + *len = bytes; >>> + else if ((r_offset % bytes) + *len > bytes) >>> + *len = bytes - (r_offset % bytes); >>> + >>> + actual = tmc_etr_buf_get_data(etr_buf, r_offset, *len, bufp); >>> + *len = actual; >>> + if (actual == bytes || (actual + r_offset) % bytes == 0) >>> + atomic_dec(&byte_cntr_data->irq_cnt); >>> +} >>> + >> >> How can you safely read the ETR data while it is running ? You should >> stop the ETR and then provide the data. You could potentially do things >> like split the ETR buffer into two halves and switch the half used by >> the ETR on interrupt and expose this to user. >> >> >>> +/* Flush the remaining data in the ETR buffer after the byte cntr >>> has stopped. */ >>> +static ssize_t ctcu_flush_etr_buffer(struct ctcu_byte_cntr >>> *byte_cntr_data, size_t len, >>> + char **bufpp) >>> +{ >>> + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data- >>> >sink->dev.parent); >>> + struct etr_buf *etr_buf = tmcdrvdata->sysfs_buf; >>> + ssize_t read_len = 0, remaining_len; >>> + long r_offset, w_offset; >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + r_offset = byte_cntr_data->r_offset; >>> + w_offset = byte_cntr_data->w_offset; >>> + if (w_offset < r_offset) >>> + remaining_len = tmcdrvdata->size + w_offset - r_offset; >>> + else >>> + remaining_len = w_offset - r_offset; >>> + >>> + if (remaining_len > len) >>> + remaining_len = len; >>> + >>> + if (remaining_len > 0) >>> + read_len = tmc_etr_buf_get_data(etr_buf, r_offset, >>> remaining_len, bufpp); >>> + >>> + return read_len; >>> +} >>> + >>> +static ssize_t ctcu_byte_cntr_copy_data(char __user *data, size_t >>> len, char *bufp, >>> + struct ctcu_byte_cntr *byte_cntr_data, >>> + struct tmc_drvdata *tmcdrvdata) >>> +{ >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + if (copy_to_user(data, bufp, len)) >>> + return -EFAULT; >>> + >>> + byte_cntr_data->total_size += len; >>> + if (byte_cntr_data->r_offset + len >= tmcdrvdata->size) >>> + byte_cntr_data->r_offset = 0; >>> + else >>> + byte_cntr_data->r_offset += len; >>> + >>> + return len; >>> +} >>> + >>> +/* The read function for /dev/byte-cntr%d */ >> >> WHY ? WHY can't the data be exported by the existing /dev/tmc_etr* ? >> >>> +static ssize_t ctcu_byte_cntr_read_etr_bytes(struct file *fp, char >>> __user *data, >>> + size_t len, loff_t *ppos) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data = fp->private_data; >>> + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data- >>> >sink->dev.parent); >>> + char *bufp = NULL; >>> + ssize_t read_len; >>> + >>> + if (!data) >>> + return -EINVAL; >>> + >>> + /* >>> + * Flush the remaining data in the ETR buffer based on the write >>> + * offset of the ETR buffer when the byte cntr function has >>> stopped. >>> + */ >>> + if (!byte_cntr_data->read_active || !byte_cntr_data->enable) { >>> + read_len = ctcu_flush_etr_buffer(byte_cntr_data, len, &bufp); >>> + if (read_len > 0) >>> + return ctcu_byte_cntr_copy_data(data, read_len, bufp, >>> + byte_cntr_data, tmcdrvdata); >>> + >>> + return -EINVAL; >>> + } >>> + >>> + if (!atomic_read(&byte_cntr_data->irq_cnt)) { >>> + if (wait_event_interruptible(byte_cntr_data->wq, >>> + atomic_read(&byte_cntr_data->irq_cnt) > 0 || >>> + !byte_cntr_data->enable)) >>> + return -ERESTARTSYS; >>> + } >>> + >>> + __ctcu_byte_cntr_read_etr_bytes(byte_cntr_data, &len, &bufp); >>> + >>> + return ctcu_byte_cntr_copy_data(data, len, bufp, byte_cntr_data, >>> tmcdrvdata); >>> +} >> >> Could we not plug this into TMC-ETR read ? >> >> NAK for a special file approach. As Mike mentioned you need to make >> sure we are doing this safely. >> >> Suzuki >> >> >> >>> + >>> +/* Start the byte-cntr function when the path is enabled. */ >>> +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct >>> coresight_path *path) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> + struct coresight_device *sink = coresight_get_sink(path); >>> + struct ctcu_byte_cntr *byte_cntr_data; >>> + int port_num; >>> + >>> + if (!sink) >>> + return; >>> + >>> + port_num = ctcu_get_active_port(sink, csdev); >>> + if (port_num < 0) >>> + return; >>> + >>> + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; >>> + /* Don't start byte-cntr function when threshold is not set. */ >>> + if (!byte_cntr_data->thresh_val) >>> + return; >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + atomic_set(&byte_cntr_data->irq_cnt, 0); >>> + byte_cntr_data->sink = sink; >>> + byte_cntr_data->enable = true; >>> +} >>> + >>> +/* Stop the byte-cntr function when the path is disabled. */ >>> +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct >>> coresight_path *path) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> + struct coresight_device *sink = coresight_get_sink(path); >>> + struct ctcu_byte_cntr *byte_cntr_data; >>> + struct tmc_drvdata *tmcdrvdata; >>> + int port_num; >>> + >>> + if (!sink) >>> + return; >>> + >>> + port_num = ctcu_get_active_port(sink, csdev); >>> + if (port_num < 0) >>> + return; >>> + >>> + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; >>> + tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + /* Store the w_offset of the ETR buffer when stopping. */ >>> + byte_cntr_data->w_offset = tmc_get_rwp_offset(tmcdrvdata); >>> + atomic_set(&byte_cntr_data->irq_cnt, 0); >>> + byte_cntr_data->read_active = false; >>> + byte_cntr_data->enable = false; >>> + /* >>> + * Wakeup once to force the read function to read the remaining >>> + * data of the ETR buffer. >>> + */ >>> + wake_up(&byte_cntr_data->wq); >>> +} >>> + >>> +static int ctcu_byte_cntr_release(struct inode *in, struct file *fp) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data = fp->private_data; >>> + struct device *dev = &byte_cntr_data->sink->dev; >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + atomic_set(&byte_cntr_data->irq_cnt, 0); >>> + byte_cntr_data->read_active = false; >>> + disable_irq_wake(byte_cntr_data->byte_cntr_irq); >>> + dev_dbg(dev, "send data total size: %llu bytes, r_offset: %ld >>> w_offset: %ld\n", >>> + byte_cntr_data->total_size, byte_cntr_data->r_offset, >>> + byte_cntr_data->w_offset); >>> + >>> + return 0; >>> +} >>> + >>> +static int ctcu_byte_cntr_open(struct inode *in, struct file *fp) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data = container_of(in->i_cdev, >>> + struct ctcu_byte_cntr, c_dev); >>> + struct tmc_drvdata *tmcdrvdata; >>> + >>> + if (byte_cntr_data->read_active) >>> + return -EBUSY; >>> + >>> + if (!byte_cntr_data->thresh_val || !byte_cntr_data->sink || >>> + (coresight_get_mode(byte_cntr_data->sink) != CS_MODE_SYSFS)) >>> + return -EINVAL; >>> + >>> + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); >>> + enable_irq_wake(byte_cntr_data->byte_cntr_irq); >>> + fp->private_data = byte_cntr_data; >>> + nonseekable_open(in, fp); >>> + tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); >>> + /* >>> + * The original r_offset is the w_offset of the ETR buffer at the >>> + * start of the byte-cntr. >>> + */ >>> + byte_cntr_data->r_offset = tmc_get_rwp_offset(tmcdrvdata); >>> + byte_cntr_data->total_size = 0; >>> + byte_cntr_data->read_active = true; >>> + byte_cntr_data->enable = true; >>> + >>> + return 0; >>> +} >>> + >>> +static const struct file_operations byte_cntr_fops = { >>> + .owner = THIS_MODULE, >>> + .open = ctcu_byte_cntr_open, >>> + .read = ctcu_byte_cntr_read_etr_bytes, >>> + .release = ctcu_byte_cntr_release, >>> +}; >>> + >>> +static int ctcu_byte_cntr_register_chardev(struct ctcu_byte_cntr >>> *byte_cntr_data, >>> + int port_num) >>> +{ >>> + struct device *device; >>> + dev_t devt; >>> + int ret; >>> + >>> + cdev_init(&byte_cntr_data->c_dev, &byte_cntr_fops); >>> + devt = MKDEV(MAJOR(byte_cntr_base), MINOR(byte_cntr_base) + >>> port_num); >>> + ret = cdev_add(&byte_cntr_data->c_dev, devt, 1); >>> + if (ret < 0) >>> + return -ENOMEM; >>> + >>> + device = device_create(byte_cntr_class, NULL, devt, byte_cntr_data, >>> + byte_cntr_data->name); >>> + >>> + if (IS_ERR(device)) >>> + return -ENOMEM; >>> + >>> + return 0; >>> +} >>> + >>> +static void ctcu_byte_cntr_unregister_chardev(struct ctcu_drvdata >>> *drvdata) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data; >>> + int i; >>> + >>> + for (i = 0; i < ETR_MAX_NUM; i++) { >>> + byte_cntr_data = &drvdata->byte_cntr_data[i]; >>> + device_destroy(byte_cntr_class, byte_cntr_data->c_dev.dev); >>> + } >>> +} >>> + >>> +int ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata >>> *drvdata, int etr_num) >>> +{ >>> + struct ctcu_byte_cntr *byte_cntr_data; >>> + struct device_node *nd = dev->of_node; >>> + int byte_cntr_irq, ret, i; >>> + >>> + ret = alloc_chrdev_region(&byte_cntr_base, 0, ETR_MAX_NUM, >>> BYTE_CNTR_CLASS_STR); >>> + if (ret < 0) >>> + return -ENOMEM; >>> + >>> + byte_cntr_class = class_create(BYTE_CNTR_CLASS_STR); >>> + if (IS_ERR(byte_cntr_class)) { >>> + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); >>> + return -ENOMEM; >>> + } >>> + >>> + for (i = 0; i < etr_num; i++) { >>> + byte_cntr_data = &drvdata->byte_cntr_data[i]; >>> + byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data- >>> >irq_name); >>> + if (byte_cntr_irq < 0) { >>> + ret = byte_cntr_irq; >>> + goto err_exit; >>> + } >>> + >>> + ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, >>> + IRQF_TRIGGER_RISING | IRQF_SHARED, >>> + dev_name(dev), byte_cntr_data); >>> + if (ret) { >>> + dev_err(dev, "Failed to register IRQ for %s\n", >>> + byte_cntr_data->name); >>> + goto err_exit; >>> + } >>> + >>> + ret = ctcu_byte_cntr_register_chardev(byte_cntr_data, i); >>> + if (ret) { >>> + dev_err(dev, "Failed to register chardev for %s\n", >>> + byte_cntr_data->name); >>> + goto err_exit; >>> + } >>> + >>> + byte_cntr_data->byte_cntr_irq = byte_cntr_irq; >>> + atomic_set(&byte_cntr_data->irq_cnt, 0); >>> + init_waitqueue_head(&byte_cntr_data->wq); >>> + } >>> + >>> + return 0; >>> + >>> +err_exit: >>> + ctcu_byte_cntr_unregister_chardev(drvdata); >>> + class_destroy(byte_cntr_class); >>> + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); >>> + return ret; >>> +} >>> + >>> +void ctcu_byte_cntr_remove(struct ctcu_drvdata *drvdata) >>> +{ >>> + ctcu_byte_cntr_unregister_chardev(drvdata); >>> + class_destroy(byte_cntr_class); >>> + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); >>> +} >>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/ >>> drivers/hwtracing/coresight/coresight-ctcu-core.c >>> index da35d8b4d579..5782655a5f39 100644 >>> --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c >>> @@ -46,16 +46,24 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); >>> #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) >>> #define CTCU_ATID_REG_SIZE 0x10 >>> #define CTCU_ETR0_ATID0 0xf8 >>> +#define CTCU_ETR0_IRQCTRL 0x6c >>> #define CTCU_ETR1_ATID0 0x108 >>> +#define CTCU_ETR1_IRQCTRL 0x70 >>> static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { >>> { >>> - .atid_offset = CTCU_ETR0_ATID0, >>> - .port_num = 0, >>> + .atid_offset = CTCU_ETR0_ATID0, >>> + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, >>> + .irq_name = "etr0", >>> + .byte_cntr_name = "byte-cntr0", >>> + .port_num = 0, >>> }, >>> { >>> - .atid_offset = CTCU_ETR1_ATID0, >>> - .port_num = 1, >>> + .atid_offset = CTCU_ETR1_ATID0, >>> + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, >>> + .irq_name = "etr1", >>> + .byte_cntr_name = "byte-cntr1", >>> + .port_num = 1, >>> }, >>> }; >>> @@ -64,6 +72,69 @@ static const struct ctcu_config sa8775p_cfgs = { >>> .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), >>> }; >>> +static ssize_t byte_cntr_val_show(struct device *dev, struct >>> device_attribute *attr, >>> + char *buf) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + int i, len = 0; >>> + >>> + for (i = 0; i < ETR_MAX_NUM; i++) { >>> + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) >>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", >>> + drvdata->byte_cntr_data[i].thresh_val); >>> + } >>> + >>> + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); >>> + >>> + return len; >>> +} >>> + >>> +static ssize_t byte_cntr_val_store(struct device *dev, struct >>> device_attribute *attr, >>> + const char *buf, size_t size) >>> +{ >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> + u32 thresh_vals[ETR_MAX_NUM] = { 0 }; >>> + u32 irq_ctrl_offset; >>> + int num, i; >>> + >>> + num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); >>> + if (num <= 0 || num > ETR_MAX_NUM) >>> + return -EINVAL; >>> + >>> + /* Threshold 0 disables the interruption. */ >>> + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); >>> + for (i = 0; i < num; i++) { >>> + /* A small threshold will result in a large number of >>> interruptions */ >>> + if (thresh_vals[i] && thresh_vals[i] < 4096) >>> + return -EINVAL; >>> + >>> + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { >>> + drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i]; >>> + irq_ctrl_offset = drvdata- >>> >byte_cntr_data[i].irq_ctrl_offset; >>> + CS_UNLOCK(drvdata->base); >>> + writel_relaxed(thresh_vals[i], drvdata->base + >>> irq_ctrl_offset); >>> + CS_LOCK(drvdata->base); >>> + } >>> + } >>> + >>> + return size; >>> +} >>> +static DEVICE_ATTR_RW(byte_cntr_val); >>> + >>> +static struct attribute *ctcu_attrs[] = { >>> + &dev_attr_byte_cntr_val.attr, >>> + NULL, >>> +}; >>> + >>> +static struct attribute_group ctcu_attr_grp = { >>> + .attrs = ctcu_attrs, >>> +}; >>> + >>> +static const struct attribute_group *ctcu_attr_grps[] = { >>> + &ctcu_attr_grp, >>> + NULL, >>> +}; >>> + >>> static void ctcu_program_atid_register(struct ctcu_drvdata >>> *drvdata, u32 reg_offset, >>> u8 bit, bool enable) >>> { >>> @@ -122,7 +193,7 @@ static int __ctcu_set_etr_traceid(struct >>> coresight_device *csdev, u8 traceid, in >>> * Searching the sink device from helper's view in case there are >>> multiple helper devices >>> * connected to the sink device. >>> */ >>> -static int ctcu_get_active_port(struct coresight_device *sink, >>> struct coresight_device *helper) >>> +int ctcu_get_active_port(struct coresight_device *sink, struct >>> coresight_device *helper) >>> { >>> struct coresight_platform_data *pdata = helper->pdata; >>> int i; >>> @@ -160,6 +231,8 @@ static int ctcu_enable(struct coresight_device >>> *csdev, enum cs_mode mode, void * >>> { >>> struct coresight_path *path = (struct coresight_path *)data; >>> + ctcu_byte_cntr_start(csdev, path); >>> + >>> return ctcu_set_etr_traceid(csdev, path, true); >>> } >>> @@ -167,6 +240,8 @@ static int ctcu_disable(struct coresight_device >>> *csdev, void *data) >>> { >>> struct coresight_path *path = (struct coresight_path *)data; >>> + ctcu_byte_cntr_stop(csdev, path); >>> + >>> return ctcu_set_etr_traceid(csdev, path, false); >>> } >>> @@ -188,7 +263,7 @@ static int ctcu_probe(struct platform_device *pdev) >>> const struct ctcu_config *cfgs; >>> struct ctcu_drvdata *drvdata; >>> void __iomem *base; >>> - int i; >>> + int ret, i; >>> desc.name = coresight_alloc_device_name(&ctcu_devs, dev); >>> if (!desc.name) >>> @@ -217,7 +292,14 @@ static int ctcu_probe(struct platform_device *pdev) >>> for (i = 0; i < cfgs->num_etr_config; i++) { >>> etr_cfg = &cfgs->etr_cfgs[i]; >>> drvdata->atid_offset[i] = etr_cfg->atid_offset; >>> + drvdata->byte_cntr_data[i].irq_name = etr_cfg- >>> >irq_name; >>> + drvdata->byte_cntr_data[i].name = etr_cfg- >>> >byte_cntr_name; >>> + drvdata->byte_cntr_data[i].irq_ctrl_offset = >>> + etr_cfg->irq_ctrl_offset; >>> } >>> + ret = ctcu_byte_cntr_init(dev, drvdata, cfgs- >>> >num_etr_config); >>> + if (ret < 0) >>> + dev_warn(dev, "Byte cntr init failed\n"); >>> } >>> } >>> @@ -229,6 +311,7 @@ static int ctcu_probe(struct platform_device *pdev) >>> desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; >>> desc.pdata = pdata; >>> desc.dev = dev; >>> + desc.groups = ctcu_attr_grps; >>> desc.ops = &ctcu_ops; >>> desc.access = CSDEV_ACCESS_IOMEM(base); >>> @@ -247,6 +330,7 @@ static void ctcu_remove(struct platform_device >>> *pdev) >>> { >>> struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev); >>> + ctcu_byte_cntr_remove(drvdata); >>> coresight_unregister(drvdata->csdev); >>> } >>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/ >>> hwtracing/coresight/coresight-ctcu.h >>> index e9594c38dd91..e38535c91090 100644 >>> --- a/drivers/hwtracing/coresight/coresight-ctcu.h >>> +++ b/drivers/hwtracing/coresight/coresight-ctcu.h >>> @@ -5,6 +5,8 @@ >>> #ifndef _CORESIGHT_CTCU_H >>> #define _CORESIGHT_CTCU_H >>> +#include <linux/cdev.h> >>> + >>> #include "coresight-trace-id.h" >>> /* Maximum number of supported ETR devices for a single CTCU. */ >>> @@ -13,10 +15,16 @@ >>> /** >>> * struct ctcu_etr_config >>> * @atid_offset: offset to the ATID0 Register. >>> - * @port_num: in-port number of CTCU device that connected to >>> ETR. >>> + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. >>> + * @irq_name: IRQ name in dt node. >>> + * @byte_cntr_name: name of the byte cntr device node. >>> + * @port_num: in-port number of the CTCU device that >>> connected to ETR. >>> */ >>> struct ctcu_etr_config { >>> const u32 atid_offset; >>> + const u32 irq_ctrl_offset; >>> + const char *irq_name; >>> + const char *byte_cntr_name; >>> const u32 port_num; >>> }; >>> @@ -25,15 +33,64 @@ struct ctcu_config { >>> int num_etr_config; >>> }; >>> +/** >>> + * struct ctcu_byte_cntr >>> + * @c_dev: cdev for byte_cntr. >>> + * @sink csdev of sink device. >>> + * @enable: indicates that byte_cntr function is enabled or not. >>> + * @read_active: indicates that byte-cntr node is opened or not. >>> + * @thresh_val: threshold to trigger a interruption. >>> + * @total_size total size of transferred data. >>> + * @byte_cntr_irq: IRQ number. >>> + * @irq_cnt: IRQ count. >>> + * @wq: workqueue of reading ETR data. >>> + * @read_work: work of reading ETR data. >>> + * @spin_lock: spinlock of byte cntr data. >>> + * @r_offset: offset of the pointer where reading begins. >>> + * @w_offset: offset of the write pointer in the ETR buffer when >>> + * the byte cntr is stopped. >>> + * @irq_ctrl_offset: offset to the BYTECNTRVAL Register. >>> + * @name: the name of byte cntr device node. >>> + * @irq_name: IRQ name in DT. >>> + */ >>> +struct ctcu_byte_cntr { >>> + struct cdev c_dev; >>> + struct coresight_device *sink; >>> + bool enable; >>> + bool read_active; >>> + u32 thresh_val; >>> + u64 total_size; >>> + int byte_cntr_irq; >>> + atomic_t irq_cnt; >>> + wait_queue_head_t wq; >>> + struct work_struct read_work; >>> + raw_spinlock_t spin_lock; >>> + long r_offset; >>> + long w_offset; >>> + u32 irq_ctrl_offset; >>> + const char *name; >>> + const char *irq_name; >>> +}; >>> + >>> struct ctcu_drvdata { >>> void __iomem *base; >>> struct clk *apb_clk; >>> struct device *dev; >>> struct coresight_device *csdev; >>> + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; >>> raw_spinlock_t spin_lock; >>> u32 atid_offset[ETR_MAX_NUM]; >>> /* refcnt for each traceid of each sink */ >>> u8 traceid_refcnt[ETR_MAX_NUM] >>> [CORESIGHT_TRACE_ID_RES_TOP]; >>> }; >>> +/* Generic functions */ >>> +int ctcu_get_active_port(struct coresight_device *sink, struct >>> coresight_device *helper); >>> + >>> +/* Byte-cntr functions */ >>> +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct >>> coresight_path *path); >>> +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct >>> coresight_path *path); >>> +int ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata >>> *drvdata, int port_num); >>> +void ctcu_byte_cntr_remove(struct ctcu_drvdata *drvdata); >>> + >>> #endif >>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/ >>> drivers/hwtracing/coresight/coresight-tmc-etr.c >>> index ec636ab1fd75..5dc94e890927 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >>> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >>> @@ -1040,14 +1040,15 @@ static void tmc_free_etr_buf(struct etr_buf >>> *etr_buf) >>> * Returns: The size of the linear data available @pos, with *bufpp >>> * updated to point to the buffer. >>> */ >>> -static ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, >>> - u64 offset, size_t len, char **bufpp) >>> +ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, >>> + u64 offset, size_t len, char **bufpp) >>> { >>> /* Adjust the length to limit this transaction to end of buffer */ >>> len = (len < (etr_buf->size - offset)) ? len : etr_buf->size - >>> offset; >>> return etr_buf->ops->get_data(etr_buf, (u64)offset, len, bufpp); >>> } >>> +EXPORT_SYMBOL_GPL(tmc_etr_buf_get_data); >>> static inline s64 >>> tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset) >>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/ >>> hwtracing/coresight/coresight-tmc.h >>> index baedb4dcfc3f..2fc77fd4ea25 100644 >>> --- a/drivers/hwtracing/coresight/coresight-tmc.h >>> +++ b/drivers/hwtracing/coresight/coresight-tmc.h >>> @@ -443,5 +443,7 @@ struct etr_buf *tmc_etr_get_buffer(struct >>> coresight_device *csdev, >>> enum cs_mode mode, void *data); >>> extern const struct attribute_group coresight_etr_group; >>> long tmc_get_rwp_offset(struct tmc_drvdata *drvdata); >>> +ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, u64 offset, >>> size_t len, >>> + char **bufpp); >>> #endif >> >

3 months

Re: [PATCH v3 1/1] coresight: prevent deactivate active config while enabling the config

by Mike Leach

Hi, On Thu, 9 Jan 2025 at 17:20, Yeoreum Yun <yeoreum.yun(a)arm.com> wrote: > > While enable active config via cscfg_csdev_enable_active_config(), > active config could be deactivated via configfs' sysfs interface. > This could make UAF issue in below scenario: > > CPU0 CPU1 > (sysfs enable) load module > cscfg_load_config_sets() > activate config. // sysfs > (sys_active_cnt == 1) > ... > cscfg_csdev_enable_active_config() > lock(csdev->cscfg_csdev_lock) > // here load config activate by CPU1 > unlock(csdev->cscfg_csdev_lock) > > deactivate config // sysfs > (sys_activec_cnt == 0) > cscfg_unload_config_sets() > unload module > > // access to config_desc which freed > // while unloading module. > cfs_csdev_enable_config > > To address this, use cscfg_config_desc's active_cnt as a reference count > which will be holded when > - activate the config. > - enable the activated config. > and put the module reference when config_active_cnt == 0. > > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> > --- > from v2 to v3: > - add cscfg_config_desc_get()/put() (from Suzuki). > - remove sys_enable_cnt. > > from v1 to v2: > - modify commit message. > --- > .../hwtracing/coresight/coresight-config.h | 2 +- > .../coresight/coresight-etm4x-core.c | 3 + > .../hwtracing/coresight/coresight-syscfg.c | 55 ++++++++++++++----- > 3 files changed, 44 insertions(+), 16 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h > index b9ebc9fcfb7f..90fd937d3bd8 100644 > --- a/drivers/hwtracing/coresight/coresight-config.h > +++ b/drivers/hwtracing/coresight/coresight-config.h > @@ -228,7 +228,7 @@ struct cscfg_feature_csdev { > * @feats_csdev:references to the device features to enable. > */ > struct cscfg_config_csdev { > - const struct cscfg_config_desc *config_desc; > + struct cscfg_config_desc *config_desc; > struct coresight_device *csdev; > bool enabled; > struct list_head node; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 86893115df17..6218ef40acbc 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -986,6 +986,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) > smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); > > raw_spin_unlock(&drvdata->spinlock); > + > + cscfg_csdev_disable_active_config(csdev); > + > cpus_read_unlock(); > > /* > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index a70c1454b410..8766f72db33e 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -391,14 +391,17 @@ static void cscfg_owner_put(struct cscfg_load_owner_info *owner_info) > static void cscfg_remove_owned_csdev_configs(struct coresight_device *csdev, void *load_owner) > { > struct cscfg_config_csdev *config_csdev, *tmp; > + unsigned long flags; > > if (list_empty(&csdev->config_csdev_list)) > return; > > + raw_spin_lock_irqsave(&csdev->cscfg_csdev_lock, flags); > list_for_each_entry_safe(config_csdev, tmp, &csdev->config_csdev_list, node) { > if (config_csdev->config_desc->load_owner == load_owner) > list_del(&config_csdev->node); > } > + raw_spin_unlock_irqrestore(&csdev->cscfg_csdev_lock, flags); > } > > static void cscfg_remove_owned_csdev_features(struct coresight_device *csdev, void *load_owner) > @@ -867,6 +870,28 @@ void cscfg_csdev_reset_feats(struct coresight_device *csdev) > } > EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats); > > +static bool cscfg_config_desc_get(struct cscfg_config_desc *config_desc, bool enable) > +{ > + if (enable) > + return atomic_inc_not_zero(&config_desc->active_cnt); > + Not sure why we have an "enable" parameter here - it completely changes the meaning of the function - with no comment at the start. From where it is called it makes figuring out the logic confusing. Just keep the "get" functionality and drop the parameter & the nz check. > + /* when activate config */ > + > + /* must ensure that config cannot be unloaded in use */ > + if (cscfg_owner_get(config_desc->load_owner)) > + return false; > + > + atomic_inc(&config_desc->active_cnt); > + > + return true; > +} > + > +static void cscfg_config_desc_put(struct cscfg_config_desc *config_desc) > +{ > + if (!atomic_dec_return(&config_desc->active_cnt)) > + cscfg_owner_put(config_desc->load_owner); > +} > + > /* > * This activate configuration for either perf or sysfs. Perf can have multiple > * active configs, selected per event, sysfs is limited to one. > @@ -890,22 +915,17 @@ static int _cscfg_activate_config(unsigned long cfg_hash) > if (config_desc->available == false) > return -EBUSY; > > - /* must ensure that config cannot be unloaded in use */ > - err = cscfg_owner_get(config_desc->load_owner); > - if (err) > + if (!cscfg_config_desc_get(config_desc, false)) { Drop the false parameter here. > + err = -EINVAL; > break; > + } > + > /* > * increment the global active count - control changes to > * active configurations > */ > atomic_inc(&cscfg_mgr->sys_active_cnt); > > - /* > - * mark the descriptor as active so enable config on a > - * device instance will use it > - */ > - atomic_inc(&config_desc->active_cnt); > - > err = 0; > dev_dbg(cscfg_device(), "Activate config %s.\n", config_desc->name); > break; > @@ -920,9 +940,8 @@ static void _cscfg_deactivate_config(unsigned long cfg_hash) > > list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) { > if ((unsigned long)config_desc->event_ea->var == cfg_hash) { > - atomic_dec(&config_desc->active_cnt); > atomic_dec(&cscfg_mgr->sys_active_cnt); > - cscfg_owner_put(config_desc->load_owner); > + cscfg_config_desc_put(config_desc); > dev_dbg(cscfg_device(), "Deactivate config %s.\n", config_desc->name); > break; > } > @@ -1047,7 +1066,7 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > unsigned long cfg_hash, int preset) > { > struct cscfg_config_csdev *config_csdev_active = NULL, *config_csdev_item; > - const struct cscfg_config_desc *config_desc; > + struct cscfg_config_desc *config_desc; > unsigned long flags; > int err = 0; > > @@ -1062,8 +1081,8 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > raw_spin_lock_irqsave(&csdev->cscfg_csdev_lock, flags); > list_for_each_entry(config_csdev_item, &csdev->config_csdev_list, node) { > config_desc = config_csdev_item->config_desc; > - if ((atomic_read(&config_desc->active_cnt)) && > - ((unsigned long)config_desc->event_ea->var == cfg_hash)) { > + if (((unsigned long)config_desc->event_ea->var == cfg_hash) && > + cscfg_config_desc_get(config_desc, true)) { This obfuscates the logic of the comparisons without good reason. With the true parameter, the function does no "get" operation but just replicates the logic being replaced - checking the active_cnt is non-zero. Restore this to the original logic to make it readable again Regards Mike > config_csdev_active = config_csdev_item; > csdev->active_cscfg_ctxt = (void *)config_csdev_active; > break; > @@ -1097,7 +1116,11 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > err = -EBUSY; > raw_spin_unlock_irqrestore(&csdev->cscfg_csdev_lock, flags); > } > + > + if (err) > + cscfg_config_desc_put(config_desc); > } > + > return err; > } > EXPORT_SYMBOL_GPL(cscfg_csdev_enable_active_config); > @@ -1136,8 +1159,10 @@ void cscfg_csdev_disable_active_config(struct coresight_device *csdev) > raw_spin_unlock_irqrestore(&csdev->cscfg_csdev_lock, flags); > > /* true if there was an enabled active config */ > - if (config_csdev) > + if (config_csdev) { > cscfg_csdev_disable_config(config_csdev); > + cscfg_config_desc_put(config_csdev->config_desc); > + } > } > EXPORT_SYMBOL_GPL(cscfg_csdev_disable_active_config); > > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 months, 1 week

Re: [PATCH v1 3/4] coresight: ctcu: Enable byte-cntr for TMC ETR devices

by Suzuki K Poulose

On 10/03/2025 09:04, Jie Gan wrote: > The byte-cntr function provided by the CTCU device is used to transfer data > from the ETR buffer to the userspace. An interrupt is triggered if the data Why do we need a new device to transfer the data to userspace ? > size exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions and the read function > will read the data from the ETR buffer if the IRQ count is greater than 0. > Each successful read process will decrement the IRQ count by 1. Having an interrupt is good, but see below. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/Makefile | 2 +- > .../coresight/coresight-ctcu-byte-cntr.c | 339 ++++++++++++++++++ > .../hwtracing/coresight/coresight-ctcu-core.c | 96 ++++- > drivers/hwtracing/coresight/coresight-ctcu.h | 59 ++- > .../hwtracing/coresight/coresight-tmc-etr.c | 5 +- > drivers/hwtracing/coresight/coresight-tmc.h | 2 + > 6 files changed, 493 insertions(+), 10 deletions(-) > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 8e62c3150aeb..c90a06768a18 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -52,4 +52,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o > -coresight-ctcu-y := coresight-ctcu-core.o > +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > new file mode 100644 > index 000000000000..0d16385663f5 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > @@ -0,0 +1,339 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/coresight.h> > +#include <linux/device.h> > +#include <linux/dma-mapping.h> > +#include <linux/fs.h> > +#include <linux/interrupt.h> > +#include <linux/of_irq.h> > +#include <linux/property.h> > +#include <linux/uaccess.h> > + > +#include "coresight-ctcu.h" > +#include "coresight-priv.h" > +#include "coresight-tmc.h" > + > +#define BYTE_CNTR_CLASS_STR "byte-cntr-class" > + > +static struct class *byte_cntr_class; > +static dev_t byte_cntr_base; > + > +static irqreturn_t byte_cntr_handler(int irq, void *data) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data; > + > + atomic_inc(&byte_cntr_data->irq_cnt); > + wake_up(&byte_cntr_data->wq); > + > + return IRQ_HANDLED; > +} > + > +/* Read the data from ETR's DDR buffer. */ > +static void __ctcu_byte_cntr_read_etr_bytes(struct ctcu_byte_cntr *byte_cntr_data, > + size_t *len, char **bufp) > +{ > + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); > + size_t actual, bytes = byte_cntr_data->thresh_val; > + struct etr_buf *etr_buf = tmcdrvdata->sysfs_buf; > + long r_offset; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + r_offset = byte_cntr_data->r_offset; > + if (*len >= bytes) > + *len = bytes; > + else if ((r_offset % bytes) + *len > bytes) > + *len = bytes - (r_offset % bytes); > + > + actual = tmc_etr_buf_get_data(etr_buf, r_offset, *len, bufp); > + *len = actual; > + if (actual == bytes || (actual + r_offset) % bytes == 0) > + atomic_dec(&byte_cntr_data->irq_cnt); > +} > + How can you safely read the ETR data while it is running ? You should stop the ETR and then provide the data. You could potentially do things like split the ETR buffer into two halves and switch the half used by the ETR on interrupt and expose this to user. > +/* Flush the remaining data in the ETR buffer after the byte cntr has stopped. */ > +static ssize_t ctcu_flush_etr_buffer(struct ctcu_byte_cntr *byte_cntr_data, size_t len, > + char **bufpp) > +{ > + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); > + struct etr_buf *etr_buf = tmcdrvdata->sysfs_buf; > + ssize_t read_len = 0, remaining_len; > + long r_offset, w_offset; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + r_offset = byte_cntr_data->r_offset; > + w_offset = byte_cntr_data->w_offset; > + if (w_offset < r_offset) > + remaining_len = tmcdrvdata->size + w_offset - r_offset; > + else > + remaining_len = w_offset - r_offset; > + > + if (remaining_len > len) > + remaining_len = len; > + > + if (remaining_len > 0) > + read_len = tmc_etr_buf_get_data(etr_buf, r_offset, remaining_len, bufpp); > + > + return read_len; > +} > + > +static ssize_t ctcu_byte_cntr_copy_data(char __user *data, size_t len, char *bufp, > + struct ctcu_byte_cntr *byte_cntr_data, > + struct tmc_drvdata *tmcdrvdata) > +{ > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + if (copy_to_user(data, bufp, len)) > + return -EFAULT; > + > + byte_cntr_data->total_size += len; > + if (byte_cntr_data->r_offset + len >= tmcdrvdata->size) > + byte_cntr_data->r_offset = 0; > + else > + byte_cntr_data->r_offset += len; > + > + return len; > +} > + > +/* The read function for /dev/byte-cntr%d */ WHY ? WHY can't the data be exported by the existing /dev/tmc_etr* ? > +static ssize_t ctcu_byte_cntr_read_etr_bytes(struct file *fp, char __user *data, > + size_t len, loff_t *ppos) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = fp->private_data; > + struct tmc_drvdata *tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); > + char *bufp = NULL; > + ssize_t read_len; > + > + if (!data) > + return -EINVAL; > + > + /* > + * Flush the remaining data in the ETR buffer based on the write > + * offset of the ETR buffer when the byte cntr function has stopped. > + */ > + if (!byte_cntr_data->read_active || !byte_cntr_data->enable) { > + read_len = ctcu_flush_etr_buffer(byte_cntr_data, len, &bufp); > + if (read_len > 0) > + return ctcu_byte_cntr_copy_data(data, read_len, bufp, > + byte_cntr_data, tmcdrvdata); > + > + return -EINVAL; > + } > + > + if (!atomic_read(&byte_cntr_data->irq_cnt)) { > + if (wait_event_interruptible(byte_cntr_data->wq, > + atomic_read(&byte_cntr_data->irq_cnt) > 0 || > + !byte_cntr_data->enable)) > + return -ERESTARTSYS; > + } > + > + __ctcu_byte_cntr_read_etr_bytes(byte_cntr_data, &len, &bufp); > + > + return ctcu_byte_cntr_copy_data(data, len, bufp, byte_cntr_data, tmcdrvdata); > +} Could we not plug this into TMC-ETR read ? NAK for a special file approach. As Mike mentioned you need to make sure we are doing this safely. Suzuki > + > +/* Start the byte-cntr function when the path is enabled. */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + int port_num; > + > + if (!sink) > + return; > + > + port_num = ctcu_get_active_port(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + /* Don't start byte-cntr function when threshold is not set. */ > + if (!byte_cntr_data->thresh_val) > + return; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + atomic_set(&byte_cntr_data->irq_cnt, 0); > + byte_cntr_data->sink = sink; > + byte_cntr_data->enable = true; > +} > + > +/* Stop the byte-cntr function when the path is disabled. */ > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + struct tmc_drvdata *tmcdrvdata; > + int port_num; > + > + if (!sink) > + return; > + > + port_num = ctcu_get_active_port(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + /* Store the w_offset of the ETR buffer when stopping. */ > + byte_cntr_data->w_offset = tmc_get_rwp_offset(tmcdrvdata); > + atomic_set(&byte_cntr_data->irq_cnt, 0); > + byte_cntr_data->read_active = false; > + byte_cntr_data->enable = false; > + /* > + * Wakeup once to force the read function to read the remaining > + * data of the ETR buffer. > + */ > + wake_up(&byte_cntr_data->wq); > +} > + > +static int ctcu_byte_cntr_release(struct inode *in, struct file *fp) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = fp->private_data; > + struct device *dev = &byte_cntr_data->sink->dev; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + atomic_set(&byte_cntr_data->irq_cnt, 0); > + byte_cntr_data->read_active = false; > + disable_irq_wake(byte_cntr_data->byte_cntr_irq); > + dev_dbg(dev, "send data total size: %llu bytes, r_offset: %ld w_offset: %ld\n", > + byte_cntr_data->total_size, byte_cntr_data->r_offset, > + byte_cntr_data->w_offset); > + > + return 0; > +} > + > +static int ctcu_byte_cntr_open(struct inode *in, struct file *fp) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = container_of(in->i_cdev, > + struct ctcu_byte_cntr, c_dev); > + struct tmc_drvdata *tmcdrvdata; > + > + if (byte_cntr_data->read_active) > + return -EBUSY; > + > + if (!byte_cntr_data->thresh_val || !byte_cntr_data->sink || > + (coresight_get_mode(byte_cntr_data->sink) != CS_MODE_SYSFS)) > + return -EINVAL; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + enable_irq_wake(byte_cntr_data->byte_cntr_irq); > + fp->private_data = byte_cntr_data; > + nonseekable_open(in, fp); > + tmcdrvdata = dev_get_drvdata(byte_cntr_data->sink->dev.parent); > + /* > + * The original r_offset is the w_offset of the ETR buffer at the > + * start of the byte-cntr. > + */ > + byte_cntr_data->r_offset = tmc_get_rwp_offset(tmcdrvdata); > + byte_cntr_data->total_size = 0; > + byte_cntr_data->read_active = true; > + byte_cntr_data->enable = true; > + > + return 0; > +} > + > +static const struct file_operations byte_cntr_fops = { > + .owner = THIS_MODULE, > + .open = ctcu_byte_cntr_open, > + .read = ctcu_byte_cntr_read_etr_bytes, > + .release = ctcu_byte_cntr_release, > +}; > + > +static int ctcu_byte_cntr_register_chardev(struct ctcu_byte_cntr *byte_cntr_data, > + int port_num) > +{ > + struct device *device; > + dev_t devt; > + int ret; > + > + cdev_init(&byte_cntr_data->c_dev, &byte_cntr_fops); > + devt = MKDEV(MAJOR(byte_cntr_base), MINOR(byte_cntr_base) + port_num); > + ret = cdev_add(&byte_cntr_data->c_dev, devt, 1); > + if (ret < 0) > + return -ENOMEM; > + > + device = device_create(byte_cntr_class, NULL, devt, byte_cntr_data, > + byte_cntr_data->name); > + > + if (IS_ERR(device)) > + return -ENOMEM; > + > + return 0; > +} > + > +static void ctcu_byte_cntr_unregister_chardev(struct ctcu_drvdata *drvdata) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + int i; > + > + for (i = 0; i < ETR_MAX_NUM; i++) { > + byte_cntr_data = &drvdata->byte_cntr_data[i]; > + device_destroy(byte_cntr_class, byte_cntr_data->c_dev.dev); > + } > +} > + > +int ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct device_node *nd = dev->of_node; > + int byte_cntr_irq, ret, i; > + > + ret = alloc_chrdev_region(&byte_cntr_base, 0, ETR_MAX_NUM, BYTE_CNTR_CLASS_STR); > + if (ret < 0) > + return -ENOMEM; > + > + byte_cntr_class = class_create(BYTE_CNTR_CLASS_STR); > + if (IS_ERR(byte_cntr_class)) { > + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); > + return -ENOMEM; > + } > + > + for (i = 0; i < etr_num; i++) { > + byte_cntr_data = &drvdata->byte_cntr_data[i]; > + byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data->irq_name); > + if (byte_cntr_irq < 0) { > + ret = byte_cntr_irq; > + goto err_exit; > + } > + > + ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, > + IRQF_TRIGGER_RISING | IRQF_SHARED, > + dev_name(dev), byte_cntr_data); > + if (ret) { > + dev_err(dev, "Failed to register IRQ for %s\n", > + byte_cntr_data->name); > + goto err_exit; > + } > + > + ret = ctcu_byte_cntr_register_chardev(byte_cntr_data, i); > + if (ret) { > + dev_err(dev, "Failed to register chardev for %s\n", > + byte_cntr_data->name); > + goto err_exit; > + } > + > + byte_cntr_data->byte_cntr_irq = byte_cntr_irq; > + atomic_set(&byte_cntr_data->irq_cnt, 0); > + init_waitqueue_head(&byte_cntr_data->wq); > + } > + > + return 0; > + > +err_exit: > + ctcu_byte_cntr_unregister_chardev(drvdata); > + class_destroy(byte_cntr_class); > + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); > + return ret; > +} > + > +void ctcu_byte_cntr_remove(struct ctcu_drvdata *drvdata) > +{ > + ctcu_byte_cntr_unregister_chardev(drvdata); > + class_destroy(byte_cntr_class); > + unregister_chrdev_region(byte_cntr_base, ETR_MAX_NUM); > +} > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index da35d8b4d579..5782655a5f39 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -46,16 +46,24 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); > #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) > #define CTCU_ATID_REG_SIZE 0x10 > #define CTCU_ETR0_ATID0 0xf8 > +#define CTCU_ETR0_IRQCTRL 0x6c > #define CTCU_ETR1_ATID0 0x108 > +#define CTCU_ETR1_IRQCTRL 0x70 > > static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { > { > - .atid_offset = CTCU_ETR0_ATID0, > - .port_num = 0, > + .atid_offset = CTCU_ETR0_ATID0, > + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, > + .irq_name = "etr0", > + .byte_cntr_name = "byte-cntr0", > + .port_num = 0, > }, > { > - .atid_offset = CTCU_ETR1_ATID0, > - .port_num = 1, > + .atid_offset = CTCU_ETR1_ATID0, > + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, > + .irq_name = "etr1", > + .byte_cntr_name = "byte-cntr1", > + .port_num = 1, > }, > }; > > @@ -64,6 +72,69 @@ static const struct ctcu_config sa8775p_cfgs = { > .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), > }; > > +static ssize_t byte_cntr_val_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + int i, len = 0; > + > + for (i = 0; i < ETR_MAX_NUM; i++) { > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) > + len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", > + drvdata->byte_cntr_data[i].thresh_val); > + } > + > + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); > + > + return len; > +} > + > +static ssize_t byte_cntr_val_store(struct device *dev, struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 thresh_vals[ETR_MAX_NUM] = { 0 }; > + u32 irq_ctrl_offset; > + int num, i; > + > + num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); > + if (num <= 0 || num > ETR_MAX_NUM) > + return -EINVAL; > + > + /* Threshold 0 disables the interruption. */ > + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); > + for (i = 0; i < num; i++) { > + /* A small threshold will result in a large number of interruptions */ > + if (thresh_vals[i] && thresh_vals[i] < 4096) > + return -EINVAL; > + > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { > + drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i]; > + irq_ctrl_offset = drvdata->byte_cntr_data[i].irq_ctrl_offset; > + CS_UNLOCK(drvdata->base); > + writel_relaxed(thresh_vals[i], drvdata->base + irq_ctrl_offset); > + CS_LOCK(drvdata->base); > + } > + } > + > + return size; > +} > +static DEVICE_ATTR_RW(byte_cntr_val); > + > +static struct attribute *ctcu_attrs[] = { > + &dev_attr_byte_cntr_val.attr, > + NULL, > +}; > + > +static struct attribute_group ctcu_attr_grp = { > + .attrs = ctcu_attrs, > +}; > + > +static const struct attribute_group *ctcu_attr_grps[] = { > + &ctcu_attr_grp, > + NULL, > +}; > + > static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, > u8 bit, bool enable) > { > @@ -122,7 +193,7 @@ static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, in > * Searching the sink device from helper's view in case there are multiple helper devices > * connected to the sink device. > */ > -static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) > +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper) > { > struct coresight_platform_data *pdata = helper->pdata; > int i; > @@ -160,6 +231,8 @@ static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void * > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_start(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, true); > } > > @@ -167,6 +240,8 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_stop(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, false); > } > > @@ -188,7 +263,7 @@ static int ctcu_probe(struct platform_device *pdev) > const struct ctcu_config *cfgs; > struct ctcu_drvdata *drvdata; > void __iomem *base; > - int i; > + int ret, i; > > desc.name = coresight_alloc_device_name(&ctcu_devs, dev); > if (!desc.name) > @@ -217,7 +292,14 @@ static int ctcu_probe(struct platform_device *pdev) > for (i = 0; i < cfgs->num_etr_config; i++) { > etr_cfg = &cfgs->etr_cfgs[i]; > drvdata->atid_offset[i] = etr_cfg->atid_offset; > + drvdata->byte_cntr_data[i].irq_name = etr_cfg->irq_name; > + drvdata->byte_cntr_data[i].name = etr_cfg->byte_cntr_name; > + drvdata->byte_cntr_data[i].irq_ctrl_offset = > + etr_cfg->irq_ctrl_offset; > } > + ret = ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); > + if (ret < 0) > + dev_warn(dev, "Byte cntr init failed\n"); > } > } > > @@ -229,6 +311,7 @@ static int ctcu_probe(struct platform_device *pdev) > desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; > desc.pdata = pdata; > desc.dev = dev; > + desc.groups = ctcu_attr_grps; > desc.ops = &ctcu_ops; > desc.access = CSDEV_ACCESS_IOMEM(base); > > @@ -247,6 +330,7 @@ static void ctcu_remove(struct platform_device *pdev) > { > struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev); > > + ctcu_byte_cntr_remove(drvdata); > coresight_unregister(drvdata->csdev); > } > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h > index e9594c38dd91..e38535c91090 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu.h > +++ b/drivers/hwtracing/coresight/coresight-ctcu.h > @@ -5,6 +5,8 @@ > > #ifndef _CORESIGHT_CTCU_H > #define _CORESIGHT_CTCU_H > +#include <linux/cdev.h> > + > #include "coresight-trace-id.h" > > /* Maximum number of supported ETR devices for a single CTCU. */ > @@ -13,10 +15,16 @@ > /** > * struct ctcu_etr_config > * @atid_offset: offset to the ATID0 Register. > - * @port_num: in-port number of CTCU device that connected to ETR. > + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. > + * @irq_name: IRQ name in dt node. > + * @byte_cntr_name: name of the byte cntr device node. > + * @port_num: in-port number of the CTCU device that connected to ETR. > */ > struct ctcu_etr_config { > const u32 atid_offset; > + const u32 irq_ctrl_offset; > + const char *irq_name; > + const char *byte_cntr_name; > const u32 port_num; > }; > > @@ -25,15 +33,64 @@ struct ctcu_config { > int num_etr_config; > }; > > +/** > + * struct ctcu_byte_cntr > + * @c_dev: cdev for byte_cntr. > + * @sink csdev of sink device. > + * @enable: indicates that byte_cntr function is enabled or not. > + * @read_active: indicates that byte-cntr node is opened or not. > + * @thresh_val: threshold to trigger a interruption. > + * @total_size total size of transferred data. > + * @byte_cntr_irq: IRQ number. > + * @irq_cnt: IRQ count. > + * @wq: workqueue of reading ETR data. > + * @read_work: work of reading ETR data. > + * @spin_lock: spinlock of byte cntr data. > + * @r_offset: offset of the pointer where reading begins. > + * @w_offset: offset of the write pointer in the ETR buffer when > + * the byte cntr is stopped. > + * @irq_ctrl_offset: offset to the BYTECNTRVAL Register. > + * @name: the name of byte cntr device node. > + * @irq_name: IRQ name in DT. > + */ > +struct ctcu_byte_cntr { > + struct cdev c_dev; > + struct coresight_device *sink; > + bool enable; > + bool read_active; > + u32 thresh_val; > + u64 total_size; > + int byte_cntr_irq; > + atomic_t irq_cnt; > + wait_queue_head_t wq; > + struct work_struct read_work; > + raw_spinlock_t spin_lock; > + long r_offset; > + long w_offset; > + u32 irq_ctrl_offset; > + const char *name; > + const char *irq_name; > +}; > + > struct ctcu_drvdata { > void __iomem *base; > struct clk *apb_clk; > struct device *dev; > struct coresight_device *csdev; > + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; > raw_spinlock_t spin_lock; > u32 atid_offset[ETR_MAX_NUM]; > /* refcnt for each traceid of each sink */ > u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; > }; > > +/* Generic functions */ > +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper); > + > +/* Byte-cntr functions */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path); > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path); > +int ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num); > +void ctcu_byte_cntr_remove(struct ctcu_drvdata *drvdata); > + > #endif > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index ec636ab1fd75..5dc94e890927 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1040,14 +1040,15 @@ static void tmc_free_etr_buf(struct etr_buf *etr_buf) > * Returns: The size of the linear data available @pos, with *bufpp > * updated to point to the buffer. > */ > -static ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, > - u64 offset, size_t len, char **bufpp) > +ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, > + u64 offset, size_t len, char **bufpp) > { > /* Adjust the length to limit this transaction to end of buffer */ > len = (len < (etr_buf->size - offset)) ? len : etr_buf->size - offset; > > return etr_buf->ops->get_data(etr_buf, (u64)offset, len, bufpp); > } > +EXPORT_SYMBOL_GPL(tmc_etr_buf_get_data); > > static inline s64 > tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset) > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index baedb4dcfc3f..2fc77fd4ea25 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -443,5 +443,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, > enum cs_mode mode, void *data); > extern const struct attribute_group coresight_etr_group; > long tmc_get_rwp_offset(struct tmc_drvdata *drvdata); > +ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf, u64 offset, size_t len, > + char **bufpp); > > #endif

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