CoreSight

coresight@lists.linaro.org

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2521 discussions

by erin.mooney＠collaboratesuite.com

Hi, I just wanted to check if you would be interested in acquiring a contact list of Managed Service providers (MSPs) and Managed Security Service Providers (MSSPs) for your Marketing and Demand Generation program. *You might also be interested in other categories like*: · CSPs, ISPs, ISVs, VARS, SIs · Cyber Security Customers of Top Companies · Storage customers of Top Companies · Virtualization customers of Top Companies · Networking customers of Top Companies · Contact Center customers of Top Companies · CRM, ERP and HCM customers of Top Companies · Microsoft, Salesforce, AWS, Oracle, SAP, Cisco, IBM etc. Customers *Each contact comes with* Company name, Website, Contact name (First, Middle, Last), Title, Direct email address, Phone, Postal address, Industry, SIC codes, Employee size, Revenue size. Please let me know if this is something of interest to you so that I can provide you with further information. Warm regards, Erin Mooney| Go-To-Market Coordinator If you wish to not to receive further emails, change the subject line to Unsubscribe

5 years, 1 month

à Dellys, je vous propose d'investir dans villas et appartements à 30m de la plage.

by sales＠auresconsult.com

5 years, 1 month

Re: [PATCH v9 00/24] coresight: allow to build coresight as modules

by Tingwei Zhang

On Thu, Sep 10, 2020 at 04:45:52AM +0800, tsoni(a)codeaurora.org wrote: > On 2020-09-09 09:15, Mathieu Poirier wrote: > >On Wed, Sep 09, 2020 at 02:54:33AM +0000, Tingwei Zhang wrote: > >>On Wed, Sep 09, 2020 at 01:53:51AM +0800, Mathieu Poirier wrote: > >>> Hi Tingwei, > >>> > >>> Apologies for the untimely response to this set, I am hoping to get > to > >>> it in the next two weeks. > >>> > >> > >>It's fine, Mathieu. Please let me know your comments once you have time. > >>I'm targeting to get these set merged in 5.10 Kernel. > > > >From the above it is not clear if you want this set to be _in_ the 5.10 > >cycle > >or added to my list _during_ the 5.10 cycle, which would make it part of > >the > >5.11 cycle. In any case the latter seems more realistic. > > Tingwei can correct me here, but we prefer to have patches to be part of the > 5.10 release. It means they should get merged in Linus's tree in the next > merge window. Yes. The target is to merge this series into Linus's tree in 5.10 Kernel. Thanks, Tingwei > > ---Trilok Soni

5 years, 1 month

Re: [PATCH v9 00/24] coresight: allow to build coresight as modules

by Mathieu Poirier

On Wed, Sep 09, 2020 at 02:54:33AM +0000, Tingwei Zhang wrote: > On Wed, Sep 09, 2020 at 01:53:51AM +0800, Mathieu Poirier wrote: > > Hi Tingwei, > > > > Apologies for the untimely response to this set, I am hoping to get to > > it in the next two weeks. > > > > It's fine, Mathieu. Please let me know your comments once you have time. > I'm targeting to get these set merged in 5.10 Kernel. >From the above it is not clear if you want this set to be _in_ the 5.10 cycle or added to my list _during_ the 5.10 cycle, which would make it part of the 5.11 cycle. In any case the latter seems more realistic. > > > Thanks, > > Mathieu > > > > On Wed, 19 Aug 2020 at 23:47, Tingwei Zhang <tingwei(a)codeaurora.org> > > wrote: > > > > > > Allow to build coresight as modules. This gives developers the > > feasibility to > > > test their code without reboot. > > > > > > This series is based on below two series. > > > > > > - "coresight: allow to build components as modules" > > > https://lkml.org/lkml/2018/6/5/989 > > > - "coresight: make drivers modular" > > > https://lkml.org/lkml/2020/1/17/468 > > > > > > Change from v8: > > > Protect etmdrvdata[] by modifying it on relevant CPU (Mathieu and > > Suzuki) > > > Grab the device before allocating memory for the node (Mathieu) > > > Add author of coresight core driver (Mathieu) > > > > > > Change from v7: > > > Depends on below change for ETM hotplug (Sai) > > > > > https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash > > .ranjan(a)codeaurora.org/ > > > Add mutex lock to protect etmdrvdata[] (Suzuki) > > > Add helper function coresight_get_ref() (Suzuki) > > > Reorg replicator and funnel change. Use two patches to support these > > > two drivers. (Suzuki) > > > Add fix tag to "coresight: etm: perf: Fix warning caused by > > etm_setup_aux > > > failure" (Suzuki) > > > Update author of "coresight: cti: Fix bug clearing sysfs links on > > callback" > > > > > > Change from v6: > > > Correct module description for CATU (Mike) > > > Check ect_ret equals 0 and set ect_enabled flag (Mike) > > > Add Tested-by and Reviewed-by from Mike > > > > > > Change from v5: > > > Add below CTI clean up change from Mike into series > > > -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html > > > Increase module reference count when enabling CTI device (Mike) > > > > > > Change from v4: > > > Fix error handling in coresight_grab_devicei() (Greg) > > > Add coresight: cti: Fix remove sysfs link error from Mike > > > -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html > > > Move cti_remove_conn_xrefs() into cti_remove() (Mike) > > > Align patch subject to coresight: <component>: <description> (Mike) > > > > > > Change from v3: > > > Rebase to coresight-next (Mike and Mathieu) > > > Reorder try_get_module() (Suzuki) > > > Clean up etmdrvdata[] in device remote path (Mike) > > > Move cti_remove_conn_xrefs to cti_remove (Mike) > > > > > > Change from v2: > > > Rebase to 5.8-rc5. Export coresight_add_sysfs_link and > > > coresight_remove_sysfs_link > > > Fix one cut and paste error on MODULE_DESCRIPTION of CTI > > > > > > Change from v1: > > > Use try_module_get() to avoid module to be unloaded when device is used > > > in active trace session. (Mathieu P) > > > > > > Change from above two series. > > > This series adds the support to dynamically remove module when the > > device in > > > that module is enabled and used by some trace path. It disables all > > trace > > > paths with that device and release the trace path. > > > > > > Kim Phillips (8): > > > coresight: use IS_ENABLED for CONFIGs that may be modules > > > coresight: etm3x: allow etm3x to be built as a module > > > coresight: etm4x: allow etm4x to be built as a module > > > coresight: etb: allow etb to be built as a module > > > coresight: tpiu: allow tpiu to be built as a module > > > coresight: tmc: allow tmc to be built as a module > > > coresight: allow funnel driver to be built as module > > > coresight: allow replicator driver to be built as module > > > > > > Mian Yousaf Kaukab (2): > > > coresight: export global symbols > > > coresight: tmc-etr: add function to register catu ops > > > > > > Mike Leach (2): > > > coresight: cti: Fix remove sysfs link error > > > coresight: cti: Fix bug clearing sysfs links on callback > > > > > > Tingwei Zhang (12): > > > coresight: cpu_debug: add module name in Kconfig > > > coresight: cpu_debug: define MODULE_DEVICE_TABLE > > > coresight: add coresight prefix to barrier_pkt > > > coresight: add try_get_module() in coresight_grab_device() > > > coresight: stm: allow to build coresight-stm as a module > > > coresight: etm: perf: Fix warning caused by etm_setup_aux failure > > > coresight: cti: add function to register cti associate ops > > > coresight: cti: don't disable ect device if it's not enabled > > > coresight: cti: increase reference count when enabling cti > > > coresight: cti: allow cti to be built as a module > > > coresight: catu: allow catu drivers to be built as modules > > > coresight: allow the coresight core driver to be built as a module > > > > > > drivers/hwtracing/coresight/Kconfig | 54 ++++-- > > > drivers/hwtracing/coresight/Makefile | 22 +-- > > > drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- > > > drivers/hwtracing/coresight/coresight-catu.h | 2 - > > > .../{coresight.c => coresight-core.c} | 154 +++++++++++++++--- > > > .../hwtracing/coresight/coresight-cpu-debug.c | 2 + > > > .../{coresight-cti.c => coresight-cti-core.c} | 63 ++++++- > > > drivers/hwtracing/coresight/coresight-etb10.c | 28 +++- > > > .../hwtracing/coresight/coresight-etm-perf.c | 13 +- > > > .../hwtracing/coresight/coresight-etm-perf.h | 5 +- > > > ...resight-etm3x.c => coresight-etm3x-core.c} | 28 +++- > > > ...resight-etm4x.c => coresight-etm4x-core.c} | 84 +++++++--- > > > .../hwtracing/coresight/coresight-funnel.c | 64 +++++++- > > > .../hwtracing/coresight/coresight-platform.c | 1 + > > > drivers/hwtracing/coresight/coresight-priv.h | 24 ++- > > > .../coresight/coresight-replicator.c | 65 +++++++- > > > drivers/hwtracing/coresight/coresight-stm.c | 20 ++- > > > drivers/hwtracing/coresight/coresight-sysfs.c | 2 + > > > .../{coresight-tmc.c => coresight-tmc-core.c} | 25 ++- > > > .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- > > > .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- > > > drivers/hwtracing/coresight/coresight-tmc.h | 3 + > > > drivers/hwtracing/coresight/coresight-tpiu.c | 20 ++- > > > include/linux/coresight.h | 3 +- > > > 24 files changed, 634 insertions(+), 108 deletions(-) > > > rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} > > (92%) > > > rename drivers/hwtracing/coresight/{coresight-cti.c => > > coresight-cti-core.c} (94%) > > > rename drivers/hwtracing/coresight/{coresight-etm3x.c => > > coresight-etm3x-core.c} (97%) > > > rename drivers/hwtracing/coresight/{coresight-etm4x.c => > > coresight-etm4x-core.c} (96%) > > > rename drivers/hwtracing/coresight/{coresight-tmc.c => > > coresight-tmc-core.c} (95%) > > > > > > -- > > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora > > Forum, > > > a Linux Foundation Collaborative Project > > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel(a)lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

5 years, 1 month

Re: [PATCH] coresight: etm4x: fix issues on trcseqevr access

by Mathieu Poirier

Hi Mike, On Mon, 7 Sep 2020 at 10:52, Mike Leach <mike.leach(a)linaro.org> wrote: > > Hi, > > On Thu, 3 Sep 2020 at 18:42, Mathieu Poirier <mathieu.poirier(a)linaro.org> wrote: > > > > On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote: > > > The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid > > > accessing the reserved register. > > > > > > Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") > > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > > Cc: Mike Leach <mike.leach(a)linaro.org> > > > Cc: Shaokun Zhang <zhangshaokun(a)hisilicon.com> > > > Cc: lizixian(a)hisilicon.com > > > > > > Signed-off-by: Jonathan Zhou <jonathan.zhouwen(a)huawei.com> > > > --- > > > drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > > > index 96425e818fc2..44e44c817bf8 100644 > > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > > > @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > > > state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); > > > state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); > > > > > > - for (i = 0; i < drvdata->nrseqstate; i++) > > > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > > > state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); > > > > The section 3.4.3 "Guidelines for trace unit registers to be saved and restored" > > of the ETM4 Architecture Specification (ARM IHI0064F ID042818) is clear on the > > fact that registers TRCSEQEVR0-3 have to be taken into account when saving the > > I think this is a typo in the TRM. I'll ping the docs people in ARM. Did you get an answer from the document people? Is this really a typographical problem? Thanks, Mathieu > > > trace unit state. > > > > Looking @ the register descriptions for TRCSEQEVRn (7.3.63) in the > above document n=0-2. > The number of states is set by TRCIDR5.NUMSEQSTATE (7.3.35). This can > take the value 0 or 4. > If 4 then there are 3 TRCSEQEVR(n) registers - 0 to 2 - one for each > state transition. > > Thus this patch is correct in using nrseqstate - 1. > > Regards > > Mike > > > Thanks, > > Mathieu > > > > > > > > state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); > > > @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) > > > writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); > > > writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); > > > > > > - for (i = 0; i < drvdata->nrseqstate; i++) > > > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > > > writel_relaxed(state->trcseqevr[i], > > > drvdata->base + TRCSEQEVRn(i)); > > > -- > > > 1.9.1 > > > > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK

5 years, 1 month

[PATCH v9 00/24] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v8: Protect etmdrvdata[] by modifying it on relevant CPU (Mathieu and Suzuki) Grab the device before allocating memory for the node (Mathieu) Add author of coresight core driver (Mathieu) Change from v7: Depends on below change for ETM hotplug (Sai) https://lore.kernel.org/linux-arm-kernel/20200729051310.18436-1-saiprakash.… Add mutex lock to protect etmdrvdata[] (Suzuki) Add helper function coresight_get_ref() (Suzuki) Reorg replicator and funnel change. Use two patches to support these two drivers. (Suzuki) Add fix tag to "coresight: etm: perf: Fix warning caused by etm_setup_aux failure" (Suzuki) Update author of "coresight: cti: Fix bug clearing sysfs links on callback" Change from v6: Correct module description for CATU (Mike) Check ect_ret equals 0 and set ect_enabled flag (Mike) Add Tested-by and Reviewed-by from Mike Change from v5: Add below CTI clean up change from Mike into series -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Increase module reference count when enabling CTI device (Mike) Change from v4: Fix error handling in coresight_grab_devicei() (Greg) Add coresight: cti: Fix remove sysfs link error from Mike -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html Move cti_remove_conn_xrefs() into cti_remove() (Mike) Align patch subject to coresight: <component>: <description> (Mike) Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (8): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: etm3x: allow etm3x to be built as a module coresight: etm4x: allow etm4x to be built as a module coresight: etb: allow etb to be built as a module coresight: tpiu: allow tpiu to be built as a module coresight: tmc: allow tmc to be built as a module coresight: allow funnel driver to be built as module coresight: allow replicator driver to be built as module Mian Yousaf Kaukab (2): coresight: export global symbols coresight: tmc-etr: add function to register catu ops Mike Leach (2): coresight: cti: Fix remove sysfs link error coresight: cti: Fix bug clearing sysfs links on callback Tingwei Zhang (12): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() coresight: stm: allow to build coresight-stm as a module coresight: etm: perf: Fix warning caused by etm_setup_aux failure coresight: cti: add function to register cti associate ops coresight: cti: don't disable ect device if it's not enabled coresight: cti: increase reference count when enabling cti coresight: cti: allow cti to be built as a module coresight: catu: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 ++++-- drivers/hwtracing/coresight/Makefile | 22 +-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 154 +++++++++++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 63 ++++++- drivers/hwtracing/coresight/coresight-etb10.c | 28 +++- .../hwtracing/coresight/coresight-etm-perf.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 28 +++- ...resight-etm4x.c => coresight-etm4x-core.c} | 84 +++++++--- .../hwtracing/coresight/coresight-funnel.c | 64 +++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 24 ++- .../coresight/coresight-replicator.c | 65 +++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 25 ++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 20 ++- include/linux/coresight.h | 3 +- 24 files changed, 634 insertions(+), 108 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (92%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (96%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (95%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

5 years, 1 month

Payment Confirmed 9350DD892544

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5 years, 1 month

[PATCH v2] coresight: etm4x: Handle unreachable sink in perf mode

by Suzuki K Poulose

If the specified/hinted sink is not reachable from a subset of the CPUs, we could end up unable to trace the event on those CPUs. This is the best effort we could do until we support 1:1 configurations. Fail gracefully in such cases avoiding a WARN_ON, which can be easily triggered by the user on certain platforms (Arm N1SDP), with the following trace paths : CPU0 \ -- Funnel0 --> ETF0 --> / \ CPU1 \ MainFunnel CPU2 / \ / -- Funnel1 --> ETF1 --> / CPU1 $ perf record --per-thread -e cs_etm/@ETF0/u -- <app> could trigger the following WARNING, when the event is scheduled on CPU2. [10919.513250] ------------[ cut here ]------------ [10919.517861] WARNING: CPU: 2 PID: 24021 at drivers/hwtracing/coresight/coresight-etm-perf.c:316 etm_event_start+0xf8/0x100 ... [10919.564403] CPU: 2 PID: 24021 Comm: perf Not tainted 5.8.0+ #24 [10919.570308] pstate: 80400089 (Nzcv daIf +PAN -UAO BTYPE=--) [10919.575865] pc : etm_event_start+0xf8/0x100 [10919.580034] lr : etm_event_start+0x80/0x100 [10919.584202] sp : fffffe001932f940 [10919.587502] x29: fffffe001932f940 x28: fffffc834995f800 [10919.592799] x27: 0000000000000000 x26: fffffe0011f3ced0 [10919.598095] x25: fffffc837fce244c x24: fffffc837fce2448 [10919.603391] x23: 0000000000000002 x22: fffffc8353529c00 [10919.608688] x21: fffffc835bb31000 x20: 0000000000000000 [10919.613984] x19: fffffc837fcdcc70 x18: 0000000000000000 [10919.619281] x17: 0000000000000000 x16: 0000000000000000 [10919.624577] x15: 0000000000000000 x14: 00000000000009f8 [10919.629874] x13: 00000000000009f8 x12: 0000000000000018 [10919.635170] x11: 0000000000000000 x10: 0000000000000000 [10919.640467] x9 : fffffe00108cd168 x8 : 0000000000000000 [10919.645763] x7 : 0000000000000020 x6 : 0000000000000001 [10919.651059] x5 : 0000000000000002 x4 : 0000000000000001 [10919.656356] x3 : 0000000000000000 x2 : 0000000000000000 [10919.661652] x1 : fffffe836eb40000 x0 : 0000000000000000 [10919.666949] Call trace: [10919.669382] etm_event_start+0xf8/0x100 [10919.673203] etm_event_add+0x40/0x60 [10919.676765] event_sched_in.isra.134+0xcc/0x210 [10919.681281] merge_sched_in+0xb0/0x2a8 [10919.685017] visit_groups_merge.constprop.140+0x15c/0x4b8 [10919.690400] ctx_sched_in+0x15c/0x170 [10919.694048] perf_event_sched_in+0x6c/0xa0 [10919.698130] ctx_resched+0x60/0xa0 [10919.701517] perf_event_exec+0x288/0x2f0 [10919.705425] begin_new_exec+0x4c8/0xf58 [10919.709247] load_elf_binary+0x66c/0xf30 [10919.713155] exec_binprm+0x15c/0x450 [10919.716716] __do_execve_file+0x508/0x748 [10919.720711] __arm64_sys_execve+0x40/0x50 [10919.724707] do_el0_svc+0xf4/0x1b8 [10919.728095] el0_sync_handler+0xf8/0x124 [10919.732003] el0_sync+0x140/0x180 Even though we don't support using separate sinks for the ETMs yet (e.g, for 1:1 configurations), we should at least honor the user's choice and handle the limitations gracefully, by simply skipping the tracing on ETMs which can't reach the requested sink. Fixes: f9d81a657bb8 ("coresight: perf: Allow tracing on hotplugged CPUs") Reported-by: Jeremy Linton <jeremy.linton(a)arm.com> Tested-by: Jeremy Linton <jeremy.linton(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- Change since v1: - Updated the description, added Tested-by. - No code changes - Rebased on coresight/next --- drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 1a3169e69bb1..9d61a71da96f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -321,6 +321,16 @@ static void etm_event_start(struct perf_event *event, int flags) if (!event_data) goto fail; + /* + * Check if this ETM is allowed to trace, as decided + * at etm_setup_aux(). This could be due to an unreachable + * sink from this ETM. We can't do much in this case if + * the sink was specified or hinted to the driver. For + * now, simply don't record anything on this ETM. + */ + if (!cpumask_test_cpu(cpu, &event_data->mask)) + goto fail_end_stop; + path = etm_event_cpu_path(event_data, cpu); /* We need a sink, no need to continue without one */ sink = coresight_get_sink(path); -- 2.24.1

5 years, 2 months

[PATCH v2] coresight: cti: write regsiters directly in cti_enable_hw()

by Tingwei Zhang

Deadlock as below is triggered by one CPU holds drvdata->spinlock and calls cti_enable_hw(). Smp_call_function_single() is called in cti_enable_hw() and tries to let another CPU write CTI registers. That CPU is trying to get drvdata->spinlock in cti_cpu_pm_notify() and doesn't response to IPI from smp_call_function_single(). [ 988.335937] CPU: 6 PID: 10258 Comm: sh Tainted: G W L 5.8.0-rc6-mainline-16783-gc38daa79b26b-dirty #1 [ 988.346364] Hardware name: Thundercomm Dragonboard 845c (DT) [ 988.352073] pstate: 20400005 (nzCv daif +PAN -UAO BTYPE=--) [ 988.357689] pc : smp_call_function_single+0x158/0x1b8 [ 988.362782] lr : smp_call_function_single+0x124/0x1b8 ... [ 988.451638] Call trace: [ 988.454119] smp_call_function_single+0x158/0x1b8 [ 988.458866] cti_enable+0xb4/0xf8 [coresight_cti] [ 988.463618] coresight_control_assoc_ectdev+0x6c/0x128 [coresight] [ 988.469855] coresight_enable+0x1f0/0x364 [coresight] [ 988.474957] enable_source_store+0x5c/0x9c [coresight] [ 988.480140] dev_attr_store+0x14/0x28 [ 988.483839] sysfs_kf_write+0x38/0x4c [ 988.487532] kernfs_fop_write+0x1c0/0x2b0 [ 988.491585] vfs_write+0xfc/0x300 [ 988.494931] ksys_write+0x78/0xe0 [ 988.498283] __arm64_sys_write+0x18/0x20 [ 988.502240] el0_svc_common+0x98/0x160 [ 988.506024] do_el0_svc+0x78/0x80 [ 988.509377] el0_sync_handler+0xd4/0x270 [ 988.513337] el0_sync+0x164/0x180 This change write CTI registers directly in cti_enable_hw(). Config->hw_powered has been checked to be true with spinlock holded. CTI is powered and can be programmed until spinlock is released. Fixes: 6a0953ce7de9 ("coresight: cti: Add CPU idle pm notifer to CTI devices") Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> --- drivers/hwtracing/coresight/coresight-cti.c | 24 +++++---------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index c4e9cc7034ab..d04181c12a7f 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -86,22 +86,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) CS_LOCK(drvdata->base); } -static void cti_enable_hw_smp_call(void *info) -{ - struct cti_drvdata *drvdata = info; - - cti_write_all_hw_regs(drvdata); -} - /* write regs to hardware and enable */ static int cti_enable_hw(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; struct device *dev = &drvdata->csdev->dev; int rc = 0; + unsigned long flags; pm_runtime_get_sync(dev->parent); - spin_lock(&drvdata->spinlock); + spin_lock_irqsave(&drvdata->spinlock, flags); /* no need to do anything if enabled or unpowered*/ if (config->hw_enabled || !config->hw_powered) @@ -112,19 +106,11 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) if (rc) goto cti_err_not_enabled; - if (drvdata->ctidev.cpu >= 0) { - rc = smp_call_function_single(drvdata->ctidev.cpu, - cti_enable_hw_smp_call, - drvdata, 1); - if (rc) - goto cti_err_not_enabled; - } else { - cti_write_all_hw_regs(drvdata); - } + cti_write_all_hw_regs(drvdata); config->hw_enabled = true; atomic_inc(&drvdata->config.enable_req_count); - spin_unlock(&drvdata->spinlock); + spin_unlock_irqrestore(&drvdata->spinlock, flags); return rc; cti_state_unchanged: @@ -132,7 +118,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) /* cannot enable due to error */ cti_err_not_enabled: - spin_unlock(&drvdata->spinlock); + spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(dev->parent); return rc; } -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

5 years, 2 months

[PATCH] coresight: etm4x: Handle unreachable sink in perf mode

by Suzuki K Poulose

If the specified/hinted sink is not reachable from a subset of the CPUs, we could end up unable to trace the event on those CPUs. This is the best effort we could do until we support 1:1 configurations. Fail gracefully in such cases avoiding a WARN_ON, which can be easily triggered by the user on certain platforms, like : [10919.513250] ------------[ cut here ]------------ [10919.517861] WARNING: CPU: 2 PID: 24021 at drivers/hwtracing/coresight/coresight-etm-perf.c:316 etm_event_start+0xf8/0x100 ... [10919.564403] CPU: 2 PID: 24021 Comm: perf Not tainted 5.8.0+ #24 [10919.570308] pstate: 80400089 (Nzcv daIf +PAN -UAO BTYPE=--) [10919.575865] pc : etm_event_start+0xf8/0x100 [10919.580034] lr : etm_event_start+0x80/0x100 [10919.584202] sp : fffffe001932f940 [10919.587502] x29: fffffe001932f940 x28: fffffc834995f800 [10919.592799] x27: 0000000000000000 x26: fffffe0011f3ced0 [10919.598095] x25: fffffc837fce244c x24: fffffc837fce2448 [10919.603391] x23: 0000000000000002 x22: fffffc8353529c00 [10919.608688] x21: fffffc835bb31000 x20: 0000000000000000 [10919.613984] x19: fffffc837fcdcc70 x18: 0000000000000000 [10919.619281] x17: 0000000000000000 x16: 0000000000000000 [10919.624577] x15: 0000000000000000 x14: 00000000000009f8 [10919.629874] x13: 00000000000009f8 x12: 0000000000000018 [10919.635170] x11: 0000000000000000 x10: 0000000000000000 [10919.640467] x9 : fffffe00108cd168 x8 : 0000000000000000 [10919.645763] x7 : 0000000000000020 x6 : 0000000000000001 [10919.651059] x5 : 0000000000000002 x4 : 0000000000000001 [10919.656356] x3 : 0000000000000000 x2 : 0000000000000000 [10919.661652] x1 : fffffe836eb40000 x0 : 0000000000000000 [10919.666949] Call trace: [10919.669382] etm_event_start+0xf8/0x100 [10919.673203] etm_event_add+0x40/0x60 [10919.676765] event_sched_in.isra.134+0xcc/0x210 [10919.681281] merge_sched_in+0xb0/0x2a8 [10919.685017] visit_groups_merge.constprop.140+0x15c/0x4b8 [10919.690400] ctx_sched_in+0x15c/0x170 [10919.694048] perf_event_sched_in+0x6c/0xa0 [10919.698130] ctx_resched+0x60/0xa0 [10919.701517] perf_event_exec+0x288/0x2f0 [10919.705425] begin_new_exec+0x4c8/0xf58 [10919.709247] load_elf_binary+0x66c/0xf30 [10919.713155] exec_binprm+0x15c/0x450 [10919.716716] __do_execve_file+0x508/0x748 [10919.720711] __arm64_sys_execve+0x40/0x50 [10919.724707] do_el0_svc+0xf4/0x1b8 [10919.728095] el0_sync_handler+0xf8/0x124 [10919.732003] el0_sync+0x140/0x180 Fixes: f9d81a657bb8 ("coresight: perf: Allow tracing on hotplugged CPUs") Reported-by: Jeremy Linton <jeremy.linton(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 1a3169e69bb1..9d61a71da96f 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -321,6 +321,16 @@ static void etm_event_start(struct perf_event *event, int flags) if (!event_data) goto fail; + /* + * Check if this ETM is allowed to trace, as decided + * at etm_setup_aux(). This could be due to an unreachable + * sink from this ETM. We can't do much in this case if + * the sink was specified or hinted to the driver. For + * now, simply don't record anything on this ETM. + */ + if (!cpumask_test_cpu(cpu, &event_data->mask)) + goto fail_end_stop; + path = etm_event_cpu_path(event_data, cpu); /* We need a sink, no need to continue without one */ sink = coresight_get_sink(path); -- 2.24.1

5 years, 2 months

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