CoreSight

coresight@lists.linaro.org

2 participants
2521 discussions

by Cecylia Lazar

Bonjour Je contacte au nom du fabricant de savons, liquides et gels pour la désinfection des mains et les produits de nettoyage. Je voudrais vous offrir des produits de désinfection inodores qui nettoient et désinfectent efficacement la peau, éliminant les virus et les bactéries de vos mains. Les produits de désinfection sont destinés à un usage général et professionnel (hôpitaux, salles de traitement, laboratoires et autres). Nous proposons également des savons liquides efficaces avec une large gamme de parfums, gels douche, shampooings et revitalisants capillaires, et des détergents concentrés qui se distinguent sur le marché avec des performances élevées. Nos produits sont sans danger pour tous les types de peau, destinés à un usage quotidien, ils ne contiennent ni silicones ni parabènes. En raison du bon rapport qualité-prix, les cosmétiques et les produits de lavage sont très populaires sur les marchés européens. Puis-je présenter une offre? Cordialement Cecylia Lazar Responsable du développement commercial

5 years, 3 months

[PATCH v6 00/25] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v5: Add below CTI clean up change from Mike into series -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Increase module reference count when enabling CTI device (Mike) Change from v4: Fix error handling in coresight_grab_devicei() (Greg) Add coresight: cti: Fix remove sysfs link error from Mike -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html Move cti_remove_conn_xrefs() into cti_remove() (Mike) Align patch subject to coresight: <component>: <description> (Mike) Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (7): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: etm3x: allow etm3x to be built as a module coresight: etm4x: allow etm4x to be built as a module coresight: etb: allow etb to be built as a module coresight: tpiu: allow tpiu to be built as a module coresight: tmc: allow tmc to be built as a module coresight: allow funnel and replicator drivers to be built as modules Mian Yousaf Kaukab (4): coresight: export global symbols coresight: funnel: remove multiple init calls from funnel driver coresight: replicator: remove multiple init calls coresight: tmc-etr: add function to register catu ops Mike Leach (1): coresight: cti: Fix remove sysfs link error Tingwei Zhang (13): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() coresight: stm: allow to build coresight-stm as a module coresight: etm: perf: Fix warning caused by etm_setup_aux failure coresight: cti: add function to register cti associate ops coresight: cti: Fix bug clearing sysfs links on callback coresight: cti: don't disable ect device if it's not enabled coresight: cti: increase reference count when enabling cti coresight: cti: allow cti to be built as a module coresight: catu: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 +++++-- drivers/hwtracing/coresight/Makefile | 22 +-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 134 +++++++++++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 62 ++++++-- drivers/hwtracing/coresight/coresight-etb10.c | 22 ++- .../hwtracing/coresight/coresight-etm-perf.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 27 +++- ...resight-etm4x.c => coresight-etm4x-core.c} | 26 +++- .../hwtracing/coresight/coresight-funnel.c | 62 +++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 24 ++-- .../coresight/coresight-replicator.c | 63 +++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 19 ++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 19 ++- include/linux/coresight.h | 3 +- 24 files changed, 559 insertions(+), 86 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (93%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (98%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (96%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

5 years, 3 months

Open CSD trace

by Ajith Kurian Issac

Hi Mike, We are trying to make open CSD working in our silicon sample. It is very much required for our debug as we cannot attach DS5 early enough. We were able to generate the trace.bin and generate the trace decode file(attached) I have few questions [image: image.png] The end portion of teh trace looks something like this. I know PTM only takes the branch address. Is there any way we can make it more readable by filling the missing instructions between branches? or is this the final output. Also can you check the attached file and see if anything else is missing in our setup? Ajith K Issac Broadcom DCSG

5 years, 3 months

[PATCH] coresight: Make sysFS functional on topolgies with per core sink

by Linu Cherian

Coresight driver assumes sink is common across all the ETMs, and tries to build a path between ETM and the first enabled sink found using bus based search. This breaks implmentations that has multiple per core sinks in enabled state. For this, - coresight_find_sink API is updated with an additional flag so that it is able to return an enabled sink - coresight_get_enabled_sink API is updated to do a connection based search, when a source reference is given. Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- .../hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 5 +- drivers/hwtracing/coresight/coresight.c | 51 +++++++++++++++++-- 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 1a3169e69bb1..25041d2654e3 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -223,7 +223,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, id = (u32)event->attr.config2; sink = coresight_get_sink_by_id(id); } else { - sink = coresight_get_enabled_sink(true); + sink = coresight_get_enabled_sink(NULL, true); } mask = &event_data->mask; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index f2dc625ea585..010ed26db340 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -148,10 +148,13 @@ static inline void coresight_write_reg_pair(void __iomem *addr, u64 val, void coresight_disable_path(struct list_head *path); int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data); struct coresight_device *coresight_get_sink(struct list_head *path); -struct coresight_device *coresight_get_enabled_sink(bool reset); +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool reset); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * coresight_find_default_sink(struct coresight_device *csdev); +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev); struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e9c90f2de34a..ae69169c58d3 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -566,6 +566,10 @@ static int coresight_enabled_sink(struct device *dev, const void *data) /** * coresight_get_enabled_sink - returns the first enabled sink found on the bus + * When a source reference is given, enabled sink is found using connection based + * search. + * + * @source: Coresight source device reference * @deactivate: Whether the 'enable_sink' flag should be reset * * When operated from perf the deactivate parameter should be set to 'true'. @@ -576,10 +580,21 @@ static int coresight_enabled_sink(struct device *dev, const void *data) * parameter should be set to 'false', hence mandating users to explicitly * clear the flag. */ -struct coresight_device *coresight_get_enabled_sink(bool deactivate) +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool deactivate) { struct device *dev = NULL; + struct coresight_device *sink; + + if (!source) + goto bus_search; + sink = coresight_find_enabled_sink(source); + if (sink && deactivate) + sink->activated = false; + + return sink; +bus_search: dev = bus_find_device(&coresight_bustype, NULL, &deactivate, coresight_enabled_sink); @@ -828,6 +843,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * * @csdev: source / current device to check. * @depth: [in] search depth of calling dev, [out] depth of found sink. + * @enabled: flag to search only enabled sinks * * This will walk the connection path from a source (ETM) till a suitable * sink is encountered and return that sink to the original caller. @@ -839,7 +855,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * return best sink found, or NULL if not found at this node or child nodes. */ static struct coresight_device * -coresight_find_sink(struct coresight_device *csdev, int *depth) +coresight_find_sink(struct coresight_device *csdev, int *depth, bool enabled) { int i, curr_depth = *depth + 1, found_depth = 0; struct coresight_device *found_sink = NULL; @@ -862,7 +878,8 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) child_dev = csdev->pdata->conns[i].child_dev; if (child_dev) - sink = coresight_find_sink(child_dev, &child_depth); + sink = coresight_find_sink(child_dev, &child_depth, + enabled); if (sink) found_sink = coresight_select_best_sink(found_sink, @@ -872,6 +889,10 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) } return_def_sink: + /* Check if we need to return an enabled sink */ + if (enabled && found_sink) + if (!found_sink->activated) + found_sink = NULL; /* return found sink and depth */ if (found_sink) *depth = found_depth; @@ -901,10 +922,30 @@ coresight_find_default_sink(struct coresight_device *csdev) /* look for a default sink if we have not found for this device */ if (!csdev->def_sink) - csdev->def_sink = coresight_find_sink(csdev, &depth); + csdev->def_sink = coresight_find_sink(csdev, &depth, false); return csdev->def_sink; } +/** + * coresight_find_enabled_sink: Find the suitable enabled sink + * + * @csdev: starting source to find a connected sink. + * + * Walks connections graph looking for a suitable sink to enable for the + * supplied source. Uses CoreSight device subtypes and distance from source + * to select the best sink. + * + * Used in cases where the CoreSight user (sysfs) has selected a sink. + */ +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev) +{ + int depth = 0; + + /* look for the enabled sink */ + return coresight_find_sink(csdev, &depth, true); +} + static int coresight_remove_sink_ref(struct device *dev, void *data) { struct coresight_device *sink = data; @@ -992,7 +1033,7 @@ int coresight_enable(struct coresight_device *csdev) * Search for a valid sink for this session but don't reset the * "enable_sink" flag in sysFS. Users get to do that explicitly. */ - sink = coresight_get_enabled_sink(false); + sink = coresight_get_enabled_sink(csdev, false); if (!sink) { ret = -EINVAL; goto out; -- 2.25.1

5 years, 3 months

[PATCH 0/1] Fix issue with module unload and CTI cleanup

by Mike Leach

In the proposed Coresight module set v5 [1] from Tingwei, unloading the ETM module before the CTI module will crash on unload of the CTI module due to the cleanup callback from Coresight to the CTI module not working correctly in clearing sysfs callbacks. Patch fixes this issue. Applies on [1]. Tingwei - could you consider adding this to your set for v6? [1] https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Mike Leach (1): coresight: cti: Fix bug clearing sysfs links on callback drivers/hwtracing/coresight/coresight-core.c | 4 ++-- drivers/hwtracing/coresight/coresight-cti-core.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) -- 2.17.1

5 years, 3 months

[PATCHv2] coresight: etm4x: Fix etm4_count race by moving cpuhp callbacks to init

by Sai Prakash Ranjan

etm4_count keeps track of number of ETMv4 registered and on some systems, a race is observed on etm4_count variable which can lead to multiple calls to cpuhp_setup_state_nocalls_cpuslocked(). This function internally calls cpuhp_store_callbacks() which prevents multiple registrations of callbacks for a given state and due to this race, it returns -EBUSY leading to ETM probe failures like below. coresight-etm4x: probe of 7040000.etm failed with error -16 This race can easily be triggered with async probe by setting probe type as PROBE_PREFER_ASYNCHRONOUS and with ETM power management property "arm,coresight-loses-context-with-cpu". Prevent this race by moving cpuhp callbacks to etm driver init since the cpuhp callbacks doesn't have to depend on the etm4_count and can be once setup during driver init. Similarly we move cpu_pm notifier registration to driver init and completely remove etm4_count usage. Fixes: 9b6a3f3633a5 ("coresight: etmv4: Fix CPU power management setup in probe() function") Fixes: 58eb457be028 ("hwtracing/coresight-etm4x: Convert to hotplug state machine") Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> --- Changes in v2: * Rearrange cpuhp callbacks and move them to driver init (Suzuki K Poulose) --- drivers/hwtracing/coresight/coresight-etm4x.c | 51 ++++++++++--------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 6d7d2169bfb2..adb71987a1e3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -48,8 +48,6 @@ module_param(pm_save_enable, int, 0444); MODULE_PARM_DESC(pm_save_enable, "Save/restore state on power down: 1 = never, 2 = self-hosted"); -/* The number of ETMv4 currently registered */ -static int etm4_count; static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; static void etm4_set_default_config(struct etmv4_config *config); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, @@ -1403,12 +1401,9 @@ static int etm4_pm_setup_cpuslocked(void) { int ret; - if (etm4_count++) - return 0; - ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); if (ret) - goto reduce_count; + return ret; ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, "arm/coresight4:starting", @@ -1432,17 +1427,11 @@ static int etm4_pm_setup_cpuslocked(void) unregister_notifier: cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); - -reduce_count: - --etm4_count; return ret; } static void etm4_pm_clear(void) { - if (--etm4_count != 0) - return; - cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); if (hp_online) { @@ -1498,22 +1487,12 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; - cpus_read_lock(); etmdrvdata[drvdata->cpu] = drvdata; if (smp_call_function_single(drvdata->cpu, etm4_init_arch_data, drvdata, 1)) dev_err(dev, "ETM arch init failed\n"); - ret = etm4_pm_setup_cpuslocked(); - cpus_read_unlock(); - - /* etm4_pm_setup_cpuslocked() does its own cleanup - exit on error */ - if (ret) { - etmdrvdata[drvdata->cpu] = NULL; - return ret; - } - if (etm4_arch_supported(drvdata->arch) == false) { ret = -EINVAL; goto err_arch_supported; @@ -1560,7 +1539,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) err_arch_supported: etmdrvdata[drvdata->cpu] = NULL; - etm4_pm_clear(); return ret; } @@ -1598,4 +1576,29 @@ static struct amba_driver etm4x_driver = { .probe = etm4_probe, .id_table = etm4_ids, }; -builtin_amba_driver(etm4x_driver); + +static int __init etm4x_init(void) +{ + int ret; + + cpus_read_lock(); + ret = etm4_pm_setup_cpuslocked(); + cpus_read_unlock(); + + /* etm4_pm_setup_cpuslocked() does its own cleanup - exit on error */ + if (ret) + return ret; + + ret = amba_driver_register(&etm4x_driver); + if (ret) { + pr_info("Error registering etm4x driver\n"); + goto err_init; + } + + return ret; + +err_init: + etm4_pm_clear(); + return ret; +} +module_init(etm4x_init); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

5 years, 3 months

[PATCH v4 00/20] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (7): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: allow etm3x to be built as a module coresight: allow etm4x to be built as a module coresight: allow etb to be built as a module coresight: allow tpiu to be built as a module coresight: allow tmc to be built as a module coresight: allow funnel and replicator drivers to be built as modules Mian Yousaf Kaukab (4): coresight: export global symbols coresight: remove multiple init calls from funnel driver coresight: remove multiple init calls from replicator driver coresight: tmc-etr: add function to register catu ops Tingwei Zhang (9): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() allow to build coresight-stm as a module, for ease of development. coresight: cti: add function to register cti associate ops coresight: allow cti to be built as a module coresight: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 ++++++++-- drivers/hwtracing/coresight/Makefile | 22 ++-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 102 ++++++++++++++---- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 51 ++++++++- drivers/hwtracing/coresight/coresight-etb10.c | 22 +++- .../hwtracing/coresight/coresight-etm-perf.c | 9 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 27 ++++- ...resight-etm4x.c => coresight-etm4x-core.c} | 26 ++++- .../hwtracing/coresight/coresight-funnel.c | 62 ++++++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 24 ++--- .../coresight/coresight-replicator.c | 63 ++++++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 +++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 19 +++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 +++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 19 +++- include/linux/coresight.h | 2 +- 24 files changed, 520 insertions(+), 77 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (95%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (96%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (98%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (96%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

5 years, 3 months

COVID 19: Face Masks & Hand Sanitizer

by Rod Saif

Hello, PPE stock we can ship today from Los Angeles, CA. You can also send someone to inspect the stock or pick it up from Beverly Hills California. * Nitrile Gloves * KN95 (CDC EUI List FDA approved) * KN95 (FDA approved) * 3Ply Disposable Masks (Level 1, 2, 3 - Medical grade) * Contactless Thermometer * Hand Sanitizers For production run: * Isolation Gowns * Disposable Shoe Cover * Disposable Head Cover * Rapid Antibody Test Kits (FOB China) * Cotton Masks Let me know if we can get on a call, you can call us directly on 310 596 5555. We are FDA approved company (FDA number 3016649392) and PPAI. Thanks and stay safe, Rod Saif 310 596 5555 ppekits.net <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/d?c=8128568&l=c97…> PPE Kits by Dioz Group of Companies, Beverly Hills CA (PPAI/ FDA) Regards, -- Rod Saif | Director of Marketing Dioz Group | Oasis Apparel | Alanic | PPE KITS | Clean Health USA HQ: Beverly Hills, CA 90211, USA Web: www.diozgroup.com <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/d?c=8128568&l=e93…> Web: https://cleanhealthusa.com You may unsubscribe <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/u?u=2e22cc71-539b…> to stop receiving our emails.

5 years, 3 months

ETM probe failure since commit 9b6a3f3633a5cc9("coresight: etmv4: Fix CPU power management setup in probe() function")

by Sai Prakash Ranjan

Hi Mike, Since commit 9b6a3f3633a5cc9("coresight: etmv4: Fix CPU power management setup in probe() function"), ETM probe fails consistently like below: localhost ~ # dmesg | grep -i etm [ 6.460602] coresight-etm4x: probe of 7040000.etm failed with error -16 [ 6.524756] coresight etm1: CPU1: ETM v4.2 initialized [ 6.531152] coresight etm2: CPU2: ETM v4.2 initialized [ 6.538495] coresight etm3: CPU3: ETM v4.2 initialized [ 6.545124] coresight etm4: CPU4: ETM v4.2 initialized [ 6.552904] coresight etm5: CPU5: ETM v4.2 initialized [ 6.559714] coresight etm6: CPU6: ETM v4.2 initialized [ 6.569596] coresight etm7: CPU7: ETM v4.2 initialized localhost ~ # Most of the time its for ETM0 but I occasionally see ETM1 and other ETMs failing to probe, but the some ETM probe failure is always there. I'm using SC7180 based platform on 5.4 kernel which has all the coresight patches backported. If I revert that commit, I don't see the issue at all. In case you can identify something which might be causing this, please let me know. I'm planning to look into this as well in the meantime. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

5 years, 3 months

Invitation to Data analysis, modeling and simulation using excel Workshop

by FDC K

5 years, 3 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight