CoreSight

coresight@lists.linaro.org

6 participants
2565 discussions

by Mike Leach

Version 1.5.6 is now release. Contains build fixes and documentation upates Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

9 months, 1 week

[PATCH v7 0/2] coresight: Add label sysfs node support

by Mao Jinlong

With current design, the name of the non-cpu bounded coresight component is the device type with the number. And with 'ls' command we can get the register address of the component. But from these information, we can't know what the HW or system the component belongs to. Add label in DT and show the hw information by reading label sysfs node. cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0 tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1 tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2 /sys/bus/coresight/devices # cat cti*/label cti_dlct_0 cti_dlct_1 cti_apss_0 cti_apss_1 cti_apss_2 Change since V6: 1. Update the date and verison in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++++ .../sysfs-bus-coresight-devices-funnel | 6 ++++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++++ .../bindings/arm/arm,coresight-cti.yaml | 6 ++++ .../arm/arm,coresight-dummy-sink.yaml | 6 ++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++++ .../arm/arm,coresight-dynamic-funnel.yaml | 6 ++++ .../arm/arm,coresight-dynamic-replicator.yaml | 6 ++++ .../arm/arm,coresight-static-funnel.yaml | 6 ++++ .../arm/arm,coresight-static-replicator.yaml | 6 ++++ .../bindings/arm/arm,coresight-tmc.yaml | 6 ++++ .../bindings/arm/qcom,coresight-tpda.yaml | 6 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 6 ++++ drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++++++++++++++++++ 14 files changed, 110 insertions(+) -- 2.25.1

9 months, 1 week

Re: [PATCH v14 02/10] Coresight: Add trace_id function to retrieving the trace ID

by Suzuki K Poulose

On 26/02/2025 04:13, Jie Gan wrote: > Add 'trace_id' function pointer in coresight_ops. It's responsible for retrieving > the device's trace ID. > > Co-developed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: James Clark <james.clark(a)linaro.org> > Reviewed-by: James Clark <james.clark(a)linaro.org> > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-dummy.c | 13 ++++++++- > .../coresight/coresight-etm3x-core.c | 1 + > .../coresight/coresight-etm4x-core.c | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 11 ++++++++ > drivers/hwtracing/coresight/coresight-tpda.c | 11 ++++++++ > include/linux/coresight.h | 5 ++++ > 7 files changed, 68 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 0a9380350fb5..6cad777757f3 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -23,6 +23,7 @@ > #include "coresight-etm-perf.h" > #include "coresight-priv.h" > #include "coresight-syscfg.h" > +#include "coresight-trace-id.h" > > /* > * Mutex used to lock all sysfs enable and disable actions and loading and > @@ -1515,6 +1516,32 @@ void coresight_remove_driver(struct amba_driver *amba_drv, > } > EXPORT_SYMBOL_GPL(coresight_remove_driver); > > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink) > +{ > + int trace_id; > + int cpu = source_ops(csdev)->cpu_id(csdev); > + > + switch (mode) { > + case CS_MODE_SYSFS: > + trace_id = coresight_trace_id_get_cpu_id(cpu); > + break; > + case CS_MODE_PERF: Please could we handle a case where "sink" may be passed NULL ? if (WARN_ON(!sink)) return -EINVAL; Sorry, didn't spot that in the last review. Suzuki > + trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > + break; > + default: > + trace_id = -EINVAL; > + break; > + } > + > + if (!IS_VALID_CS_TRACE_ID(trace_id)) > + dev_err(&csdev->dev, > + "Failed to allocate trace ID on CPU%d\n", cpu); > + > + return trace_id; > +} > +EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id); > + > MODULE_LICENSE("GPL v2"); > MODULE_AUTHOR("Pratik Patel <pratikp(a)codeaurora.org>"); > MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier(a)linaro.org>"); > diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > index 9be53be8964b..b5692ba358c1 100644 > --- a/drivers/hwtracing/coresight/coresight-dummy.c > +++ b/drivers/hwtracing/coresight/coresight-dummy.c > @@ -41,6 +41,16 @@ static void dummy_source_disable(struct coresight_device *csdev, > dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); > } > > +static int dummy_source_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct dummy_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode mode, > void *data) > { > @@ -62,7 +72,8 @@ static const struct coresight_ops_source dummy_source_ops = { > }; > > static const struct coresight_ops dummy_source_cs_ops = { > - .source_ops = &dummy_source_ops, > + .trace_id = dummy_source_trace_id, > + .source_ops = &dummy_source_ops, > }; > > static const struct coresight_ops_sink dummy_sink_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index c103f4c70f5d..c1dda4bc4a2f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -704,6 +704,7 @@ static const struct coresight_ops_source etm_source_ops = { > }; > > static const struct coresight_ops etm_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 2c1a60577728..cfd116b87460 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1067,6 +1067,7 @@ static const struct coresight_ops_source etm4_source_ops = { > }; > > static const struct coresight_ops etm4_cs_ops = { > + .trace_id = coresight_etm_get_trace_id, > .source_ops = &etm4_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index b581a30a1cd9..aca25b5e3be2 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -281,12 +281,23 @@ static void stm_disable(struct coresight_device *csdev, > } > } > > +static int stm_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct stm_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static const struct coresight_ops_source stm_source_ops = { > .enable = stm_enable, > .disable = stm_disable, > }; > > static const struct coresight_ops stm_cs_ops = { > + .trace_id = stm_trace_id, > .source_ops = &stm_source_ops, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 189a4abc2561..68079169b11b 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -241,12 +241,23 @@ static void tpda_disable(struct coresight_device *csdev, > dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); > } > > +static int tpda_trace_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode, > + __maybe_unused struct coresight_device *sink) > +{ > + struct tpda_drvdata *drvdata; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->atid; > +} > + > static const struct coresight_ops_link tpda_link_ops = { > .enable = tpda_enable, > .disable = tpda_disable, > }; > > static const struct coresight_ops tpda_cs_ops = { > + .trace_id = tpda_trace_id, > .link_ops = &tpda_link_ops, > }; > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 157c4bd009a1..ce89ad24c2a2 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -335,6 +335,7 @@ enum cs_mode { > CS_MODE_PERF, > }; > > +#define coresight_ops(csdev) csdev->ops > #define source_ops(csdev) csdev->ops->source_ops > #define sink_ops(csdev) csdev->ops->sink_ops > #define link_ops(csdev) csdev->ops->link_ops > @@ -410,6 +411,8 @@ struct coresight_ops_helper { > }; > > struct coresight_ops { > + int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > const struct coresight_ops_sink *sink_ops; > const struct coresight_ops_link *link_ops; > const struct coresight_ops_source *source_ops; > @@ -697,4 +700,6 @@ int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, > > void coresight_remove_driver(struct amba_driver *amba_drv, > struct platform_driver *pdev_drv); > +int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, > + struct coresight_device *sink); > #endif /* _LINUX_COREISGHT_H */

9 months, 1 week

Re: [PATCH 1/2] dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg'

by Suzuki K Poulose

On Wed, 26 Feb 2025 12:29:13 +0100, Krzysztof Kozlowski wrote: > Binding listed variable number of IO addresses without defining them, > however example DTS code, all in-tree DTS and Linux kernel driver > mention only one address space, so drop the second to make binding > precise and correctly describe the hardware. > > Applied, thanks! [1/2] dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' https://git.kernel.org/coresight/c/d72deaf0 [2/2] dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' https://git.kernel.org/coresight/c/1e4e4542 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

9 months, 1 week

[PATCH v4 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Changes in V4: 1. Update the date and kernel verison in ABI file. 2. Update the year of copyright. Changes in V3: 1. Update the date in ABI file. 2. Remove the unrelated change. 3. Correct typo. 4. Move the CMB_CR related definitions together. Changes in V2: 1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) || tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support. 2. Embed mcmb_dataset struct into cmb struct. 3. Update the date and version in sysfs-bus-coresight-devices-tpdm Link: https://patchwork.kernel.org/project/linux-arm-msm/patch/20241105123940.396… Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 7 +- drivers/hwtracing/coresight/coresight-tpdm.c | 120 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++-- 4 files changed, 155 insertions(+), 20 deletions(-) -- 2.17.1

9 months, 1 week

Re: [PATCH v2 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition

by Yuanfang Zhang

On 2/26/2025 7:09 PM, Krzysztof Kozlowski wrote: > On 26/02/2025 12:05, Yuanfang Zhang wrote: >> + >> + compatible: >> + items: >> + - const: qcom,coresight-tnoc >> + - const: arm,primecell >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 >> + description: >> + Physical address space of the device. > Not much improved - still items are not listed. Which binding did you > choose as an example as I asked to? (so I can fix it) > qcom,coresight-tpda.yaml > Best regards, > Krzysztof

9 months, 1 week

Re: [PATCH 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition

by Yuanfang Zhang

On 2/20/2025 8:25 PM, Krzysztof Kozlowski wrote: > On 20/02/2025 10:41, Yuanfang Zhang wrote: >> Adds new coresight-tnoc.yaml file describing the bindings required >> to define Trace NOC in the device trees. >> >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> > > <form letter> > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. > > Tools like b4 or scripts/get_maintainer.pl provide you proper list of > people, so fix your workflow. Tools might also fail if you work on some > ancient tree (don't, instead use mainline) or work on fork of kernel > (don't, instead use mainline). Just use b4 and everything should be > fine, although remember about `b4 prep --auto-to-cc` if you added new > patches to the patchset. > > You missed at least devicetree list (maybe more), so this won't be > tested by automated tooling. Performing review on untested code might be > a waste of time. > > Please kindly resend and include all necessary To/Cc entries. > </form letter> > updated in https://lore.kernel.org/r/20250221-trace-noc-driver-v1-0-0a23fc643217@quici… >> --- >> .../bindings/arm/qcom,coresight-tnoc.yaml | 107 +++++++++++++++++++++ >> 1 file changed, 107 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..b8c1aaf014fb483fd960ec55d1193fb3f66136d2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml >> @@ -0,0 +1,107 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Ttrace NOC(Network On Chip) >> + >> +maintainers: >> + - yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> + >> +description: >> + The Trace NoC is an integration hierarchy which is a replacement of Dragonlink tile configuration. >> + It brings together debug component like TPDA, funnel and interconnect Trace Noc which collects trace > > Wrap according to coding style. > Done in V2. >> + from subsystems and transfers to QDSS sink. >> + >> + It sits in the different subsystem of SOC and aggregates the trace and transports it to Aggregation TNoC >> + or to QDSS trace sink eventually. Trace NoC embeds bridges for all the interfaces(APB, ATB, QPMDA & NTS). >> + >> + Trace NoC can take inputs from different trace sources i.e. ATB, QPMDA. >> + >> +# Need a custom select here or 'arm,primecell' will match on lots of nodes >> +select: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,coresight-tnoc >> + required: >> + - compatible >> + >> +properties: >> + $nodename: >> + pattern: "^tn(@[0-9a-f]+)$" >> + compatible: >> + items: >> + - const: qcom,coresight-tnoc >> + - const: arm,primecell >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 > > Look how existing bindings do it. You need to list and describe the items. > Done in V2. > Best regards, > Krzysztof

9 months, 1 week

Re: [PATCH 1/5] dt-bindings: arm: Add Coresight device Trace NOC definition

by Yuanfang Zhang

On 2/22/2025 6:47 PM, Krzysztof Kozlowski wrote: > On 21/02/2025 08:40, Yuanfang Zhang wrote: >> Adds new coresight-tnoc.yaml file describing the bindings required >> to define Trace NOC in the device trees. >> >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> > > > So you just sent the same v1, ignoring previous review. That's not how > it works. > sorry for this incorrect process. because i just update --to-cc list and no other change, i forced the version to V1, hoped it would work like resend, but the result was not as expected. > Provide proper changelog, implement ENTIRE feedback and do no ask > maintainers do point the same issues TWICE. > > NAK > > <form letter> > It seems my or other reviewer's previous comments were not fully > addressed. Maybe the feedback got lost between the quotes, maybe you > just forgot to apply it. Please go back to the previous discussion and > either implement all requested changes or keep discussing them. > > Thank you. > </form letter> > > Best regards, > Krzysztof >

9 months, 1 week

Re: [PATCH 2/5] coresight: add coresight Trace NOC driver

by Yuanfang Zhang

On 2/22/2025 6:54 PM, Krzysztof Kozlowski wrote: > On 21/02/2025 08:40, Yuanfang Zhang wrote: >> Add driver to support Coresight device Trace NOC(Network On Chip). >> Trace NOC is an integration hierarchy which is a replacement of >> Dragonlink configuration. It brings together debug components like >> TPDA, funnel and interconnect Trace Noc. >> >> It sits in the different subsystem of SOC and aggregates the trace >> and transports to QDSS trace bus. >> >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >> --- >> drivers/hwtracing/coresight/Kconfig | 10 ++ >> drivers/hwtracing/coresight/Makefile | 1 + >> drivers/hwtracing/coresight/coresight-tnoc.c | 191 +++++++++++++++++++++++++++ >> drivers/hwtracing/coresight/coresight-tnoc.h | 53 ++++++++ >> 4 files changed, 255 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig >> index 06f0a7594169c5f03ca5f893b7debd294587de78..712b2469e37610e6fc5f15cedb2535bf570f99aa 100644 >> --- a/drivers/hwtracing/coresight/Kconfig >> +++ b/drivers/hwtracing/coresight/Kconfig >> @@ -247,4 +247,14 @@ config CORESIGHT_DUMMY >> >> To compile this driver as a module, choose M here: the module will be >> called coresight-dummy. >> + >> +config CORESIGHT_TNOC >> + tristate "Coresight Trace Noc driver" >> + help >> + This driver provides support for Trace NoC component. >> + Trace NoC is a interconnect that is used to collect trace from >> + various subsystems and transport it QDSS trace sink.It sits in >> + the different tiles of SOC and aggregates the trace local to the >> + tile and transports it another tile or to QDSS trace sink eventually. >> + >> endif >> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile >> index 4ba478211b318ea5305f9f98dda40a041759f09f..ab1cff8f027495fabe3872d52f8c0877e39f0ea8 100644 >> --- a/drivers/hwtracing/coresight/Makefile >> +++ b/drivers/hwtracing/coresight/Makefile >> @@ -51,3 +51,4 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ >> coresight-cti-sysfs.o >> obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >> obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o >> +obj-$(CONFIG_CORESIGHT_TNOC) += coresight-tnoc.o > > Why do you keep adding entries to the end instead to some logically > ordered place? > > Dummy driver, before tpda (obviously tpda should go after tpdm) and now > this... This is just unnecessarily making simultaneous edits difficult. > sure, add it after funnel/replicator before etm, since it work as a link. >> diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c >> new file mode 100644 >> index 0000000000000000000000000000000000000000..11b9a7fd1efdc9fff7c1e9666bda14acb41786cb >> --- /dev/null >> +++ b/drivers/hwtracing/coresight/coresight-tnoc.c >> @@ -0,0 +1,191 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <linux/kernel.h> >> +#include <linux/module.h> >> +#include <linux/device.h> >> +#include <linux/platform_device.h> >> +#include <linux/amba/bus.h> >> +#include <linux/io.h> >> +#include <linux/coresight.h> >> +#include <linux/of.h> >> + >> +#include "coresight-priv.h" >> +#include "coresight-tnoc.h" >> +#include "coresight-trace-id.h" >> + > > >> + >> + drvdata->base = devm_ioremap_resource(dev, &adev->res); >> + if (!drvdata->base) >> + return -ENOMEM; >> + >> + spin_lock_init(&drvdata->spinlock); >> + >> + ret = trace_noc_init_default_data(drvdata); >> + if (ret) >> + return ret; >> + >> + desc.ops = &trace_noc_cs_ops; >> + desc.type = CORESIGHT_DEV_TYPE_LINK; >> + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; >> + desc.pdata = adev->dev.platform_data; >> + desc.dev = &adev->dev; >> + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); >> + drvdata->csdev = coresight_register(&desc); >> + if (IS_ERR(drvdata->csdev)) >> + return PTR_ERR(drvdata->csdev); >> + >> + pm_runtime_put(&adev->dev); >> + >> + dev_dbg(drvdata->dev, "Trace Noc initialized\n"); > > > Drop. There is really no need to tell that function finished. > > Please run standard kernel tools for static analysis, like coccinelle, > smatch and sparse, and fix reported warnings. Also please check for > warnings when building with W=1. Most of these commands (checks or W=1 > build) can build specific targets, like some directory, to narrow the > scope to only your code. The code here looks like it needs a fix. Feel > free to get in touch if the warning is not clear. > Done. > > Best regards, > Krzysztof >

9 months, 1 week

[PATCH v4] coresight-etm4x: add isb() before reading the TRCSTATR

by Yuanfang Zhang

As recommended by section 4.3.7 ("Synchronization when using system instructions to progrom the trace unit") of ARM IHI 0064H.b, the self-hosted trace analyzer must perform a Context synchronization event between writing to the TRCPRGCTLR and reading the TRCSTATR. Additionally, add an ISB between the each read of TRCSTATR on coresight_timeout() when using system instructions to program the trace unit. Fixes: 1ab3bb9df5e3 ("coresight: etm4x: Add necessary synchronization for sysreg access") Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-core.c | 20 ++++++--- drivers/hwtracing/coresight/coresight-etm4x-core.c | 48 +++++++++++++++++++--- include/linux/coresight.h | 4 ++ 3 files changed, 62 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index ea38ecf26fcbfb383eb40a222788bf5d7976013d..c42aa9fddab9b752361b84deab6b10be045b7104 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1017,18 +1017,20 @@ static void coresight_remove_conns(struct coresight_device *csdev) } /** - * coresight_timeout - loop until a bit has changed to a specific register - * state. + * coresight_timeout_action - loop until a bit has changed to a specific register + * state, with a callback after every trial. * @csa: coresight device access for the device * @offset: Offset of the register from the base of the device. * @position: the position of the bit of interest. * @value: the value the bit should have. + * @cb: Call back after each trial. * * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if * TIMEOUT_US has elapsed, which ever happens first. */ -int coresight_timeout(struct csdev_access *csa, u32 offset, - int position, int value) +int coresight_timeout_action(struct csdev_access *csa, u32 offset, + int position, int value, + coresight_timeout_cb_t cb) { int i; u32 val; @@ -1044,7 +1046,8 @@ int coresight_timeout(struct csdev_access *csa, u32 offset, if (!(val & BIT(position))) return 0; } - + if (cb) + cb(csa, offset, position, value); /* * Delay is arbitrary - the specification doesn't say how long * we are expected to wait. Extra check required to make sure @@ -1056,6 +1059,13 @@ int coresight_timeout(struct csdev_access *csa, u32 offset, return -EAGAIN; } +EXPORT_SYMBOL_GPL(coresight_timeout_action); + +int coresight_timeout(struct csdev_access *csa, u32 offset, + int position, int value) +{ + return coresight_timeout_action(csa, offset, position, value, NULL); +} EXPORT_SYMBOL_GPL(coresight_timeout); u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index dd8c74f893dbdfe1a35d811ef2dc476b81ce07ae..b933cdc4e52fd5ecd16d3ad97cf0d3f1a3fd87e4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -399,6 +399,29 @@ static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, } #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ +static void etm4x_sys_ins_barrier(struct csdev_access *csa, u32 offset, int pos, int val) +{ + if (!csa->io_mem) + isb(); +} + +/* + * etm4x_wait_status: Poll for TRCSTATR.<pos> == <val>. While using system + * instruction to access the trace unit, each access must be separated by a + * synchronization barrier. See ARM IHI0064H.b section "4.3.7 Synchronization of + * register updates", for system instructions section, in "Notes": + * + * "In particular, whenever disabling or enabling the trace unit, a poll of + * TRCSTATR needs explicit synchronization between each read of TRCSTATR" + */ +static int etm4x_wait_status(struct csdev_access *csa, int pos, int val) +{ + if (!csa->io_mem) + return coresight_timeout_action(csa, TRCSTATR, pos, val, + etm4x_sys_ins_barrier); + return coresight_timeout(csa, TRCSTATR, pos, val); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; @@ -430,7 +453,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); /* wait for TRCSTATR.IDLE to go up */ - if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) + if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); if (drvdata->nr_pe) @@ -523,7 +546,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); /* wait for TRCSTATR.IDLE to go back down to '0' */ - if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) + if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); @@ -906,10 +929,25 @@ static void etm4_disable_hw(void *info) tsb_csync(); etm4x_relaxed_write32(csa, control, TRCPRGCTLR); + /* + * As recommended by section 4.3.7 ("Synchronization when using system + * instructions to progrom the trace unit") of ARM IHI 0064H.b, the + * self-hosted trace analyzer must perform a Context synchronization + * event between writing to the TRCPRGCTLR and reading the TRCSTATR. + */ + if (!csa->io_mem) + isb(); + /* wait for TRCSTATR.PMSTABLE to go to '1' */ - if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) + if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for PM stable Trace Status\n"); + /* + * As recommended by section 4.3.7 (Synchronization of register updates) + * of ARM IHI 0064H.b. + */ + isb(); + /* read the status of the single shot comparators */ for (i = 0; i < drvdata->nr_ss_cmp; i++) { config->ss_status[i] = @@ -1711,7 +1749,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4_os_lock(drvdata); /* wait for TRCSTATR.PMSTABLE to go up */ - if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { + if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) { dev_err(etm_dev, "timeout while waiting for PM Stable Status\n"); etm4_os_unlock(drvdata); @@ -1802,7 +1840,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcpdcr = etm4x_read32(csa, TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ - if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { + if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) { dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); etm4_os_unlock(drvdata); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c1334259427850173ccc5872a6ced550a99f8e1c..f106b1025111892e9d44ac643f7409552952d4da 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -639,6 +639,10 @@ extern int coresight_enable_sysfs(struct coresight_device *csdev); extern void coresight_disable_sysfs(struct coresight_device *csdev); extern int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value); +typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int); +extern int coresight_timeout_action(struct csdev_access *csa, u32 offset, + int position, int value, + coresight_timeout_cb_t cb); extern int coresight_claim_device(struct coresight_device *csdev); extern int coresight_claim_device_unlocked(struct coresight_device *csdev); --- base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 change-id: 20250116-etm_sync-7be51cc6cbcd Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

9 months, 1 week

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