CoreSight

coresight@lists.linaro.org

4 participants
2500 discussions

Re: [PATCH 1/3] coresight: Don't save handle in path

by James Clark

On 06/02/2025 3:02 am, Jie Gan wrote: > > > On 2/1/2025 12:36 AM, James Clark wrote: >> Signed-off-by: James Clark <james.clark(a)linaro.org> >> --- >> drivers/hwtracing/coresight/coresight-core.c | 10 +++++----- >> drivers/hwtracing/coresight/coresight-dummy.c | 2 +- >> drivers/hwtracing/coresight/coresight-etb10.c | 8 +++----- >> drivers/hwtracing/coresight/coresight-etm-perf.c | 3 +-- >> drivers/hwtracing/coresight/coresight-priv.h | 4 ++-- >> drivers/hwtracing/coresight/coresight-sysfs.c | 2 +- >> drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 ++++----- >> drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +++++-------- >> drivers/hwtracing/coresight/coresight-tmc.h | 2 +- >> drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- >> drivers/hwtracing/coresight/coresight-trbe.c | 4 +--- >> drivers/hwtracing/coresight/ultrasoc-smb.c | 8 +++----- >> include/linux/coresight.h | 2 +- >> 13 files changed, 29 insertions(+), 40 deletions(-) >> > > Hi James > > I removed the handle from coresight_path and placed these codes in a > separate patch. However, I believe this change is not related to the > CTCU driver or coresight_path. Therefore, I suggest we submit it > independently. > > Thanks, > Jie > > Yeah if you've removed the handle from the path then we can do the other void* changes separately. Makes sense. >> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/ >> hwtracing/coresight/coresight-core.c >> index 11d5d5320b1a..253ef02fde12 100644 >> --- a/drivers/hwtracing/coresight/coresight-core.c >> +++ b/drivers/hwtracing/coresight/coresight-core.c >> @@ -272,9 +272,9 @@ void coresight_add_helper(struct coresight_device >> *csdev, >> EXPORT_SYMBOL_GPL(coresight_add_helper); >> static int coresight_enable_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> - return sink_ops(csdev)->enable(csdev, mode, data); >> + return sink_ops(csdev)->enable(csdev, mode, handle); >> } >> static void coresight_disable_sink(struct coresight_device *csdev) >> @@ -448,7 +448,8 @@ static int coresight_enable_helpers(struct >> coresight_device *csdev, >> return 0; >> } >> -int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode) >> +int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode, >> + struct perf_output_handle *handle) >> { >> int ret = 0; >> u32 type; >> @@ -479,7 +480,7 @@ int coresight_enable_path(struct coresight_path >> *cs_path, enum cs_mode mode) >> switch (type) { >> case CORESIGHT_DEV_TYPE_SINK: >> - ret = coresight_enable_sink(csdev, mode, cs_path); >> + ret = coresight_enable_sink(csdev, mode, handle); >> /* >> * Sink is the first component turned on. If we >> * failed to enable the sink, there are no components >> @@ -807,7 +808,6 @@ void coresight_release_path(struct coresight_path >> *cs_path) >> kfree(nd); >> } >> - cs_path->handle = NULL; >> kfree(cs_path->path); >> kfree(cs_path); >> } >> diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/ >> hwtracing/coresight/coresight-dummy.c >> index dfcf24e9c49a..6f86d33efef4 100644 >> --- a/drivers/hwtracing/coresight/coresight-dummy.c >> +++ b/drivers/hwtracing/coresight/coresight-dummy.c >> @@ -54,7 +54,7 @@ static int dummy_source_trace_id(struct >> coresight_device *csdev, enum cs_mode mo >> } >> static int dummy_sink_enable(struct coresight_device *csdev, enum >> cs_mode mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> dev_dbg(csdev->dev.parent, "Dummy sink enabled\n"); >> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/ >> hwtracing/coresight/coresight-etb10.c >> index 05430d8931d1..e373b0f590bf 100644 >> --- a/drivers/hwtracing/coresight/coresight-etb10.c >> +++ b/drivers/hwtracing/coresight/coresight-etb10.c >> @@ -167,14 +167,12 @@ static int etb_enable_sysfs(struct >> coresight_device *csdev) >> return ret; >> } >> -static int etb_enable_perf(struct coresight_device *csdev, void *data) >> +static int etb_enable_perf(struct coresight_device *csdev, struct >> perf_output_handle *handle) >> { >> int ret = 0; >> pid_t pid; >> unsigned long flags; >> struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -225,7 +223,7 @@ static int etb_enable_perf(struct coresight_device >> *csdev, void *data) >> } >> static int etb_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> int ret; >> @@ -234,7 +232,7 @@ static int etb_enable(struct coresight_device >> *csdev, enum cs_mode mode, >> ret = etb_enable_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = etb_enable_perf(csdev, data); >> + ret = etb_enable_perf(csdev, handle); >> break; >> default: >> ret = -EINVAL; >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/ >> drivers/hwtracing/coresight/coresight-etm-perf.c >> index b6765abb0a26..0fad9968c2c0 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >> @@ -501,9 +501,8 @@ static void etm_event_start(struct perf_event >> *event, int flags) >> if (WARN_ON_ONCE(!sink)) >> goto fail_end_stop; >> - cs_path->handle = handle; >> /* Nothing will happen without a path */ >> - if (coresight_enable_path(cs_path, CS_MODE_PERF)) >> + if (coresight_enable_path(cs_path, CS_MODE_PERF, handle)) >> goto fail_end_stop; >> /* Finally enable the tracer */ >> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/ >> hwtracing/coresight/coresight-priv.h >> index 8e02a222b9f8..7bd43304f461 100644 >> --- a/drivers/hwtracing/coresight/coresight-priv.h >> +++ b/drivers/hwtracing/coresight/coresight-priv.h >> @@ -112,7 +112,6 @@ struct cs_buffers { >> * @trace_id: trace_id of the whole path. >> */ >> struct coresight_path { >> - struct perf_output_handle *handle; >> struct list_head *path; >> u8 trace_id; >> }; >> @@ -142,7 +141,8 @@ static inline void CS_UNLOCK(void __iomem *addr) >> } >> void coresight_disable_path(struct coresight_path *cs_path); >> -int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode); >> +int coresight_enable_path(struct coresight_path *cs_path, enum >> cs_mode mode, >> + struct perf_output_handle *handle); >> struct coresight_device *coresight_get_sink(struct list_head *path); >> struct coresight_device *coresight_get_sink_by_id(u32 id); >> struct coresight_device * >> diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/ >> hwtracing/coresight/coresight-sysfs.c >> index 04e76cc1bfdf..f9a6b838726c 100644 >> --- a/drivers/hwtracing/coresight/coresight-sysfs.c >> +++ b/drivers/hwtracing/coresight/coresight-sysfs.c >> @@ -209,7 +209,7 @@ int coresight_enable_sysfs(struct coresight_device >> *csdev) >> goto out; >> } >> - ret = coresight_enable_path(cs_path, CS_MODE_SYSFS); >> + ret = coresight_enable_path(cs_path, CS_MODE_SYSFS, NULL); >> if (ret) >> goto err_path; >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/ >> drivers/hwtracing/coresight/coresight-tmc-etf.c >> index e6b07f917556..fdf1c2511d67 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> @@ -244,14 +244,13 @@ static int tmc_enable_etf_sink_sysfs(struct >> coresight_device *csdev) >> return ret; >> } >> -static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, >> void *data) >> +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, >> + struct perf_output_handle *handle) >> { >> int ret = 0; >> pid_t pid; >> unsigned long flags; >> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path= (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -303,7 +302,7 @@ static int tmc_enable_etf_sink_perf(struct >> coresight_device *csdev, void *data) >> } >> static int tmc_enable_etf_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> int ret; >> @@ -312,7 +311,7 @@ static int tmc_enable_etf_sink(struct >> coresight_device *csdev, >> ret = tmc_enable_etf_sink_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = tmc_enable_etf_sink_perf(csdev, data); >> + ret = tmc_enable_etf_sink_perf(csdev, handle); >> break; >> /* We shouldn't be here */ >> default: >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/ >> drivers/hwtracing/coresight/coresight-tmc-etr.c >> index 82a872882e24..2d0bd06bab2a 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >> @@ -1252,10 +1252,8 @@ static int tmc_enable_etr_sink_sysfs(struct >> coresight_device *csdev) >> } >> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct etr_perf_buffer *etr_perf; >> switch (mode) { >> @@ -1643,14 +1641,13 @@ tmc_update_etr_buffer(struct coresight_device >> *csdev, >> return size; >> } >> -static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, >> void *data) >> +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, >> + struct perf_output_handle *handle) >> { >> int rc = 0; >> pid_t pid; >> unsigned long flags; >> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); >> spin_lock_irqsave(&drvdata->spinlock, flags); >> @@ -1698,13 +1695,13 @@ static int tmc_enable_etr_sink_perf(struct >> coresight_device *csdev, void *data) >> } >> static int tmc_enable_etr_sink(struct coresight_device *csdev, >> - enum cs_mode mode, void *data) >> + enum cs_mode mode, struct perf_output_handle *handle) >> { >> switch (mode) { >> case CS_MODE_SYSFS: >> return tmc_enable_etr_sink_sysfs(csdev); >> case CS_MODE_PERF: >> - return tmc_enable_etr_sink_perf(csdev, data); >> + return tmc_enable_etr_sink_perf(csdev, handle); >> default: >> return -EINVAL; >> } >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/ >> hwtracing/coresight/coresight-tmc.h >> index 2671926be62a..e991afd43742 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc.h >> +++ b/drivers/hwtracing/coresight/coresight-tmc.h >> @@ -336,7 +336,7 @@ struct coresight_device >> *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); >> void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); >> void tmc_etr_remove_catu_ops(void); >> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, >> - enum cs_mode mode, void *data); >> + enum cs_mode mode, struct perf_output_handle >> *handle); >> extern const struct attribute_group coresight_etr_group; >> #endif >> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/ >> hwtracing/coresight/coresight-tpiu.c >> index 97ef36f03ec2..ccf463ac7bf5 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpiu.c >> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c >> @@ -75,7 +75,7 @@ static void tpiu_enable_hw(struct csdev_access *csa) >> } >> static int tpiu_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *__unused) >> + struct perf_output_handle *__unused) >> { >> struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/ >> hwtracing/coresight/coresight-trbe.c >> index 5005efd88a66..997d5976d2d2 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -1009,12 +1009,10 @@ static int __arm_trbe_enable(struct trbe_buf >> *buf, >> } >> static int arm_trbe_enable(struct coresight_device *csdev, enum >> cs_mode mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >> struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct trbe_buf *buf = etm_perf_sink_config(handle); >> WARN_ON(cpudata->cpu != smp_processor_id()); >> diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/ >> hwtracing/coresight/ultrasoc-smb.c >> index 9be88394b3bb..1574b5067206 100644 >> --- a/drivers/hwtracing/coresight/ultrasoc-smb.c >> +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c >> @@ -213,11 +213,9 @@ static void smb_enable_sysfs(struct >> coresight_device *csdev) >> coresight_set_mode(csdev, CS_MODE_SYSFS); >> } >> -static int smb_enable_perf(struct coresight_device *csdev, void *data) >> +static int smb_enable_perf(struct coresight_device *csdev, struct >> perf_output_handle *handle) >> { >> struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> - struct coresight_path *cs_path = (struct coresight_path *)data; >> - struct perf_output_handle *handle = cs_path->handle; >> struct cs_buffers *buf = etm_perf_sink_config(handle); >> pid_t pid; >> @@ -241,7 +239,7 @@ static int smb_enable_perf(struct coresight_device >> *csdev, void *data) >> } >> static int smb_enable(struct coresight_device *csdev, enum cs_mode >> mode, >> - void *data) >> + struct perf_output_handle *handle) >> { >> struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); >> int ret = 0; >> @@ -262,7 +260,7 @@ static int smb_enable(struct coresight_device >> *csdev, enum cs_mode mode, >> smb_enable_sysfs(csdev); >> break; >> case CS_MODE_PERF: >> - ret = smb_enable_perf(csdev, data); >> + ret = smb_enable_perf(csdev, handle); >> break; >> default: >> ret = -EINVAL; >> diff --git a/include/linux/coresight.h b/include/linux/coresight.h >> index 87f9baa7fefe..a859fc00eef9 100644 >> --- a/include/linux/coresight.h >> +++ b/include/linux/coresight.h >> @@ -353,7 +353,7 @@ enum cs_mode { >> */ >> struct coresight_ops_sink { >> int (*enable)(struct coresight_device *csdev, enum cs_mode mode, >> - void *data); >> + struct perf_output_handle *handle); >> int (*disable)(struct coresight_device *csdev); >> void *(*alloc_buffer)(struct coresight_device *csdev, >> struct perf_event *event, void **pages, >

8 months, 1 week

[PATCH] coresight-tmc: stop disabling tmc when flush timeout

by Yuanfang Zhang

When multiple ETMs are enabled simultaneously, the time required to complete a flush in the process of reading the TMC device node may exceed the default wait time of 100us. If the TMC capture is stopped while any ETM has not completed its flush, it can cause the corresponding CPU to hang. Fix the by checking the TMCReady bit after the flush. If TMCReady bit is set, TraceCaptEn bit can be clear; otherwise, return directly and stop the TMC read. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++----- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63ebdbed6719133 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) return; } -static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); + + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) tmc_disable_hw(drvdata); CS_LOCK(drvdata->base); + return 0; } static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) @@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) ret = -EINVAL; goto out; } - __tmc_etb_disable_hw(drvdata); + ret = __tmc_etb_disable_hw(drvdata); + if (ret) + goto out; } drvdata->reading = true; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53dce4d82842bec3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata) } } -static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { + int rc; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); + + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to disable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) tmc_disable_hw(drvdata); CS_LOCK(drvdata->base); - + return 0; } void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) @@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) } /* Disable the TMC if we are trying to read from a running session. */ - if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) - __tmc_etr_disable_hw(drvdata); - + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) { + ret = __tmc_etr_disable_hw(drvdata); + if (ret) + goto out; + } drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); --- base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 change-id: 20250103-fix_cpu_hung-b5a95179ada4 Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

8 months, 1 week

Re: [RFC v2 08/38] ABI: sysfs-bus-coresight-*: fix kernelversion tags

by Suzuki K Poulose

On 28/01/2025 00:05, Mauro Carvalho Chehab wrote: > Some kernelversion tags are missing colons. Add them to comply with > ABI description and produce right results when converted to html/pdf. > > Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei(a)kernel.org> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > .../testing/sysfs-bus-coresight-devices-cti | 78 +++++++++---------- > .../testing/sysfs-bus-coresight-devices-tpdm | 52 ++++++------- > 2 files changed, 65 insertions(+), 65 deletions(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > index bf2869c413e7..a97b70f588da 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti > @@ -1,241 +1,241 @@ > What: /sys/bus/coresight/devices/<cti-name>/enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable/Disable the CTI hardware. > > What: /sys/bus/coresight/devices/<cti-name>/powered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Indicate if the CTI hardware is powered. > > What: /sys/bus/coresight/devices/<cti-name>/ctmid > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Display the associated CTM ID > > What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Number of devices connected to triggers on this CTI > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Name of connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Input trigger signals from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the input trigger signals > from connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Output trigger signals to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Functional types for the output trigger signals > to connected device <N> > > What: /sys/bus/coresight/devices/<cti-name>/regs/inout_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Select the index for inen and outen registers. > > What: /sys/bus/coresight/devices/<cti-name>/regs/inen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIINEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/outen > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write the CTIOUTEN register selected by inout_sel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/gate > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write CTIGATE register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/asicctl > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Read or write ASICCTL register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/intack > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write the INTACK register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Set CTIAPPSET register to activate channel. Read back to > determine current value of register. > > What: /sys/bus/coresight/devices/<cti-name>/regs/appclear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPCLEAR register to deactivate channel. > > What: /sys/bus/coresight/devices/<cti-name>/regs/apppulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Write APPPULSE to pulse a channel active for one clock > cycle. > > What: /sys/bus/coresight/devices/<cti-name>/regs/chinstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read current status of channel inputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/choutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of channel outputs. > > What: /sys/bus/coresight/devices/<cti-name>/regs/triginstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of input trigger signals > > What: /sys/bus/coresight/devices/<cti-name>/regs/trigoutstatus > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) read current status of output trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI input trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI input trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_attach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Attach a CTI output trigger to a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_detach > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Detach a CTI output trigger from a CTM channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable CTIGATE for single channel (Write) or list enabled > channels through the gate (R). > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_disable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Disable CTIGATE for single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_set > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Activate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_clear > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Deactivate a single channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_pulse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Pulse a single channel - activate for a single clock cycle. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_filtered > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) List of output triggers filtered across all connections. > > What: /sys/bus/coresight/devices/<cti-name>/channels/trig_filter_enable > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Enable or disable trigger output signal filtering. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_inuse > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with at least one attached trigger signal. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_free > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) show channels with no attached trigger signals. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_sel > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (RW) Write channel number to select a channel to view, read to > see selected channel number. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_in > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see input triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_out > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Read) Read to see output triggers connected to selected view > channel. > > What: /sys/bus/coresight/devices/<cti-name>/channels/chan_xtrigs_reset > Date: March 2020 > -KernelVersion 5.7 > +KernelVersion: 5.7 > Contact: Mike Leach or Mathieu Poirier > Description: (Write) Clear all channel / trigger programming. > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index bf710ea6e0ef..53cb454b60d0 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -1,6 +1,6 @@ > What: /sys/bus/coresight/devices/<tpdm-name>/integration_test > Date: January 2023 > -KernelVersion 6.2 > +KernelVersion: 6.2 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Run integration test for tpdm. Integration test > @@ -14,7 +14,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Reset the dataset of the tpdm. > @@ -24,7 +24,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger type of the DSB for tpdm. > @@ -35,7 +35,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the DSB for tpdm. > @@ -46,7 +46,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the programming mode of the DSB for tpdm. > @@ -60,7 +60,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the index number of the edge detection for the DSB > @@ -69,7 +69,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to control the edge detection corresponding to > @@ -85,7 +85,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Write a data to mask the edge detection corresponding to the index > @@ -97,21 +97,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control value of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > Read a set of the edge control mask of the DSB in TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the DSB > @@ -119,7 +119,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the DSB > @@ -127,21 +127,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of DSB tpdm. Read > @@ -153,7 +153,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern type of DSB tpdm. Read > @@ -165,7 +165,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] > Date: March 2023 > -KernelVersion 6.7 > +KernelVersion: 6.7 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the DSB subunit > @@ -173,7 +173,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: (Write) Set the data collection mode of CMB tpdm. Continuous > change creates CMB data set elements on every CMBCLK edge. > @@ -187,7 +187,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the trigger pattern for the CMB > @@ -195,7 +195,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the trigger pattern for the CMB > @@ -203,21 +203,21 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the value of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the mask of the pattern for the CMB subunit TPDM. > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (Write) Set the pattern timestamp of CMB tpdm. Read > @@ -229,7 +229,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the trigger timestamp of the CMB for tpdm. > @@ -240,7 +240,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Read or write the status of timestamp upon all interface. > @@ -252,7 +252,7 @@ Description: > > What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31] > Date: January 2024 > -KernelVersion 6.9 > +KernelVersion: 6.9 > Contact: Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC) <quic_taozha(a)quicinc.com> > Description: > (RW) Set/Get the MSR(mux select register) for the CMB subunit

8 months, 1 week

Re: [PATCH v9 3/6] Coresight: Introduce a new struct coresight_path

by James Clark

8 months, 2 weeks

[PATCH 0/3] coresight: Alloc trace ID after building the path

by James Clark

Proof of concept to support CTCU device. Applies to Jie's patchset in the parent email. I think this would be a good simplification, it removes some code and makes things a bit clearer, and works for both the old and new CTCU requirements. It will require merging into the parent patchset somehow as it undoes some of those changes. James Clark (3): coresight: Don't save handle in path coresight: Export coresight_get_sink() coresight: Alloc trace ID after building the path drivers/hwtracing/coresight/coresight-core.c | 107 +++++++++++++----- drivers/hwtracing/coresight/coresight-dummy.c | 9 +- drivers/hwtracing/coresight/coresight-etb10.c | 8 +- .../hwtracing/coresight/coresight-etm-perf.c | 20 ++-- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 84 ++------------ .../coresight/coresight-etm3x-sysfs.c | 3 +- .../coresight/coresight-etm4x-core.c | 83 ++------------ .../coresight/coresight-etm4x-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x.h | 1 - drivers/hwtracing/coresight/coresight-priv.h | 17 +-- drivers/hwtracing/coresight/coresight-stm.c | 5 +- drivers/hwtracing/coresight/coresight-sysfs.c | 6 +- .../hwtracing/coresight/coresight-tmc-etf.c | 9 +- .../hwtracing/coresight/coresight-tmc-etr.c | 13 +-- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- drivers/hwtracing/coresight/coresight-tpda.c | 3 +- drivers/hwtracing/coresight/coresight-tpdm.c | 3 +- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 4 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 8 +- include/linux/coresight.h | 25 +++- 22 files changed, 159 insertions(+), 258 deletions(-) -- 2.34.1

8 months, 2 weeks

Re: [PATCH v9 5/6] Coresight: Add Coresight TMC Control Unit driver

by James Clark

On 29/01/2025 1:02 pm, Jie Gan wrote: > > > On 1/29/2025 6:35 PM, James Clark wrote: >> >> >> On 29/01/2025 12:46 am, Jie Gan wrote: >>> >>> >>> On 1/28/2025 7:55 PM, James Clark wrote: >>>> >>>> >>>> On 24/01/2025 7:25 am, Jie Gan wrote: >>>>> The Coresight TMC Control Unit hosts miscellaneous configuration >>>>> registers >>>>> which control various features related to TMC ETR sink. >>>>> >>>>> Based on the trace ID, which is programmed in the related CTCU ATID >>>>> register of a specific ETR, trace data with that trace ID gets into >>>>> the ETR buffer, while other trace data gets dropped. >>>>> >>>>> Enabling source device sets one bit of the ATID register based on >>>>> source device's trace ID. >>>>> Disabling source device resets the bit according to the source >>>>> device's trace ID. >>>>> >>>>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>>>> --- >>>>> drivers/hwtracing/coresight/Kconfig | 12 + >>>>> drivers/hwtracing/coresight/Makefile | 1 + >>>>> drivers/hwtracing/coresight/coresight-ctcu.c | 276 ++++++++++++++ >>>>> + ++++ >>>>> drivers/hwtracing/coresight/coresight-ctcu.h | 30 ++ >>>>> include/linux/coresight.h | 3 +- >>>>> 5 files changed, 321 insertions(+), 1 deletion(-) >>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c >>>>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h >>>> > >>>> >>>> [...] >>>> >>>>> +/* >>>>> + * ctcu_set_etr_traceid: Retrieve the ATID offset and trace ID. >>>>> + * >>>>> + * Returns 0 indicates success. None-zero result means failure. >>>>> + */ >>>>> +static int ctcu_set_etr_traceid(struct coresight_device *csdev, >>>>> struct coresight_path *cs_path, >>>>> + bool enable) >>>>> +{ >>>>> + struct coresight_device *sink = coresight_get_sink(cs_path- >>>>> >path); >>>>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev- >>>>> >dev.parent); >>>>> + u8 trace_id = cs_path->trace_id; >>>>> + int port_num; >>>>> + >>>>> + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(trace_id) || >>>>> IS_ERR_OR_NULL(drvdata)) { >>>>> + dev_err(&csdev->dev, "Invalid parameters\n"); >>>>> + return -EINVAL; >>>>> + } >>>>> + >>>>> + port_num = ctcu_get_active_port(sink, csdev); >>>>> + if (port_num < 0) >>>>> + return -EINVAL; >>>>> + >>>>> + /* >>>>> + * Skip the disable session if more than one TPDM device that >>>>> + * connected to the same TPDA device has been enabled. >>>>> + */ >>>>> + if (enable) >>>>> + atomic_inc(&drvdata->traceid_refcnt[port_num][trace_id]); >>>>> + else { >>>>> + if (atomic_dec_return(&drvdata->traceid_refcnt[port_num] >>>>> [trace_id]) > 0) { >>>>> + dev_dbg(&csdev->dev, "Skip the disable session\n"); >>>>> + return 0; >>>>> + } >>>>> + } >>>>> + >>>>> + dev_dbg(&csdev->dev, "traceid is %d\n", cs_path->trace_id); >>>>> + >>>>> + return __ctcu_set_etr_traceid(csdev, trace_id, port_num, enable); >>>> >>>> Hi Jie, >>>> >>>> Using atomic_dec_return() here doesn't prevent >>>> __ctcu_set_etr_traceid() from running concurrent enable and >>>> disables. Once you pass the atomic_dec_return() a second call to >>>> enable it will mess it up. >>>> >>>> I think you need a spinlock around the whole thing and then the >>>> refcounts don't need to be atomics. >>>> >>> Hi, James >>> Thanks for comment. I may not fully tested my codes here. What I was >>> thinking is there's no way the refcnt could become a negative number >>> under current framework. So I just added spinlock in >>> __ctcu_set_etr_traceid() to ensure concurrent sessions correctly >>> manipulate the register. >>> >>> As the trace_id related to the bit of the ATID register, I think the >>> concurrent processes are working fine with spinlock around read/write >>> register. >>> >>> I may not fully got your point here. Please help me to correct it. >>> >>> Thanks, >>> Jie >>> >>> >> >> No it can't become negative, but the refcount can be a different state >> to the one that was actually written: >> >> >> CPU0 CPU1 >> ---- ---- >> ctcu_set_etr_traceid(enable) >> ctcu_set_etr_traceid(disable) >> atomic_inc() >> recount == 1 >> atomic_dec() >> recount == 0 >> >> __ctcu_set_etr_traceid(disable) >> Lock and write disable state to >> device >> >> __ctcu_set_etr_traceid(enable) >> Lock and write enable state to >> device >> >> >> As you can see this leaves the device in an enabled state but the >> refcount is 0. > Yes, you are right. I didnt consider this scenario. We definitely need > spinlock here. > >> >> This is also quite large if you use atomic types: >> >> /* refcnt for each traceid of each sink */ >> atomic_t traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; >> >> Presumably you can't have the refcount for each ID be higher than the >> max number of TPDMs connected? If you make the locked area a bit wider >> you don't need atomic types and also solve the above problem. So you >> could do u8, or DECLARE_BITMAP() and bitmap_read() etc to read 3 bit >> values. Or however wide it needs to be. > The original purpose of using atomic here is trying to narrow the locked > area. > > I think u8 is ok here. > u8 traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP] will cost > 224 bytes, I think it's acceptable here. > > Thanks, > Jie > Yep u8 sounds ok then

8 months, 2 weeks

Re: [PATCH v9 5/6] Coresight: Add Coresight TMC Control Unit driver

by James Clark

On 29/01/2025 12:46 am, Jie Gan wrote: > > > On 1/28/2025 7:55 PM, James Clark wrote: >> >> >> On 24/01/2025 7:25 am, Jie Gan wrote: >>> The Coresight TMC Control Unit hosts miscellaneous configuration >>> registers >>> which control various features related to TMC ETR sink. >>> >>> Based on the trace ID, which is programmed in the related CTCU ATID >>> register of a specific ETR, trace data with that trace ID gets into >>> the ETR buffer, while other trace data gets dropped. >>> >>> Enabling source device sets one bit of the ATID register based on >>> source device's trace ID. >>> Disabling source device resets the bit according to the source >>> device's trace ID. >>> >>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>> --- >>> drivers/hwtracing/coresight/Kconfig | 12 + >>> drivers/hwtracing/coresight/Makefile | 1 + >>> drivers/hwtracing/coresight/coresight-ctcu.c | 276 +++++++++++++++++++ >>> drivers/hwtracing/coresight/coresight-ctcu.h | 30 ++ >>> include/linux/coresight.h | 3 +- >>> 5 files changed, 321 insertions(+), 1 deletion(-) >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c >>> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h >> > >> >> [...] >> >>> +/* >>> + * ctcu_set_etr_traceid: Retrieve the ATID offset and trace ID. >>> + * >>> + * Returns 0 indicates success. None-zero result means failure. >>> + */ >>> +static int ctcu_set_etr_traceid(struct coresight_device *csdev, >>> struct coresight_path *cs_path, >>> + bool enable) >>> +{ >>> + struct coresight_device *sink = coresight_get_sink(cs_path->path); >>> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> + u8 trace_id = cs_path->trace_id; >>> + int port_num; >>> + >>> + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(trace_id) || >>> IS_ERR_OR_NULL(drvdata)) { >>> + dev_err(&csdev->dev, "Invalid parameters\n"); >>> + return -EINVAL; >>> + } >>> + >>> + port_num = ctcu_get_active_port(sink, csdev); >>> + if (port_num < 0) >>> + return -EINVAL; >>> + >>> + /* >>> + * Skip the disable session if more than one TPDM device that >>> + * connected to the same TPDA device has been enabled. >>> + */ >>> + if (enable) >>> + atomic_inc(&drvdata->traceid_refcnt[port_num][trace_id]); >>> + else { >>> + if (atomic_dec_return(&drvdata->traceid_refcnt[port_num] >>> [trace_id]) > 0) { >>> + dev_dbg(&csdev->dev, "Skip the disable session\n"); >>> + return 0; >>> + } >>> + } >>> + >>> + dev_dbg(&csdev->dev, "traceid is %d\n", cs_path->trace_id); >>> + >>> + return __ctcu_set_etr_traceid(csdev, trace_id, port_num, enable); >> >> Hi Jie, >> >> Using atomic_dec_return() here doesn't prevent >> __ctcu_set_etr_traceid() from running concurrent enable and disables. >> Once you pass the atomic_dec_return() a second call to enable it will >> mess it up. >> >> I think you need a spinlock around the whole thing and then the >> refcounts don't need to be atomics. >> > Hi, James > Thanks for comment. I may not fully tested my codes here. What I was > thinking is there's no way the refcnt could become a negative number > under current framework. So I just added spinlock in > __ctcu_set_etr_traceid() to ensure concurrent sessions correctly > manipulate the register. > > As the trace_id related to the bit of the ATID register, I think the > concurrent processes are working fine with spinlock around read/write > register. > > I may not fully got your point here. Please help me to correct it. > > Thanks, > Jie > > No it can't become negative, but the refcount can be a different state to the one that was actually written: CPU0 CPU1 ---- ---- ctcu_set_etr_traceid(enable) ctcu_set_etr_traceid(disable) atomic_inc() recount == 1 atomic_dec() recount == 0 __ctcu_set_etr_traceid(disable) Lock and write disable state to device __ctcu_set_etr_traceid(enable) Lock and write enable state to device As you can see this leaves the device in an enabled state but the refcount is 0. This is also quite large if you use atomic types: /* refcnt for each traceid of each sink */ atomic_t traceid_refcnt[ATID_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; Presumably you can't have the refcount for each ID be higher than the max number of TPDMs connected? If you make the locked area a bit wider you don't need atomic types and also solve the above problem. So you could do u8, or DECLARE_BITMAP() and bitmap_read() etc to read 3 bit values. Or however wide it needs to be.

8 months, 2 weeks

Re: [PATCH v9 5/6] Coresight: Add Coresight TMC Control Unit driver

by James Clark

On 24/01/2025 7:25 am, Jie Gan wrote: > The Coresight TMC Control Unit hosts miscellaneous configuration registers > which control various features related to TMC ETR sink. > > Based on the trace ID, which is programmed in the related CTCU ATID > register of a specific ETR, trace data with that trace ID gets into > the ETR buffer, while other trace data gets dropped. > > Enabling source device sets one bit of the ATID register based on > source device's trace ID. > Disabling source device resets the bit according to the source > device's trace ID. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/Kconfig | 12 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-ctcu.c | 276 +++++++++++++++++++ > drivers/hwtracing/coresight/coresight-ctcu.h | 30 ++ > include/linux/coresight.h | 3 +- > 5 files changed, 321 insertions(+), 1 deletion(-) > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h > [...] > +/* > + * ctcu_set_etr_traceid: Retrieve the ATID offset and trace ID. > + * > + * Returns 0 indicates success. None-zero result means failure. > + */ > +static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *cs_path, > + bool enable) > +{ > + struct coresight_device *sink = coresight_get_sink(cs_path->path); > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + u8 trace_id = cs_path->trace_id; > + int port_num; > + > + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(trace_id) || IS_ERR_OR_NULL(drvdata)) { > + dev_err(&csdev->dev, "Invalid parameters\n"); > + return -EINVAL; > + } > + > + port_num = ctcu_get_active_port(sink, csdev); > + if (port_num < 0) > + return -EINVAL; > + > + /* > + * Skip the disable session if more than one TPDM device that > + * connected to the same TPDA device has been enabled. > + */ > + if (enable) > + atomic_inc(&drvdata->traceid_refcnt[port_num][trace_id]); > + else { > + if (atomic_dec_return(&drvdata->traceid_refcnt[port_num][trace_id]) > 0) { > + dev_dbg(&csdev->dev, "Skip the disable session\n"); > + return 0; > + } > + } > + > + dev_dbg(&csdev->dev, "traceid is %d\n", cs_path->trace_id); > + > + return __ctcu_set_etr_traceid(csdev, trace_id, port_num, enable); Hi Jie, Using atomic_dec_return() here doesn't prevent __ctcu_set_etr_traceid() from running concurrent enable and disables. Once you pass the atomic_dec_return() a second call to enable it will mess it up. I think you need a spinlock around the whole thing and then the refcounts don't need to be atomics.

8 months, 2 weeks

Re: [PATCH v9 3/6] Coresight: Introduce a new struct coresight_path

by James Clark

On 24/01/2025 7:25 am, Jie Gan wrote: > Add 'struct coresight_path' to store the data that is needed by > coresight_enable_path/coresight_disable_path. The structure > will be transmitted to the helper and sink device to enable > related funcationalities. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 87 ++++++++++++++----- > drivers/hwtracing/coresight/coresight-etb10.c | 3 +- > .../hwtracing/coresight/coresight-etm-perf.c | 52 ++++++----- > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > drivers/hwtracing/coresight/coresight-priv.h | 21 +++-- > drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++---- > .../hwtracing/coresight/coresight-tmc-etf.c | 3 +- > .../hwtracing/coresight/coresight-tmc-etr.c | 6 +- > drivers/hwtracing/coresight/coresight-trbe.c | 4 +- > drivers/hwtracing/coresight/ultrasoc-smb.c | 3 +- > 10 files changed, 137 insertions(+), 76 deletions(-) > [...] > INIT_LIST_HEAD(path); > + cs_path->path = path; > + /* > + * Since not all source devices have a defined trace_id function, > + * make sure to check for it before use. > + * > + * Assert the mode is CS_MODE_SYSFS, the trace_id will be assigned > + * again later if the mode is CS_MODE_PERF. > + */ > + if (source_ops(source)->trace_id != NULL) { > + rc = source_ops(source)->trace_id(source, CS_MODE_SYSFS, NULL); I don't think we should do this. Doesn't this consume two trace IDs for each session? And I'm not even sure if it's released properly if it's overwritten. It should be possible to consolidate the all the trace ID allocation to a single step when building the path, or another function that gets called just after the path is built. At the moment the ID can be allocated from about 5 different places and it's quite hard to understand, especially with these new changes. I have some of it coded up, let me finish it off and I can share it. > + if(IS_VALID_CS_TRACE_ID(rc)) > + cs_path->trace_id = rc; > + else > + cs_path->trace_id = 0; > + } > + else > + cs_path->trace_id = 0; [...] > +/** > + * struct coresight_path - data needed by enable/disable path > + * @handle: perf aux handle for ETM. > + * @path: path from source to sink. > + * @trace_id: trace_id of the whole path. > + */ > +struct coresight_path { > + struct perf_output_handle *handle; This is only needed to avoid adding *handle to the enable function call signature, but having it here implies it needs to be stored. And then we need to manage the lifecycle of it by nulling it on deletion. All of this can be avoided by just adding handle to enable(). Unrelated to this patch, but I'm not sure why we were passing around void* for handle either. It just makes the code hard to read and implies some flexibility that doesn't exist. It's always "struct perf_output_handle", so we can change void* to that in the enable functions. I also have a patch for this that I'll share in a bit. > + struct list_head *path; > + u8 trace_id; > +}; > + > static inline void coresight_insert_barrier_packet(void *buf) > { > if (buf) > @@ -132,16 +144,15 @@ static inline void CS_UNLOCK(void __iomem *addr) > } while (0); > } > > -void coresight_disable_path(struct list_head *path); > -int coresight_enable_path(struct list_head *path, enum cs_mode mode, > - void *sink_data); > +void coresight_disable_path(struct coresight_path *cs_path); > +int coresight_enable_path(struct coresight_path *cs_path, enum cs_mode mode); > struct coresight_device *coresight_get_sink(struct list_head *path); This needs to be exported otherwise the build fails because you use it in a module in another commit. I assume you are building as static?

8 months, 2 weeks

Re: [PATCH v8 2/5] Coresight: Add trace_id function to retrieving the trace ID

by James Clark

On 23/01/2025 6:28 am, Jie Gan wrote: > > > On 1/13/2025 8:02 PM, James Clark wrote: >> >> >> On 26/12/2024 1:10 am, Jie Gan wrote: >>> Add 'trace_id' function pointer in ops. It's responsible for >>> retrieving the device's trace ID. >>> >>> Add 'struct cs_sink_data' to store the data that is needed by >>> coresight_enable_path/coresight_disable_path. The structure >>> will be transmitted to the helper and sink device to enable >>> related funcationalities. >>> >> >> The new cs_sink_data struct is quite specific to this change. Can we >> start passing the path around to enable/disable functions, that will >> allow devices to gather anything they want in the future. Because we >> already have coresight_get_sink(path), coresight_get_source(path) etc. >> >> And see below, but for this case we can also change the path struct to >> contain the trace ID. Then all the new functions, allocations and >> searches for the trace ID are unecessary. The CTCU will have access to >> the path, and by the time its enable function is called the trace ID >> is already assigned. >> >> It's also easier to understand at which point a trace ID is allocated, >> rather than adding the trace_id() callbacks from everywhere which >> could potentially either read or allocate. I suppose that's "safer" >> because maybe it's not allocated, but I can't see what case it would >> happen in reverse. >> >>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>> --- >>> drivers/hwtracing/coresight/coresight-core.c | 59 +++++++++++++++---- >>> drivers/hwtracing/coresight/coresight-etb10.c | 3 +- >>> .../hwtracing/coresight/coresight-etm-perf.c | 37 ++++++++++-- >>> .../coresight/coresight-etm3x-core.c | 30 ++++++++++ >>> .../coresight/coresight-etm4x-core.c | 29 +++++++++ >>> drivers/hwtracing/coresight/coresight-priv.h | 13 +++- >>> drivers/hwtracing/coresight/coresight-stm.c | 22 +++++++ >>> drivers/hwtracing/coresight/coresight-sysfs.c | 24 +++++++- >>> .../hwtracing/coresight/coresight-tmc-etf.c | 3 +- >>> .../hwtracing/coresight/coresight-tmc-etr.c | 6 +- >>> drivers/hwtracing/coresight/coresight-tpda.c | 20 +++++++ >>> drivers/hwtracing/coresight/coresight-trbe.c | 4 +- >>> drivers/hwtracing/coresight/ultrasoc-smb.c | 3 +- >>> include/linux/coresight.h | 6 ++ >>> 14 files changed, 234 insertions(+), 25 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/ >>> hwtracing/coresight/coresight-core.c >>> index 0a9380350fb5..2e560b425fd4 100644 >>> --- a/drivers/hwtracing/coresight/coresight-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-core.c >>> @@ -23,6 +23,7 @@ >>> #include "coresight-etm-perf.h" >>> #include "coresight-priv.h" >>> #include "coresight-syscfg.h" >>> +#include "coresight-trace-id.h" >>> /* >>> * Mutex used to lock all sysfs enable and disable actions and >>> loading and >>> @@ -331,12 +332,12 @@ static int coresight_enable_helper(struct >>> coresight_device *csdev, >>> return helper_ops(csdev)->enable(csdev, mode, data); >>> } >>> -static void coresight_disable_helper(struct coresight_device *csdev) >>> +static void coresight_disable_helper(struct coresight_device *csdev, >>> void *data) >>> { >>> - helper_ops(csdev)->disable(csdev, NULL); >>> + helper_ops(csdev)->disable(csdev, data); >>> } >>> -static void coresight_disable_helpers(struct coresight_device *csdev) >>> +static void coresight_disable_helpers(struct coresight_device >>> *csdev, void *data) >>> { >>> int i; >>> struct coresight_device *helper; >>> @@ -344,7 +345,7 @@ static void coresight_disable_helpers(struct >>> coresight_device *csdev) >>> for (i = 0; i < csdev->pdata->nr_outconns; ++i) { >>> helper = csdev->pdata->out_conns[i]->dest_dev; >>> if (helper && coresight_is_helper(helper)) >>> - coresight_disable_helper(helper); >>> + coresight_disable_helper(helper, data); >>> } >>> } >>> @@ -361,7 +362,7 @@ static void coresight_disable_helpers(struct >>> coresight_device *csdev) >>> void coresight_disable_source(struct coresight_device *csdev, void >>> *data) >>> { >>> source_ops(csdev)->disable(csdev, data); >>> - coresight_disable_helpers(csdev); >>> + coresight_disable_helpers(csdev, NULL); >>> } >>> EXPORT_SYMBOL_GPL(coresight_disable_source); >>> @@ -371,7 +372,8 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); >>> * disabled. >>> */ >>> static void coresight_disable_path_from(struct list_head *path, >>> - struct coresight_node *nd) >>> + struct coresight_node *nd, >>> + void *sink_data) >>> { >>> u32 type; >>> struct coresight_device *csdev, *parent, *child; >>> @@ -417,13 +419,13 @@ static void coresight_disable_path_from(struct >>> list_head *path, >>> } >>> /* Disable all helpers adjacent along the path last */ >>> - coresight_disable_helpers(csdev); >>> + coresight_disable_helpers(csdev, sink_data); >>> } >>> } >>> -void coresight_disable_path(struct list_head *path) >>> +void coresight_disable_path(struct list_head *path, void *sink_data) >>> { >>> - coresight_disable_path_from(path, NULL); >>> + coresight_disable_path_from(path, NULL, sink_data); >>> } >>> EXPORT_SYMBOL_GPL(coresight_disable_path); >>> @@ -505,10 +507,47 @@ int coresight_enable_path(struct list_head >>> *path, enum cs_mode mode, >>> out: >>> return ret; >>> err: >>> - coresight_disable_path_from(path, nd); >>> + coresight_disable_path_from(path, nd, sink_data); >>> goto out; >>> } >>> +int coresight_read_traceid(struct list_head *path, enum cs_mode mode, >>> + struct coresight_trace_id_map *id_map) >>> +{ >>> + int trace_id, type; >>> + struct coresight_device *csdev; >>> + struct coresight_node *nd; >>> + >>> + list_for_each_entry(nd, path, link) { >> >> What do you think about also changing the path to this: >> >> struct coresight_path { >> struct list_head *path, >> u8 trace_id >> }; >> >> That would avoid having to traverse the path on every enable and would >> remove this function. You could also cache the trace ID in the CTCU >> for a similar benefit, but it wouldn't remove the need to call this at >> least once. >> >> The expensive part should be the create path part, after that enable >> and disable should be cheap because they happen on schedule for Perf >> mode. We should be avoiding allocations and searches. >> >>> + csdev = nd->csdev; >>> + type = csdev->type; >>> + >>> + switch (type) { >>> + case CORESIGHT_DEV_TYPE_SOURCE: >>> + if (source_ops(csdev)->trace_id != NULL) { >>> + trace_id = source_ops(csdev)->trace_id(csdev, >>> + mode, >>> + id_map); >>> + if (IS_VALID_CS_TRACE_ID(trace_id)) >>> + goto out; >>> + } >>> + break; >>> + case CORESIGHT_DEV_TYPE_LINK: >>> + if (link_ops(csdev)->trace_id != NULL) { >>> + trace_id = link_ops(csdev)->trace_id(csdev); >>> + if (IS_VALID_CS_TRACE_ID(trace_id)) >>> + goto out; >>> + } >>> + break; >>> + default: >>> + break; >>> + } >>> + } >>> + return -EINVAL; >>> +out: >>> + return trace_id; >>> +} >>> + >>> struct coresight_device *coresight_get_sink(struct list_head *path) >>> { >>> struct coresight_device *csdev; >>> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/ >>> hwtracing/coresight/coresight-etb10.c >>> index aea9ac9c4bd0..904b5531c256 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etb10.c >>> +++ b/drivers/hwtracing/coresight/coresight-etb10.c >>> @@ -173,7 +173,8 @@ static int etb_enable_perf(struct >>> coresight_device *csdev, void *data) >>> pid_t pid; >>> unsigned long flags; >>> struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); >>> - struct perf_output_handle *handle = data; >>> + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; >>> + struct perf_output_handle *handle = sink_data->handle; >>> struct cs_buffers *buf = etm_perf_sink_config(handle); >>> spin_lock_irqsave(&drvdata->spinlock, flags); >>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/ >>> drivers/hwtracing/coresight/coresight-etm-perf.c >>> index ad6a8f4b70b6..e676edd42ddc 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >>> @@ -459,6 +459,7 @@ static void etm_event_start(struct perf_event >>> *event, int flags) >>> struct perf_output_handle *handle = &ctxt->handle; >>> struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); >>> struct list_head *path; >>> + struct cs_sink_data *sink_data = NULL; >>> u64 hw_id; >>> u8 trace_id; >>> @@ -498,9 +499,20 @@ static void etm_event_start(struct perf_event >>> *event, int flags) >>> if (WARN_ON_ONCE(!sink)) >>> goto fail_end_stop; >>> + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); >> >> kzalloc can't be called from here. Check dmesg for the warning. That's >> another reason to do this change on the path. Because the path is >> allocated on etm_setup_aux() where allocations are allowed. >> > Hi, James > I just tried with following command and did not observe any warning info > from dmesg, may I ask what's the issue may suffered here? > You might be missing some debugging configs like lockdep etc. The warning is that etm_event_start() is a non-sleepable context and kzalloc is sleepable. Even if it wasn't an error we still wouldn't want to do it, etm_event_start() and stop are called too frequently. > root@qemuarm64:/data# ./perf record -e cs_etm/@tmc_etr0/ --per-thread ls > configs kernel.txt logs lost+found misc > perf perf.data perf.data.old root time > tzstorage weston > [ perf record: Woken up 1 times to write data ] > [ perf record: Captured and wrote 0.145 MB perf.data ] > > For the new patch version, I implemented an 8-bit hash table in the CTCU > driver data to handle situations where multiple TPDMs are connected to > the same TPDA device have been enabled. As we know, TPDMs share the > trace_id of the TPDA device they are connected to. If we reset the bit > based on the trace_id without checking the enabled refcount, it causes > an issue where trace data from other enabled TPDM devices (sharing the > same trace_id) cannot enter the ETR buffer, as it gets filtered out by > the CTCU. I think sharing the code or a diagram might be easier to follow here. The mention of a refcount makes sense but I don't follow the need for a hash table. There are other places where single devices are shared by multiple paths, like funnels, and they're all done with refcounts. > I need allocate memory when implement hash table(add/remove key entry) > in coresight_enable_path flow, but you mentioned we cannot call kzalloc > from here. > > Thanks, > Jie > Why not allocate on setup_aux()? That's called by userspace before the session starts, and then the path is fixed from that point onwards so you shouldn't need to do any more allocations. That's how it's setup currently anyway.

8 months, 3 weeks

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight