CoreSight

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2387 discussions

[PATCH v2] coresight: etm4x: Fix width of CCITMIN field

by James Clark

CCITMIN is a 12 bit field and doesn't fit in a u8, so extend it to u16. This probably wasn't an issue previously because values higher than 255 never occurred. But since commit 0f55b43dedcd ("coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus"), a comparison with 256 was done to enable the errata, generating the following W=1 build error: coresight-etm4x-core.c:1188:24: error: result of comparison of constant 256 with expression of type 'u8' (aka 'unsigned char') is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (drvdata->ccitmin == 256) Cc: stable(a)vger.kernel.org Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Reviewed-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: James Clark <james.clark(a)arm.com> --- Changes since V1: * Change the fixes commit to the original addition of ccitmin, rather than the last refactor of the struct. drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 20e2e4cb7614..da17b6c49b0f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1036,7 +1036,7 @@ struct etmv4_drvdata { u8 ctxid_size; u8 vmid_size; u8 ccsize; - u8 ccitmin; + u16 ccitmin; u8 s_ex_level; u8 ns_ex_level; u8 q_support; -- 2.34.1

1 year, 8 months

Re: [PATCH v2 7/8] dt-bindings: arm: Add support for TPDM CMB MSR register

by Tao Zhang

On 10/27/2023 5:27 AM, Rob Herring wrote: > On Wed, Oct 25, 2023 at 10:53:27AM +0800, Tao Zhang wrote: >> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) >> for TPDM. It specifies the number of CMB MSR registers supported by >> the TDPM. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index f9a2025..a586b80a 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -69,6 +69,15 @@ properties: >> minimum: 0 >> maximum: 32 >> >> + qcom,cmb-msrs-num: >> + description: >> + Specifies the number of CMB MSR(mux select register) registers supported >> + by the monitor. If this property is not configured or set to 0, it means >> + this TPDM doesn't support CMB MSR. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 0 >> + maximum: 32 > default: 0 If the TPDM doesn't support CMB MSR, we will not configure this property. Set to 0 to indicate that CMB MSR is not supported and is only an optional method. Is it necessary to add this "default" value here? Best, Tao >> + >> clocks: >> maxItems: 1 >> >> @@ -124,6 +133,7 @@ examples: >> reg-names = "tpdm-base"; >> >> qcom,cmb-element-size = /bits/ 8 <64>; >> + qcom,cmb-msrs-num = <32>; >> >> clocks = <&aoss_qmp>; >> clock-names = "apb_pclk"; >> -- >> 2.7.4 >>

1 year, 8 months

Re: [RESEND] [GIT PULL] coresight: Update for v6.7

by Suzuki K Poulose

On 30/10/2023 12:44, Greg KH wrote: > On Mon, Oct 30, 2023 at 12:04:55PM +0000, Suzuki K Poulose wrote: >> Hi Greg >> >> On 30/10/2023 11:32, Greg KH wrote: >>> On Mon, Oct 30, 2023 at 11:02:04AM +0000, Suzuki K Poulose wrote: >>>> Hi Greg >>>> >>>> Please find the updates for Linux v6.7. Kindly pull. >>> >>> It's too late, sorry. Last week might have been too late too, why the >>> last-minute pull request? >> >> Apologies, I was out sick last week. I was hoping that there would be >> an rc8. The tree wasn't changed since last two weeks. I will try to >> send the pull request at rc5-rc6 now onwards. > > Thank you. > >>> Please send new changes after -rc1 is out for bugfixes and for normal >>> new features. >> >> Just to make sure I understand this correctly, >> - I can send a pull request with handpicked fixes for rc1 > > Yes, after -rc1 is out. > >> - What about the other new features ? Ok > > They need to wait until 6.8-rc1, you can send me a pull request for them > after -rc1 is out as well, for my -next branch. Ok. > >> (I can summaries the features below) >> - TRBE ACPI support ( Parts of this feature went into v6.6 via >> Will's perf subsystem, the coresight part was dropped due to >> a conflict. I queued it for v6.7 - 2patches) >> - CoreSight TPDM support for DSB feature (~10patches) >> - Support for configuring cycle count threshold for ETM (3 patches) >> Do they need to wait for v6.8 or could some of them go in for v6.7 ? >> >> >>> >>>> Please note the changes were queued and rebased onto v6.6-rc6 (which added >>>> some of the fixes in the cycle). >>> >>> Why rebase? What required that? >> >> This was to be on the safer side. I don't think there was any conflict. > > As Linus constantly says, NEVER rebase unless you have to. That just > makes history messy, and makes me think that something actually changed. > Merge conflicts are fine, we can handle them trivially, do not rewrite > history just for that. Noted. Thanks Suzuki > > thanks, > > greg k-h

1 year, 8 months

Re: [RESEND] [GIT PULL] coresight: Update for v6.7

by Suzuki K Poulose

Hi Greg On 30/10/2023 11:32, Greg KH wrote: > On Mon, Oct 30, 2023 at 11:02:04AM +0000, Suzuki K Poulose wrote: >> Hi Greg >> >> Please find the updates for Linux v6.7. Kindly pull. > > It's too late, sorry. Last week might have been too late too, why the > last-minute pull request? Apologies, I was out sick last week. I was hoping that there would be an rc8. The tree wasn't changed since last two weeks. I will try to send the pull request at rc5-rc6 now onwards. > > Please send new changes after -rc1 is out for bugfixes and for normal > new features. Just to make sure I understand this correctly, - I can send a pull request with handpicked fixes for rc1 - What about the other new features ? (I can summaries the features below) - TRBE ACPI support ( Parts of this feature went into v6.6 via Will's perf subsystem, the coresight part was dropped due to a conflict. I queued it for v6.7 - 2patches) - CoreSight TPDM support for DSB feature (~10patches) - Support for configuring cycle count threshold for ETM (3 patches) Do they need to wait for v6.8 or could some of them go in for v6.7 ? > >> Please note the changes were queued and rebased onto v6.6-rc6 (which added >> some of the fixes in the cycle). > > Why rebase? What required that? This was to be on the safer side. I don't think there was any conflict. Suzuki > > thanks, > > greg k-h

1 year, 8 months

[GIT PULL] coresight: Update for v6.7

by Suzuki K Poulose

Hi Greg Please find the updates for Linux v6.7. Kindly pull. Please note the changes were queued and rebased onto v6.6-rc6 (which added some of the fixes in the cycle). Suzuki The following changes since commit 58720809f52779dc0f08e53e54b014209d13eebb: Linux 6.6-rc6 (2023-10-15 13:34:39 -0700) are available in the Git repository at: git//git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.7 for you to fetch changes up to fa55e63584f2c3c84e0c3acdace42544e1832cc2: Documentation: coresight: fix `make refcheckdocs` warning (2023-10-25 11:21:29 +0100) ---------------------------------------------------------------- coresight: Updates for Linux v6.7 Updates for the hwtracing subsystem includes : - Support for CoreSight TPDM DSB set - Support for tuning Cycle count Threshold for CoreSight ETM via perf - Support for TRBE on ACPI based systems - Several fixes for the HiSilcon PTT tracing driver - Fix crash with CoreSight ETM mixing perf and sysfs mode - Remove Leo Yan from Reviewers Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Anshuman Khandual (6): coresight: trbe: Add a representative coresight_platform_data for TRBE coresight: trbe: Enable ACPI based TRBE devices coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable coresight: tmc: Make etr buffer mode user configurable from sysfs Bagas Sanjaya (1): Documentation: ABI: coresight-tpdm: Fix Bit[3] description indentation James Clark (1): coresight: Fix crash when Perf and sysfs modes are used concurrently Junhao He (1): hwtracing: hisi_ptt: Add dummy callback pmu::read() Leo Yan (1): MAINTAINERS: Remove myself as a Arm CoreSight reviewer Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support Uwe Kleine-K��nig (1): coresight: etm4x: Remove bogous __exit annotation for some functions Vegard Nossum (1): Documentation: coresight: fix `make refcheckdocs` warning Yicong Yang (4): hwtracing: hisi_ptt: Disable interrupt after trace end hwtracing: hisi_ptt: Handle the interrupt in hardirq context hwtracing: hisi_ptt: Optimize the trace data committing hwtracing: hisi_ptt: Don't try to attach a task .../ABI/testing/sysfs-bus-coresight-devices-tmc | 16 + .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 159 +++++ Documentation/arch/arm64/silicon-errata.rst | 10 + .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + Documentation/trace/coresight/coresight.rst | 6 +- MAINTAINERS | 1 - drivers/hwtracing/coresight/coresight-core.c | 3 + drivers/hwtracing/coresight/coresight-etm-perf.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 52 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 15 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 111 +++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpda.c | 126 +++- drivers/hwtracing/coresight/coresight-tpda.h | 2 + drivers/hwtracing/coresight/coresight-tpdm.c | 718 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 161 +++++ drivers/hwtracing/coresight/coresight-trbe.c | 23 +- drivers/hwtracing/coresight/coresight-trbe.h | 2 + drivers/hwtracing/ptt/hisi_ptt.c | 33 +- drivers/hwtracing/ptt/hisi_ptt.h | 1 + include/linux/coresight.h | 1 + 21 files changed, 1411 insertions(+), 58 deletions(-)

1 year, 8 months

[PATCH] perf tests: test_arm_coresight: Simplify source iteration

by James Clark

There are two reasons to do this, firstly there is a shellcheck warning in cs_etm_dev_name(), which can be completely deleted. And secondly the current iteration method doesn't support systems with both ETE and ETM because it picks one or the other. There isn't a known system with this configuration, but it could happen in the future. Iterating over all the sources for each CPU can be done by going through /sys/bus/event_source/devices/cs_etm/cpu* and following the symlink back to the Coresight device in /sys/bus/coresight/devices. This will work whether the device is ETE, ETM or any future name, and is much simpler and doesn't require any hard coded version numbers Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: James Clark <james.clark(a)arm.com> --- This was discussed here previously: https://lore.kernel.org/all/20230929041133.95355-2-atrajeev@linux.vnet.ibm.… I chose not to add a fixes tag like the original because shellcheck isn't part of the build so it doesn't really fix any real issue yet and is just a refactor. tools/perf/tests/shell/test_arm_coresight.sh | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/tools/perf/tests/shell/test_arm_coresight.sh b/tools/perf/tests/shell/test_arm_coresight.sh index fe78c4626e45..65dd85207125 100755 --- a/tools/perf/tests/shell/test_arm_coresight.sh +++ b/tools/perf/tests/shell/test_arm_coresight.sh @@ -11,19 +11,6 @@ glb_err=0 -cs_etm_dev_name() { - cs_etm_path=$(find /sys/bus/event_source/devices/cs_etm/ -name cpu* -print -quit) - trcdevarch=$(cat ${cs_etm_path}/mgmt/trcdevarch) - archhver=$((($trcdevarch >> 12) & 0xf)) - archpart=$(($trcdevarch & 0xfff)) - - if [ $archhver -eq 5 -a "$(printf "0x%X\n" $archpart)" = "0xA13" ] ; then - echo "ete" - else - echo "etm" - fi -} - skip_if_no_cs_etm_event() { perf list | grep -q 'cs_etm//' && return 0 @@ -149,7 +136,9 @@ arm_cs_iterate_devices() { arm_cs_etm_traverse_path_test() { # Iterate for every ETM device - for dev in /sys/bus/coresight/devices/$(cs_etm_dev_name)*; do + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do + # Canonicalize the path + dev=`readlink -f $dev` # Find the ETM device belonging to which CPU cpu=`cat $dev/cpu` -- 2.34.1

1 year, 8 months

Re: [PATCH] Documentation: coresight: fix `make refcheckdocs` warning

by Suzuki K Poulose

On Sun, 22 Oct 2023 20:58:06 +0200, Vegard Nossum wrote: > This reference uses a glob pattern to match multiple files, but the > asterisk was escaped as \* in order to not be interpreted by sphinx > as reStructuredText markup. > > refcheckdocs/documentation-file-ref-check doesn't know about rST syntax > and tries to interpret the \* literally (instead of as a glob). > > [...] Applied, thanks! [1/1] Documentation: coresight: fix `make refcheckdocs` warning https://git.kernel.org/coresight/c/fa55e63584f2 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 year, 8 months

Re: [PATCH] coresight-tpdm: Correct the property name of MSR number

by Tao Zhang

On 10/20/2023 4:59 PM, Krzysztof Kozlowski wrote: > On 20/10/2023 10:13, Tao Zhang wrote: >>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c >>>> index b25284e..97654aa 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >>>> @@ -892,7 +892,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) >>>> >>>> if (drvdata && tpdm_has_dsb_dataset(drvdata)) >>>> of_property_read_u32(drvdata->dev->of_node, >>>> - "qcom,dsb_msr_num", &drvdata->dsb_msr_num); >>>> + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); >>> So you never tested your DTS... We can keep asking about this but still >>> testing does not happen :/ >> Since this new property has not been applied on the exist upstream DTS, >> I tested this driver with the >> >> local DTS. Unfortunately, the property name in the local DTS is not >> updated, this is why it is not found > But your local DTS would not pass dtbs_check tests, so that's why I am > saying - you never tested it on mainline kernel. Thanks, we will add this test in the future to ensure that DTS, doc and driver are consistent. Best, Tao > > Best regards, > Krzysztof >

1 year, 8 months

Re: [PATCH] coresight: etm4x: Allow configuring cycle count threshold

by Suzuki K Poulose

On 19/10/2023 09:23, Wei-Ning Huang wrote: > Allow userspace to configure cycle count threshold through > perf_event_attr config. The last high 12-bit of config value is used to > store the cycle count threshold. > We have queued the support already in coreisght next tree, patches posted here [0] [0] - https://lore.kernel.org/r/20230921033631.1298723-1-anshuman.khandual@arm.com Suzuki > Signed-off-by: Wei-Ning Huang <wnhuang(a)google.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++- > include/linux/coresight-pmu.h | 14 ++++++++------ > tools/include/linux/coresight-pmu.h | 14 ++++++++------ > 3 files changed, 21 insertions(+), 13 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 77b0271ce6eb..155441668b4a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > struct perf_event_attr *attr = &event->attr; > unsigned long cfg_hash; > int preset; > + u64 cyc_threadhold; > > /* Clear configuration from previous run */ > memset(config, 0, sizeof(struct etmv4_config)); > @@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > if (attr->config & BIT(ETM_OPT_CYCACC)) { > config->cfg |= TRCCONFIGR_CCI; > /* TRM: Must program this for cycacc to work */ > - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; > + cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) & > + ETM_OPT_CYC_THRESHOLD_MASK; > + config->ccctlr = cyc_threshold ? cyc_threshold : > + ETM_CYC_THRESHOLD_DEFAULT; > } > if (attr->config & BIT(ETM_OPT_TS)) { > /* > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > index 51ac441a37c3..14f48658ff1c 100644 > --- a/include/linux/coresight-pmu.h > +++ b/include/linux/coresight-pmu.h > @@ -29,12 +29,14 @@ > * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > * directly use below macros as config bits. > */ > -#define ETM_OPT_BRANCH_BROADCAST 8 > -#define ETM_OPT_CYCACC 12 > -#define ETM_OPT_CTXTID 14 > -#define ETM_OPT_CTXTID2 15 > -#define ETM_OPT_TS 28 > -#define ETM_OPT_RETSTK 29 > +#define ETM_OPT_BRANCH_BROADCAST 8 > +#define ETM_OPT_CYCACC 12 > +#define ETM_OPT_CTXTID 14 > +#define ETM_OPT_CTXTID2 15 > +#define ETM_OPT_TS 28 > +#define ETM_OPT_RETSTK 29 > +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 > +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff > > /* ETMv4 CONFIGR programming bits for the ETM OPTs */ > #define ETM4_CFG_BIT_BB 3 > diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h > index 51ac441a37c3..14f48658ff1c 100644 > --- a/tools/include/linux/coresight-pmu.h > +++ b/tools/include/linux/coresight-pmu.h > @@ -29,12 +29,14 @@ > * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and > * directly use below macros as config bits. > */ > -#define ETM_OPT_BRANCH_BROADCAST 8 > -#define ETM_OPT_CYCACC 12 > -#define ETM_OPT_CTXTID 14 > -#define ETM_OPT_CTXTID2 15 > -#define ETM_OPT_TS 28 > -#define ETM_OPT_RETSTK 29 > +#define ETM_OPT_BRANCH_BROADCAST 8 > +#define ETM_OPT_CYCACC 12 > +#define ETM_OPT_CTXTID 14 > +#define ETM_OPT_CTXTID2 15 > +#define ETM_OPT_TS 28 > +#define ETM_OPT_RETSTK 29 > +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 > +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff > > /* ETMv4 CONFIGR programming bits for the ETM OPTs */ > #define ETM4_CFG_BIT_BB 3

1 year, 8 months

[PATCH v2 0/4] Fixed some issues and cleanup of ultrasoc-smb

by Junhao He

Fix the Three issues listed below and use guards to cleanup a) Fixed the BUG of atomic-sleep b) Fixed uninitialized before use buf_hw_base c) Fixed use unreset SMB buffer Changes since V1: * Add comment for remove lock from smb_read() * Move reset buffer to before register sink * Remove patch "simplify the code for check to_copy valid" * Add two new patches Link to V1: https://lore.kernel.org/lkml/20231012094706.21565-1-hejunhao3@huawei.com/ Junhao He (4): coresight: ultrasoc-smb: Fix sleep while close preempt in enable_smb coresight: ultrasoc-smb: Config SMB buffer before register sink coresight: ultrasoc-smb: Fix uninitialized before use buf_hw_base coresight: ultrasoc-smb: Use guards to cleanup drivers/hwtracing/coresight/ultrasoc-smb.c | 108 +++++++-------------- drivers/hwtracing/coresight/ultrasoc-smb.h | 6 +- 2 files changed, 37 insertions(+), 77 deletions(-) -- 2.33.0

1 year, 8 months

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