CoreSight

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2394 discussions

[PATCH] coresight: etm_pmu: Set the module field

by Suzuki K Poulose

struct pmu::module must be set to the module owning the PMU driver. Set this for the coresight etm_pmu. Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index a48c97da8165..711f451b6946 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -901,6 +901,7 @@ int __init etm_perf_init(void) etm_pmu.addr_filters_sync = etm_addr_filters_sync; etm_pmu.addr_filters_validate = etm_addr_filters_validate; etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; + etm_pmu.module = THIS_MODULE; ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); if (ret == 0) -- 2.34.1

2 years, 3 months

[PATCH] coresight: Add support of setting trace id

by Mao Jinlong

With a growing number of trace sources, the number of source could be greater than 127 in future. There will be lack of ids. There could be also trace id reserved for some trace HW. With this change, trace id will be only configured when enable the source. Trace id will be dynamically allocated when traceid of driver data is not set when enable source. Once traceid of driver data is set when enable source, the traceid will be set as the specific value. Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- .../coresight/coresight-etm4x-core.c | 35 +++--- .../coresight/coresight-etm4x-sysfs.c | 30 +++++ drivers/hwtracing/coresight/coresight-stm.c | 67 ++++++++--- drivers/hwtracing/coresight/coresight-tpda.c | 107 ++++++++++++++---- drivers/hwtracing/coresight/coresight-tpda.h | 4 +- .../hwtracing/coresight/coresight-trace-id.c | 56 +++++++++ .../hwtracing/coresight/coresight-trace-id.h | 24 ++++ 7 files changed, 274 insertions(+), 49 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1ea8f173cca0..8f2e4d2b0fc2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -233,25 +233,32 @@ static int etm4_cpu_id(struct coresight_device *csdev) int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { - int trace_id; + int trace_id, ret = 0; - /* - * This will allocate a trace ID to the cpu, - * or return the one currently allocated. - * The trace id function has its own lock - */ - trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); - if (IS_VALID_CS_TRACE_ID(trace_id)) - drvdata->trcid = (u8)trace_id; - else - dev_err(&drvdata->csdev->dev, - "Failed to allocate trace ID for %s on CPU%d\n", - dev_name(&drvdata->csdev->dev), drvdata->cpu); - return trace_id; + if (!drvdata->trcid) { + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * The trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->trcid = (u8)trace_id; + else { + ret = -EINVAL; + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + } + } else + ret = coresight_trace_id_set_cpu_id(drvdata->cpu, drvdata->trcid); + + return ret; } void etm4_release_trace_id(struct etmv4_drvdata *drvdata) { + drvdata->trcid = 0; coresight_trace_id_put_cpu_id(drvdata->cpu); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 5e62aa40ecd0..bd342e63868c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2335,6 +2335,35 @@ static ssize_t ts_source_show(struct device *dev, } static DEVICE_ATTR_RO(ts_source); +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->trcid; + return sysfs_emit(buf, "0x%x\n", val); +} + +static ssize_t traceid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 16, &val); + if (ret) + return ret; + + if (!drvdata->csdev->enable) + drvdata->trcid = val; + + return size; +} +static DEVICE_ATTR_RW(traceid); + static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_nr_pe_cmp.attr, &dev_attr_nr_addr_cmp.attr, @@ -2390,6 +2419,7 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_vmid_masks.attr, &dev_attr_cpu.attr, &dev_attr_ts_source.attr, + &dev_attr_traceid.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 66a614c5492c..1291f5f39ab1 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -192,10 +192,29 @@ static void stm_enable_hw(struct stm_drvdata *drvdata) CS_LOCK(drvdata->base); } +static int stm_configure_trace_id(struct stm_drvdata *drvdata) +{ + int traceid, ret = 0; + + if (!drvdata->traceid) { + traceid = coresight_trace_id_get_system_id(); + if (traceid < 0) + return traceid; + + drvdata->traceid = traceid; + } else + ret = coresight_trace_id_set_system_id(drvdata->traceid); + + return ret; + +} + static int stm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { u32 val; + int ret; + struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); if (mode != CS_MODE_SYSFS) @@ -207,6 +226,10 @@ static int stm_enable(struct coresight_device *csdev, if (val) return -EBUSY; + ret = stm_configure_trace_id(drvdata); + if (ret) + return ret; + pm_runtime_get_sync(csdev->dev.parent); spin_lock(&drvdata->spinlock); @@ -261,6 +284,8 @@ static void stm_disable(struct coresight_device *csdev, struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct csdev_access *csa = &csdev->access; + + coresight_trace_id_put_system_id(drvdata->traceid); /* * For as long as the tracer isn't disabled another entity can't * change its status. As such we can read the status here without @@ -268,6 +293,7 @@ static void stm_disable(struct coresight_device *csdev, */ if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { spin_lock(&drvdata->spinlock); + drvdata->traceid = 0; stm_disable_hw(drvdata); spin_unlock(&drvdata->spinlock); @@ -608,7 +634,33 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } -static DEVICE_ATTR_RO(traceid); + +static ssize_t traceid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + unsigned long val; + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 16, &val); + if (ret) + return ret; + + if (!IS_VALID_CS_TRACE_ID(val)) { + dev_err(&drvdata->csdev->dev, "Invalid trace id\n"); + return -EINVAL; + } + + if (!drvdata->csdev->enable) + drvdata->traceid = val; + else + dev_err(&drvdata->csdev->dev, "Device must be enabled! %s\n", + __func__); + + return size; +} +static DEVICE_ATTR_RW(traceid); static struct attribute *coresight_stm_attrs[] = { &dev_attr_hwevent_enable.attr, @@ -806,7 +858,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret, trace_id; + int ret; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -890,22 +942,12 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } - trace_id = coresight_trace_id_get_system_id(); - if (trace_id < 0) { - ret = trace_id; - goto cs_unregister; - } - drvdata->traceid = (u8)trace_id; - pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; -cs_unregister: - coresight_unregister(drvdata->csdev); - stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -915,7 +957,6 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); - coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index f712e112ecff..41f83a5de3f2 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -21,6 +21,28 @@ DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); +static int tpda_configure_trace_id(struct tpda_drvdata *drvdata) +{ + int traceid, ret; + /* + * TPDA must has a unique atid. This atid can uniquely + * identify the TPDM trace source connected to the TPDA. + * The TPDMs which are connected to same TPDA share the + * same trace-id. When TPDA does packetization, different + * port will have unique channel number for decoding. + */ + if (!drvdata->traceid) { + traceid = coresight_trace_id_get_system_id(); + if (traceid < 0) + return traceid; + + drvdata->traceid = traceid; + } else + ret = coresight_trace_id_set_system_id(drvdata->traceid); + + return ret; +} + /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { @@ -28,8 +50,9 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) val = readl_relaxed(drvdata->base + TPDA_CR); val &= ~TPDA_CR_ATID; - val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + val |= FIELD_PREP(TPDA_CR_ATID, drvdata->traceid); writel_relaxed(val, drvdata->base + TPDA_CR); + } static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -52,11 +75,17 @@ static void __tpda_enable(struct tpda_drvdata *drvdata, int port) tpda_enable_port(drvdata, port); CS_LOCK(drvdata->base); + } static int tpda_enable(struct coresight_device *csdev, int inport, int outport) { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + ret = tpda_configure_trace_id(drvdata); + if (ret) + return ret; spin_lock(&drvdata->spinlock); if (atomic_read(&csdev->refcnt[inport]) == 0) @@ -87,7 +116,11 @@ static void tpda_disable(struct coresight_device *csdev, int inport, { struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + coresight_trace_id_put_system_id(drvdata->traceid); spin_lock(&drvdata->spinlock); + + drvdata->traceid = 0; + if (atomic_dec_return(&csdev->refcnt[inport]) == 0) __tpda_disable(drvdata, inport); @@ -105,27 +138,63 @@ static const struct coresight_ops tpda_cs_ops = { .link_ops = &tpda_link_ops, }; -static int tpda_init_default_data(struct tpda_drvdata *drvdata) +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) { - int atid; - /* - * TPDA must has a unique atid. This atid can uniquely - * identify the TPDM trace source connected to the TPDA. - * The TPDMs which are connected to same TPDA share the - * same trace-id. When TPDA does packetization, different - * port will have unique channel number for decoding. - */ - atid = coresight_trace_id_get_system_id(); - if (atid < 0) - return atid; + int val; + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); - drvdata->atid = atid; - return 0; + val = drvdata->traceid; + return sysfs_emit(buf, "0x%x\n", val); } -static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +static ssize_t traceid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) { int ret; + unsigned long val; + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 16, &val); + if (ret) + return ret; + + if (!IS_VALID_CS_TRACE_ID(val)) { + dev_err(drvdata->dev, "Invalid trace id\n"); + return -EINVAL; + } + + if (!drvdata->csdev->enable) + drvdata->traceid = val; + else + dev_err(drvdata->dev, "Device must be enabled! %s\n", __func__); + + return size; +} +static DEVICE_ATTR_RW(traceid); + +static struct attribute *coresight_tpda_attrs[] = { + &dev_attr_traceid.attr, + NULL, +}; + +static const struct attribute_group coresight_tpda_group = { + .attrs = coresight_tpda_attrs, +}; + +static const struct attribute_group *coresight_tpda_groups[] = { + &coresight_tpda_group, + NULL, +}; + +static void tpda_init_default_data(struct tpda_drvdata *drvdata) +{ + drvdata->traceid = 0; +} + +static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +{ struct device *dev = &adev->dev; struct coresight_platform_data *pdata; struct tpda_drvdata *drvdata; @@ -151,9 +220,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); - ret = tpda_init_default_data(drvdata); - if (ret) - return ret; + tpda_init_default_data(drvdata); desc.name = coresight_alloc_device_name(&tpda_devs, dev); if (!desc.name) @@ -164,6 +231,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; desc.access = CSDEV_ACCESS_IOMEM(base); + desc.groups = coresight_tpda_groups; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); @@ -178,7 +246,6 @@ static void tpda_remove(struct amba_device *adev) { struct tpda_drvdata *drvdata = dev_get_drvdata(&adev->dev); - coresight_trace_id_put_system_id(drvdata->atid); coresight_unregister(drvdata->csdev); } diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 0399678df312..5de6dc92f450 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -22,14 +22,14 @@ * @dev: The device entity associated to this component. * @csdev: component vitals needed by the framework. * @spinlock: lock for the drvdata value. - * @enable: enable status of the component. + * @traceid: the atid value of TPDA. */ struct tpda_drvdata { void __iomem *base; struct device *dev; struct coresight_device *csdev; spinlock_t spinlock; - u8 atid; + u8 traceid; }; #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c index af5b4ef59cea..192626efcb01 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -110,6 +110,19 @@ static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map return id; } +static int coresight_trace_id_set(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) + return -EINVAL; + if (WARN(test_bit(id, id_map->used_ids), "ID is already used: %d\n", id)) + return -EINVAL; + set_bit(id, id_map->used_ids); + + DUMP_ID_MAP(id_map); + + return 0; +} + static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) { if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) @@ -195,6 +208,37 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_ return id; } +static int coresight_trace_id_map_set_cpu_id(int cpu, int id, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) { + spin_unlock_irqrestore(&id_map_lock, flags); + return -EINVAL; + } + + if (WARN(test_bit(id, id_map->used_ids), "ID is already used: %d\n", id)) { + spin_unlock_irqrestore(&id_map_lock, flags); + return -EINVAL; + } + + set_bit(id, id_map->used_ids); + + /* allocate the new id to the cpu */ + atomic_set(&per_cpu(cpu_id, cpu), id); + + cpumask_clear_cpu(cpu, &cpu_id_release_pending); + clear_bit(id, id_map->pend_rel_ids); + + spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); + + return 0; +} + static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) { unsigned long flags; @@ -251,6 +295,12 @@ static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map * /* API functions */ +int coresight_trace_id_set_cpu_id(int cpu, int id) +{ + return coresight_trace_id_map_set_cpu_id(cpu, id, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_set_cpu_id); + int coresight_trace_id_get_cpu_id(int cpu) { return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); @@ -269,6 +319,12 @@ int coresight_trace_id_read_cpu_id(int cpu) } EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); +int coresight_trace_id_set_system_id(int id) +{ + return coresight_trace_id_set(id, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_set_system_id); + int coresight_trace_id_get_system_id(void) { return coresight_trace_id_map_get_system_id(&id_map_default); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h index 3797777d367e..5dab9a473266 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.h +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -61,8 +61,21 @@ struct coresight_trace_id_map { DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); }; + /* Allocate and release IDs for a single default trace ID map */ +/** + * Set the CoreSight Trace Id for the CPU. + * + * Set CoreSight Trace Id associated with the CPU. + * + * @cpu: The CPU index for the id. + * @id: Coresight Trace ID value. + * + * return: 0 if set successfully or -EINVAL if fail to set. + */ +int coresight_trace_id_set_cpu_id(int cpu, int id); + /** * Read and optionally allocate a CoreSight trace ID and associate with a CPU. * @@ -111,6 +124,17 @@ void coresight_trace_id_put_cpu_id(int cpu); */ int coresight_trace_id_read_cpu_id(int cpu); +/** + * Set trace id for a system component. + * + * Set the trace id if system component needs a static id for the trace. + * + * @id: value of trace ID. + * + * return: 0 if set successfully or -EINVAL if fail to set. + */ +int coresight_trace_id_set_system_id(int id); + /** * Allocate a CoreSight trace ID for a system component. * -- 2.39.0

2 years, 3 months

Re: [PATCH v2 0/6] Refactor definitions out of perf.h

by Arnaldo Carvalho de Melo

Em Mon, Apr 10, 2023 at 09:25:05AM -0700, Ian Rogers escreveu: > Move definitions and declarations for greater consistency. > > The original motivation was, when fuzzing something like parse-events, > having the main function in perf.c alongside global variables like > input_name means that input_name must be redeclared with the fuzzer > function's main. However, as the fuzzer is using the tools/perf code > as a library this causes backward linking reference that the linker > may warn about. > > v2. Remove references from commit messages about linking, as Adrian > points out we could solve that problem with #ifdefs. Thanks, applied. - Arnaldo > Ian Rogers (6): > perf ui: Move window resize signal functions > perf usage: Move usage strings > perf header: Move perf_version_string declaration > perf version: Use regular verbose flag > perf util: Move input_name to util > perf util: Move perf_guest/host declarations > > tools/perf/builtin-annotate.c | 2 +- > tools/perf/builtin-buildid-list.c | 2 +- > tools/perf/builtin-c2c.c | 2 +- > tools/perf/builtin-data.c | 2 +- > tools/perf/builtin-diff.c | 2 +- > tools/perf/builtin-evlist.c | 2 +- > tools/perf/builtin-help.c | 1 + > tools/perf/builtin-kmem.c | 2 +- > tools/perf/builtin-kvm.c | 1 + > tools/perf/builtin-kwork.c | 2 +- > tools/perf/builtin-mem.c | 2 +- > tools/perf/builtin-sched.c | 2 +- > tools/perf/builtin-stat.c | 2 +- > tools/perf/builtin-timechart.c | 2 +- > tools/perf/builtin-version.c | 7 +++---- > tools/perf/builtin.h | 3 --- > tools/perf/perf.c | 27 +-------------------------- > tools/perf/perf.h | 9 --------- > tools/perf/ui/browsers/hists.c | 2 +- > tools/perf/ui/hist.c | 2 +- > tools/perf/ui/setup.c | 19 +++++++++++++++++++ > tools/perf/ui/tui/setup.c | 1 - > tools/perf/ui/ui.h | 3 +++ > tools/perf/util/cs-etm.c | 1 + > tools/perf/util/event.c | 2 +- > tools/perf/util/evlist.c | 1 + > tools/perf/util/header.h | 2 ++ > tools/perf/util/parse-events.c | 2 +- > tools/perf/util/session.c | 2 +- > tools/perf/util/top.c | 2 +- > tools/perf/util/usage.c | 6 ++++++ > tools/perf/util/util.c | 2 ++ > tools/perf/util/util.h | 8 ++++++++ > 33 files changed, 66 insertions(+), 61 deletions(-) > > -- > 2.40.0.577.gac1e443424-goog > -- - Arnaldo

2 years, 3 months

Re: [PATCH] coresight: etm4x: add AMBA id for Cortex-A510

by Mike Leach

Hi, Please also post to all the relevant lists when submitting a patch, as defined in ./scripts/get_maintainer.pl On Thu, 6 Apr 2023 at 03:23, Sean Wang <seanwang1(a)lenovo.com> wrote: > > From: Sean Wang <seanwang1(a)lenovo.com> > > Add AMBA UCI id to support Cortex-A510 > > Signed-off-by: Sean Wang <seanwang1(a)lenovo.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1ea8f173cca0..702704cf4f1f 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -2186,6 +2186,15 @@ static struct amba_cs_uci_id uci_id_etm4[] = { > } > }; > > +static struct amba_cs_uci_id uci_id_ete[] = { > + { > + /* ETE UCI data */ > + .devarch = ETM_DEVARCH_ETE_ARCH, > + .devarch_mask = ETM_DEVARCH_ID_MASK, > + .devtype = 0x00000013, > + } > +}; > + > static void clear_etmdrvdata(void *info) > { > int cpu = *(int *)info; > @@ -2264,6 +2273,7 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ > CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ > CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ > + CS_AMBA_UCI_ID(0x000bbd46, uci_id_ete),/* Cortex-A510 */ > {}, > }; > > -- > 2.34.1 > I do not believe that this is needed. ETE is architecturally required to implement the system instructions interface to the ETE trace registers, and memory mapped access to the ETE from the PE is removed by the specification Your board .dts should declare ETE with the compatible "arm,embedded-trace-extension", and the system instruction platform driver will be initialised, which does not require the AMBA matching IDs. If your solution does have the optional APB interface to the ETE we would expect this to be used by any external debug system and not by self hosted trace in the linux kernel. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 3 months

Re: [GIT PULL] coresight: Fixes for v6.3

by Suzuki K Poulose

On 05/04/2023 11:31, Greg KH wrote: > On Wed, Apr 05, 2023 at 11:16:17AM +0100, Suzuki K Poulose wrote: >> Hi Greg, >> >> On 21/03/2023 16:21, Greg KH wrote: >>> On Tue, Mar 21, 2023 at 01:38:52PM +0000, Suzuki K Poulose wrote: >>>> Greg, >>>> >>>> Please find a couple of fixes for coresight self-hosted tracing for v6.3. Kindly >>>> consider pulling. >>>> >>>> Suzuki >>>> >>>> >>>> The following changes since commit eeac8ede17557680855031c6f305ece2378af326: >>>> >>>> Linux 6.3-rc2 (2023-03-12 16:36:44 -0700) >>>> >>>> are available in the Git repository at: >>>> >>>> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-fixes-v6.3 >> >>> >>> Pulled and pushed out, thanks. >> >> Just wondering, why this hasn't shown up on linus' tree yet ? Do you plan to >> send it for rc6 ? > > Yes. Thanks! I will wait for that, before I queue the patches for the next cycle. Suzuki

2 years, 3 months

Re: [GIT PULL] coresight: Fixes for v6.3

by Suzuki K Poulose

Hi Greg, On 21/03/2023 16:21, Greg KH wrote: > On Tue, Mar 21, 2023 at 01:38:52PM +0000, Suzuki K Poulose wrote: >> Greg, >> >> Please find a couple of fixes for coresight self-hosted tracing for v6.3. Kindly >> consider pulling. >> >> Suzuki >> >> >> The following changes since commit eeac8ede17557680855031c6f305ece2378af326: >> >> Linux 6.3-rc2 (2023-03-12 16:36:44 -0700) >> >> are available in the Git repository at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-fixes-v6.3 > > Pulled and pushed out, thanks. Just wondering, why this hasn't shown up on linus' tree yet ? Do you plan to send it for rc6 ? Suzuki

2 years, 3 months

[PATCH v4 00/13] coresight: Fix CTI module refcount leak by making it a helper device

by James Clark

Changes since v3: * Put connection loss fix at the beginning so that it can be backported * Replace coresight_find_link_{x}() with coresight_find_out_connection() * Reorder coresight_enable_source() arguments for consistency * Add source and destination reference counts so that two link devices connected together don't clash * Add coresight_is_helper() * Fix overwriting csdev bug in coresight_orphan_match() * Don't clear conns[i]->dest_fwnode in coresight_remove_conns() in case it's used again * Use dev instead of adev->dev for devmem allocation in acpi_coresight_parse_graph() so that it's consistent with DT mode and doesn't cause a warning on free. * Rename coresight_add_helper_mutex() -> coresight_add_helper() * Ensure coresight_mutex isn't already held in coresight_add_helper() * Return new connection from coresight_add_out_conn() * Comment and formatting improvements ------------------ Changes since v2: * Make out_conns array contiguous instead of sparse which simplifies filling and using it. New connections are always added to the end * Store pointers to individual connection objects so that they can be shared between inputs and outputs * Fix an existing bug where connection info was lost when unloading a device * Simplify connection fixup functions. Now the orphan mechanism is used for inputs in the same way as outputs to guarantee that all connections have both an input and an output set * Use input connections to disconnect devices on unload instead of iterating through them all * Make refcount a property of the connection rather than use it's own array based on the number of inputs and outputs * Fix a bug in v2 where helpers attached to the source device weren't disabled because coresight-etm-perf.c was making a raw call to disable rather than using a helper. * Change names of connection members to make direction explicit now that the connection is shared between input and outputs ------------------ Changes since v1: * Don't dereference handle in tmc_etr_get_buffer() when not in perf mode. * Fix some W=1 warnings * Add a commit to rename child/output in terms of local/remote ------------------- Currently there is a refcount leak in CTI when using system wide mode or tracing multithreaded applications. See the last commit for a reproducer. This prevents the module from being unloaded. Historically there have been a few issues and fixes attempted around here which have resulted in some extra logic and a member to keep track of CTI being enabled 'struct coresight_device->ect_enabled'. The fix in commit 665c157e0204 ("coresight: cti: Fix hang in cti_disable_hw()") was also related to CTI having its own enable/disable path which came later than other devices. If we make CTI a helper device and enable helper devices adjacent to the path we get very similar enable/disable behavior to now, but with more reuse of the existing reference counting logic in the coresight core code. This also affects CATU which can have a little bit of its hard coded enable/disable code removed. Enabling CATU on the generic path does require that input connections are tracked so that it can get its associated ETR buffer. Applies to coresight/next (197b6b60ae7b) but also requires the realloc_array patch here [1]. Also available in full here [2]. [1]: https://lore.kernel.org/linux-arm-kernel/20230306152723.3090195-1-james.cla… [2]: https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-cs-cti-module-refcou… James Clark (13): coresight: Fix loss of connection info when a module is unloaded coresight: Use enum type for cs_mode wherever possible coresight: Change name of pdata->conns coresight: Rename nr_outports to nr_outconns coresight: Rename connection members to make the direction explicit coresight: Dynamically add connections coresight: Store pointers to connections rather than an array of them coresight: Simplify connection fixup mechanism coresight: Store in-connections as well as out-connections coresight: Make refcount a property of the connection coresight: Refactor out buffer allocation function for ETR coresight: Enable and disable helper devices adjacent to the path coresight: Fix CTI module refcount leak by making it a helper device drivers/hwtracing/coresight/coresight-catu.c | 21 +- drivers/hwtracing/coresight/coresight-core.c | 595 ++++++++++-------- .../hwtracing/coresight/coresight-cti-core.c | 52 +- .../hwtracing/coresight/coresight-cti-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-cti.h | 4 +- drivers/hwtracing/coresight/coresight-etb10.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.c | 4 +- .../coresight/coresight-etm3x-core.c | 6 +- .../coresight/coresight-etm4x-core.c | 6 +- .../hwtracing/coresight/coresight-funnel.c | 26 +- .../hwtracing/coresight/coresight-platform.c | 260 +++----- drivers/hwtracing/coresight/coresight-priv.h | 17 +- .../coresight/coresight-replicator.c | 23 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 +- .../hwtracing/coresight/coresight-tmc-etf.c | 26 +- .../hwtracing/coresight/coresight-tmc-etr.c | 110 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpda.c | 23 +- drivers/hwtracing/coresight/coresight-tpdm.c | 4 +- drivers/hwtracing/coresight/coresight-tpiu.c | 7 +- drivers/hwtracing/coresight/coresight-trbe.c | 3 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 11 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- include/linux/coresight.h | 127 ++-- 25 files changed, 701 insertions(+), 668 deletions(-) -- 2.34.1

2 years, 3 months

[PATCH v3 00/13] coresight: Fix CTI module refcount leak by making it a helper device

by James Clark

Changes since v2: * Make out_conns array contiguous instead of sparse which simplifies filling and using it. New connections are always added to the end * Store pointers to individual connection objects so that they can be shared between inputs and outputs * Fix an existing bug where connection info was lost when unloading a device * Simplify connection fixup functions. Now the orphan mechanism is used for inputs in the same way as outputs to guarantee that all connections have both an input and an output set * Use input connections to disconnect devices on unload instead of iterating through them all * Make refcount a property of the connection rather than use it's own array based on the number of inputs and outputs * Fix a bug in v2 where helpers attached to the source device weren't disabled because coresight-etm-perf.c was making a raw call to disable rather than using a helper. * Change names of connection members to make direction explicit now that the connection is shared between input and outputs ------------------ Changes since v1: * Don't dereference handle in tmc_etr_get_buffer() when not in perf mode. * Fix some W=1 warnings * Add a commit to rename child/output in terms of local/remote ------------------- Currently there is a refcount leak in CTI when using system wide mode or tracing multithreaded applications. See the last commit for a reproducer. This prevents the module from being unloaded. Historically there have been a few issues and fixes attempted around here which have resulted in some extra logic and a member to keep track of CTI being enabled 'struct coresight_device->ect_enabled'. The fix in commit 665c157e0204 ("coresight: cti: Fix hang in cti_disable_hw()") was also related to CTI having its own enable/disable path which came later than other devices. If we make CTI a helper device and enable helper devices adjacent to the path we get very similar enable/disable behavior to now, but with more reuse of the existing reference counting logic in the coresight core code. This also affects CATU which can have a little bit of its hard coded enable/disable code removed. Enabling CATU on the generic path does require that input connections are tracked so that it can get its associated ETR buffer. Applies to coresight/next (197b6b60ae7b) but also requires the realloc_array patch here [1]. Also available in full here [2]. [1]: https://lore.kernel.org/linux-arm-kernel/20230306152723.3090195-1-james.cla… [2]: https://gitlab.arm.com/linux-arm/linux-jc/-/tree/james-cs-cti-module-refcou… James Clark (13): coresight: Use enum type for cs_mode wherever possible coresight: Change name of pdata->conns coresight: Rename nr_outports to nr_outconns coresight: Rename connection members to make the direction explicit coresight: Dynamically add connections coresight: Fix loss of connection info when a module is unloaded coresight: Store pointers to connections rather than an array of them coresight: Simplify connection fixup mechanism coresight: Store in-connections as well as out-connections coresight: Make refcount a property of the connection coresight: Refactor out buffer allocation function for ETR coresight: Enable and disable helper devices adjacent to the path coresight: Fix CTI module refcount leak by making it a helper device drivers/hwtracing/coresight/coresight-catu.c | 21 +- drivers/hwtracing/coresight/coresight-core.c | 557 +++++++++--------- .../hwtracing/coresight/coresight-cti-core.c | 52 +- .../hwtracing/coresight/coresight-cti-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-cti.h | 4 +- drivers/hwtracing/coresight/coresight-etb10.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.c | 4 +- .../coresight/coresight-etm3x-core.c | 6 +- .../coresight/coresight-etm4x-core.c | 6 +- .../hwtracing/coresight/coresight-funnel.c | 26 +- .../hwtracing/coresight/coresight-platform.c | 250 +++----- drivers/hwtracing/coresight/coresight-priv.h | 17 +- .../coresight/coresight-replicator.c | 23 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 +- .../hwtracing/coresight/coresight-tmc-etf.c | 26 +- .../hwtracing/coresight/coresight-tmc-etr.c | 110 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpda.c | 23 +- drivers/hwtracing/coresight/coresight-tpdm.c | 4 +- drivers/hwtracing/coresight/coresight-tpiu.c | 7 +- drivers/hwtracing/coresight/coresight-trbe.c | 3 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 11 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- include/linux/coresight.h | 124 ++-- 25 files changed, 669 insertions(+), 649 deletions(-) -- 2.34.1

2 years, 3 months

[PATCH] MAINTAINERS: Remove Mathieu Poirier as coresight maintainer

by Suzuki K Poulose

Mathieu Poirier is no longer involved in maintainig the CoreSight self-hosted tracing subsystem. Mathieu, Thank you very much creating and maintaing the subsystem all these years ! Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- CREDITS | 5 +++++ MAINTAINERS | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/CREDITS b/CREDITS index 847059166a15..216e86f56dd9 100644 --- a/CREDITS +++ b/CREDITS @@ -3459,6 +3459,11 @@ D: several improvements to system programs S: Oldenburg S: Germany +N: Mathieu Poirier +E: mathieu.poirier(a)linaro.org +D: CoreSight kernel subsystem, Maintainer 2014-2022 +D: Perf tool support for CoreSight + N: Robert Schwebel E: robert(a)schwebel.de W: https://www.schwebel.de diff --git a/MAINTAINERS b/MAINTAINERS index 90abe83c02f3..6c971e95a6fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2091,7 +2091,6 @@ F: arch/arm/boot/dts/cx92755* N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS -M: Mathieu Poirier <mathieu.poirier(a)linaro.org> M: Suzuki K Poulose <suzuki.poulose(a)arm.com> R: Mike Leach <mike.leach(a)linaro.org> R: Leo Yan <leo.yan(a)linaro.org> -- 2.34.1

2 years, 3 months

Re: [PATCH V2 3/5] coresight: etm4x: Drop pid argument from etm4_probe()

by Suzuki K Poulose

On 31/03/2023 22:24, Steve Clevenger wrote: > > > On 3/31/2023 4:06 AM, Suzuki K Poulose wrote: >> On 27/03/2023 06:05, Anshuman Khandual wrote: >>> Coresight device pid can be retrieved from its iomem base address, >>> which is >>> stored in 'struct etm4x_drvdata'. This drops pid argument from >>> etm4_probe() >>> and 'struct etm4_init_arg'. Instead etm4_check_arch_features() derives >>> the >>> coresight device pid with a new helper coresight_get_pid(), right >>> before it >>> is consumed in etm4_hisi_match_pid(). >>> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> Cc: Mike Leach <mike.leach(a)linaro.org> >>> Cc: Leo Yan <leo.yan(a)linaro.org> >>> Cc: coresight(a)lists.linaro.org >>> Cc: linux-arm-kernel(a)lists.infradead.org >>> Cc: linux-kernel(a)vger.kernel.org >>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> --- >>> .../coresight/coresight-etm4x-core.c | 21 +++++++------------ >>> include/linux/coresight.h | 12 +++++++++++ >>> 2 files changed, 20 insertions(+), 13 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index 5d77571a8df9..3521838ab4fb 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -66,7 +66,6 @@ static u64 etm4_get_access_type(struct etmv4_config >>> *config); >>> static enum cpuhp_state hp_online; >>> struct etm4_init_arg { >>> - unsigned int pid; >>> struct device *dev; >>> struct csdev_access *csa; >>> }; >>> @@ -370,8 +369,10 @@ static void etm4_disable_arch_specific(struct >>> etmv4_drvdata *drvdata) >>> } >>> static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, >>> - unsigned int id) >>> + struct csdev_access *csa) >>> { >>> + unsigned int id = coresight_get_pid(csa); >>> + >> >> This throws up the following error on an ETE. >> >> ete: trying to read unsupported register @fe0 >> >> So, I guess this must be performed only for iomem based >> devices. System instruction based device must be identified >> by MIDR_EL1/REVIDR_EL1 if needed for specific erratum. >> This is not required now. So, we could bail out early >> if we are system instruction based device. > > Besides this, the PID is limited to (I think) 4 bits of ID. TRCIDRs > offer revision information, but nothing manufacturer specific save for > the designer. Register fields like MIDR_EL1 Variant + PartNum + Revision > and TRCPIDR3 REVAND offer help. It may be a combination of registers are > needed for a manufacturer to adequately ID a part to apply an erratum. > Perhaps you could at least cache MIDR_EL1 for possible future use? Like I said, if we ever need them, we could add it. I don't see a point in storing it right now, if we don't use it. Suzuki

2 years, 3 months

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