CoreSight

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2101 discussions

Re: [PATCH] coresight: Defer probe when the child dev is not probed

by Mike Leach

Hi, On Tue, 1 Mar 2022 at 11:42, Jinlong Mao <quic_jinlmao(a)quicinc.com> wrote: > > On 2/28/2022 10:51 PM, Suzuki K Poulose wrote: > > Hi Jinlong > > On 28/02/2022 13:31, Mao Jinlong wrote: > > From: Mao Jinlong <jinlmao(a)qti.qualcomm.com> > > It is possible that when device probe, its child device is not > probed. Then it will fail when add sysfs connection for the device. > Make device defer probe when the child device is not probed. > > > Please could you a bit a more specific on the exact issue ? > I don't see a problem with probe deferral right now, with > coresight/next. > > For e.g., > > root@juno-server:~# lsmod > Module Size Used by > coresight 73728 0 > root@juno-server:~# ls /sys/bus/coresight/devices/ > root@juno-server:~# modprobe coresight-etm4x > root@juno-server:~# lsmod > Module Size Used by > coresight_etm4x 81920 0 > coresight 73728 1 coresight_etm4x > root@juno-server:~# ls /sys/bus/coresight/devices/ > etm0 etm1 > > -- Note etm2-etm5 doesn't appear -- > > root@juno-server:~# modprobe coresight-funnel > root@juno-server:~# lsmod > Module Size Used by > coresight_funnel 20480 0 > coresight_etm4x 81920 0 > coresight 73728 2 coresight_etm4x,coresight_funnel > root@juno-server:~# ls /sys/bus/coresight/devices/ > etm0 etm1 > > -- Still don't appear --- > > root@juno-server:~# modprobe coresight-replicator > root@juno-server:~# ls /sys/bus/coresight/devices/ > etm0 etm1 > root@juno-server:~# modprobe coresight-tmc > > -- At this stage, the devices automatically get probed and appear -- > root@juno-server:~# ls /sys/bus/coresight/devices/ > etm0 etm1 etm2 etm3 etm4 etm5 funnel0 funnel1 funnel2 tmc_etf0 tmc_etr0 > > > root@juno-server:~# lsmod > Module Size Used by > coresight_tmc 40960 0 > coresight_replicator 20480 0 > coresight_funnel 20480 0 > coresight_etm4x 81920 0 > coresight 73728 4 coresight_tmc,coresight_etm4x,coresight_replicator,coresight_funnel > > So, my question is, what is this patch trying to solve ? > > > Cheers > Suzuki > > Hi Suzuki, > > This issue happens when race condition happens. > The condition is that the device and its child_device's probe happens at the same time. > > For example: device0 and its child device device1. > Both of them are calling coresight_register function. device0 is calling coresight_fixup_device_conns. > device1 is waiting for device0 to release the coresight_mutex. Because device1's csdev node is allocated, > coresight_make_links will be called for device0. Then in coresight_add_sysfs_link, has_conns_grp is true > for device0, but has_conns_grp is false for device1 as has_conns_grp is set to true in coresight_create_conns_sysfs_group . > The probe of device0 will fail for at this condition. > > > struct coresight_device *coresight_register(struct coresight_desc *desc) > { > ......... > mutex_lock(&coresight_mutex); > > ret = coresight_create_conns_sysfs_group(csdev); > if (!ret) > ret = coresight_fixup_device_conns(csdev); > if (!ret) > ret = coresight_fixup_orphan_conns(csdev); > if (!ret && cti_assoc_ops && cti_assoc_ops->add) > cti_assoc_ops->add(csdev); > > mutex_unlock(&coresight_mutex); > > ......... > > } > > static int coresight_fixup_device_conns(struct coresight_device *csdev) > { > .......... > conn->child_dev = > coresight_find_csdev_by_fwnode(conn->child_fwnode); The issue appears to be a constraint hidden in the lower layers of the code. Would a better solution not be to alter the code here: if (conn->child_dev && conn->child_dev->has_conns_grp) { ... } else { csdev->orphan = true; } which would mean that the connection attempt would drop through to label the connection as an orphan, to be cleaned up by the child itself when it runs coresight_fixup_orphan_conns() Regards Mike > if (conn->child_dev) { > ret = coresight_make_links(csdev, conn, > > conn->child_dev); > > .......... > > } > > > int coresight_add_sysfs_link(struct coresight_sysfs_link *info) > { > ................ > if (!info->orig->has_conns_grp || !info->target->has_conns_grp) > return -EINVAL; > > > > The probe fail issue is reproduced with reboot stress test on our internal device. > > With the patch, the probe fail issue is not reproduced. > > Thanks > > Jinlong Mao > > > > Signed-off-by: Mao Jinlong <jinlmao(a)qti.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-sysfs.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index 34d2a2d31d00..7df9eb59bf2c 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -73,8 +73,10 @@ int coresight_add_sysfs_link(struct coresight_sysfs_link *info) > if (!info->orig || !info->target || > !info->orig_name || !info->target_name) > return -EINVAL; > - if (!info->orig->has_conns_grp || !info->target->has_conns_grp) > + if (!info->orig->has_conns_grp) > return -EINVAL; > + if (!info->target->has_conns_grp) > + return -EPROBE_DEFER; > /* first link orig->target */ > ret = sysfs_add_link_to_group(&info->orig->dev.kobj, > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 8 months

OpenCSD Release v1.2.1

by Mike Leach

OpenCSD v1.2.1 has been released. This contains a bugfix affecting the sequencing of output packets around context updates - which can affect clients ability to provide correct memory images to the library in certain circumstances. Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 8 months

[PATCH] coresight: Drop unused 'none' enum value for each component

by Anshuman Khandual

CORESIGHT_DEV_TYPE_NONE/CORESIGHT_DEV_SUBTYPE_XXXX_NONE values are not used any where. Actual enumeration can start from 0. Just drop these unused enum values. Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> --- drivers/hwtracing/coresight/coresight-core.c | 3 --- include/linux/coresight.h | 5 ----- 2 files changed, 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 88653d1c06a4..af00dca8d1ac 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1278,9 +1278,6 @@ static struct attribute *coresight_source_attrs[] = { ATTRIBUTE_GROUPS(coresight_source); static struct device_type coresight_dev_type[] = { - { - .name = "none", - }, { .name = "sink", .groups = coresight_sink_groups, diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 93a2922b7653..9f445f09fcfe 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -36,7 +36,6 @@ extern struct bus_type coresight_bustype; enum coresight_dev_type { - CORESIGHT_DEV_TYPE_NONE, CORESIGHT_DEV_TYPE_SINK, CORESIGHT_DEV_TYPE_LINK, CORESIGHT_DEV_TYPE_LINKSINK, @@ -46,7 +45,6 @@ enum coresight_dev_type { }; enum coresight_dev_subtype_sink { - CORESIGHT_DEV_SUBTYPE_SINK_NONE, CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, @@ -54,21 +52,18 @@ enum coresight_dev_subtype_sink { }; enum coresight_dev_subtype_link { - CORESIGHT_DEV_SUBTYPE_LINK_NONE, CORESIGHT_DEV_SUBTYPE_LINK_MERG, CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, CORESIGHT_DEV_SUBTYPE_LINK_FIFO, }; enum coresight_dev_subtype_source { - CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, }; enum coresight_dev_subtype_helper { - CORESIGHT_DEV_SUBTYPE_HELPER_NONE, CORESIGHT_DEV_SUBTYPE_HELPER_CATU, }; -- 2.20.1

2 years, 8 months

Re: [PATCH] coresight: Defer probe when the child dev is not probed

by Suzuki K Poulose

Hi Jinlong On 28/02/2022 13:31, Mao Jinlong wrote: > From: Mao Jinlong <jinlmao(a)qti.qualcomm.com> > > It is possible that when device probe, its child device is not > probed. Then it will fail when add sysfs connection for the device. > Make device defer probe when the child device is not probed. Please could you a bit a more specific on the exact issue ? I don't see a problem with probe deferral right now, with coresight/next. For e.g., root@juno-server:~# lsmod Module Size Used by coresight 73728 0 root@juno-server:~# ls /sys/bus/coresight/devices/ root@juno-server:~# modprobe coresight-etm4x root@juno-server:~# lsmod Module Size Used by coresight_etm4x 81920 0 coresight 73728 1 coresight_etm4x root@juno-server:~# ls /sys/bus/coresight/devices/ etm0 etm1 -- Note etm2-etm5 doesn't appear -- root@juno-server:~# modprobe coresight-funnel root@juno-server:~# lsmod Module Size Used by coresight_funnel 20480 0 coresight_etm4x 81920 0 coresight 73728 2 coresight_etm4x,coresight_funnel root@juno-server:~# ls /sys/bus/coresight/devices/ etm0 etm1 -- Still don't appear --- root@juno-server:~# modprobe coresight-replicator root@juno-server:~# ls /sys/bus/coresight/devices/ etm0 etm1 root@juno-server:~# modprobe coresight-tmc -- At this stage, the devices automatically get probed and appear -- root@juno-server:~# ls /sys/bus/coresight/devices/ etm0 etm1 etm2 etm3 etm4 etm5 funnel0 funnel1 funnel2 tmc_etf0 tmc_etr0 root@juno-server:~# lsmod Module Size Used by coresight_tmc 40960 0 coresight_replicator 20480 0 coresight_funnel 20480 0 coresight_etm4x 81920 0 coresight 73728 4 coresight_tmc,coresight_etm4x,coresight_replicator,coresight_funnel So, my question is, what is this patch trying to solve ? Cheers Suzuki > > Signed-off-by: Mao Jinlong <jinlmao(a)qti.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-sysfs.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index 34d2a2d31d00..7df9eb59bf2c 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -73,8 +73,10 @@ int coresight_add_sysfs_link(struct coresight_sysfs_link *info) > if (!info->orig || !info->target || > !info->orig_name || !info->target_name) > return -EINVAL; > - if (!info->orig->has_conns_grp || !info->target->has_conns_grp) > + if (!info->orig->has_conns_grp) > return -EINVAL; > + if (!info->target->has_conns_grp) > + return -EPROBE_DEFER; > > /* first link orig->target */ > ret = sysfs_add_link_to_group(&info->orig->dev.kobj,

2 years, 8 months

[PATCH v2 RESEND 0/4] coresight: etm: Correct PID tracing for non-root namespace

by Leo Yan

If a profiling program runs in a non-root PID namespace and CoreSight driver enables PID tracing (with contextID), it can lead to mismatching issue between the context ID traced in hardware (from the root namespace) and the PIDs gathered by profiling tool (e.g. perf) in its non-root namespace. CoreSight driver has tried to address this issue for the contextID related interfaces under sysfs, but it misses to prevent user to set VMID (virtual contextID) for kernel runs in EL2 with VHE; furthermore, it misses to handle the case when the profiling tool runs in the non-root PID namespace. For this reason, this patch series is to correct contextID tracing for non-root namespace. After applied this patchset, patch 02 doesn't permit users to access virtual contextID via sysfs nodes in the non-root PID namespace, patch 03 and 04 stop to trace PID packet for non-root PID namespace. This patch series has been rebased on the mainline kernel and applied cleanly on latest commit dcb85f85fa6f ("gcc-plugins/stackleak: Use noinstr in favor of notrace"). Leo Yan (4): coresight: etm4x: Add lock for reading virtual context ID comparator coresight: etm4x: Don't use virtual contextID for non-root PID namespace coresight: etm4x: Don't trace PID for non-root PID namespace coresight: etm3x: Don't trace PID for non-root PID namespace .../coresight/coresight-etm3x-core.c | 4 +++ .../coresight/coresight-etm4x-core.c | 10 +++++-- .../coresight/coresight-etm4x-sysfs.c | 30 +++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) -- 2.25.1

2 years, 8 months

Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

by Suzuki K Poulose

On 07/02/2022 05:44, Anshuman Khandual wrote: > Hi James, > > These are all ETM4X specific changes. Something like this might be cleaner > and also more compact. Also would suggest to follow the same for subsequent > patches as well. > > coresight: etm4x: Cleanup TRCIDR0 register accesses > > Consistency with sysreg.h could be mentioned in the commit message itself. > > On 2/3/22 5:35 PM, James Clark wrote: >> This is a no-op change for style and consistency and has no effect on the >> binary produced by gcc-11. > > This patch adds register definitions, helper macros as well. Please expand > the commit message to add more details. This is too short, for the change > it creates. BTW why is it necessary to mention GCC version number here. > >> >> Signed-off-by: James Clark <james.clark(a)arm.com> >> --- >> .../coresight/coresight-etm4x-core.c | 36 +++++-------------- >> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++ >> drivers/hwtracing/coresight/coresight-priv.h | 5 +++ >> 3 files changed, 30 insertions(+), 28 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index e2eebd865241..107e81948f76 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info) >> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); >> >> /* INSTP0, bits[2:1] P0 tracing support field */ >> - if (BMVAL(etmidr0, 1, 2) == 0b11) >> - drvdata->instrp0 = true; >> - else >> - drvdata->instrp0 = false; >> - >> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11); >> /* TRCBB, bit[5] Branch broadcast tracing support bit */ >> - if (BMVAL(etmidr0, 5, 5)) >> - drvdata->trcbb = true; >> - else >> - drvdata->trcbb = false; >> - >> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); >> /* TRCCOND, bit[6] Conditional instruction tracing support bit */ >> - if (BMVAL(etmidr0, 6, 6)) >> - drvdata->trccond = true; >> - else >> - drvdata->trccond = false; >> - >> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); >> /* TRCCCI, bit[7] Cycle counting instruction bit */ >> - if (BMVAL(etmidr0, 7, 7)) >> - drvdata->trccci = true; >> - else >> - drvdata->trccci = false; >> - >> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); >> /* RETSTACK, bit[9] Return stack bit */ >> - if (BMVAL(etmidr0, 9, 9)) >> - drvdata->retstack = true; >> - else >> - drvdata->retstack = false; >> - >> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); >> /* NUMEVENT, bits[11:10] Number of events field */ >> - drvdata->nr_event = BMVAL(etmidr0, 10, 11); >> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT); >> /* QSUPP, bits[16:15] Q element support field */ >> - drvdata->q_support = BMVAL(etmidr0, 15, 16); >> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP); >> /* TSSIZE, bits[28:24] Global timestamp size field */ >> - drvdata->ts_size = BMVAL(etmidr0, 24, 28); >> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE); >> >> /* maximum size of resources */ >> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 3c4d69b096ca..2bd8ad953b8e 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -130,6 +130,23 @@ >> >> #define TRCRSR_TA BIT(12) >> >> +/* >> + * Bit positions of registers that are defined above, in the sysreg.h style >> + * of _MASK, _SHIFT and BIT(). >> + */ > > ^^^ not really necessary. Instead the format requirement for below mentioned > CORESIGHT_REG_VAL() macro might be relevant and should be mentioned. > >> +#define TRCIDR0_INSTP0_SHIFT 1 >> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0) >> +#define TRCIDR0_TRCBB BIT(5) >> +#define TRCIDR0_TRCCOND BIT(6) >> +#define TRCIDR0_TRCCCI BIT(7) >> +#define TRCIDR0_RETSTACK BIT(9) >> +#define TRCIDR0_NUMEVENT_SHIFT 10 >> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0) >> +#define TRCIDR0_QSUPP_SHIFT 15 >> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0) >> +#define TRCIDR0_TSSIZE_SHIFT 24 >> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0) >> + >> /* >> * System instructions to access ETM registers. >> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions >> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h >> index ff1dd2092ac5..1452c6038421 100644 >> --- a/drivers/hwtracing/coresight/coresight-priv.h >> +++ b/drivers/hwtracing/coresight/coresight-priv.h >> @@ -36,6 +36,11 @@ >> >> #define TIMEOUT_US 100 >> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) >> +/* >> + * Extract a field from a register where field is #defined in the form >> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT >> + */ > > Looking at the usage, <register_name> is already embedded in <filed_name>. So > it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register > name should be passed as separate argument (which actually might be better). > > REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE) I don't see much difference here. So I am fine either way. > > with some restructuring in the comment .. > > /* > * Extract a field from a coresight register > * > * Required fields are defined as macros like the following > * > * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT > */ > >> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT) > > This is too generic to be in a coresight header or it should just be > named CORESIGHT_REG_VAL() instead, making it more specific for here. > > The build should fail in case any required macro definition is absent. > I guess no more fortification is required in case macros are missing. > > However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h> > just before all the dependent SHIFT/MASK register field definition > starts. Not necessarily. CORESIGHT_REG_VAL() is a generic function and doesn't have anything specific to do with etm4x. We could reuse that for cleaning up other drivers in CoreSight. Cheers Suzuki

2 years, 8 months

[PATCH 0/1] perf: Set build-id using build-id header on new mmap records

by James Clark

Hi, We are seeing an issue with doing Coresight decode off target where initially the correct dso from ~/.debug is used, but after a new thread in the perf.data file is passed with its mmap record, the local version of the dso is picked up instead. This happens if the binary exists in the same path on both devices, for example /bin/ls. Initially when parsing the build-ids in the header, the dso for /bin/ls will be created, and the file will correctly point to ~/.debug/bin/ls/2f15ad836be3339dec0e2e6a3c637e08e48aacbd/elf, but for any new threads or mmaps that are also for /bin/ls, they will not have a build-id set so they point to /bin/ls on the local machine rather than the debug folder. To fix this I made it possible to look up which existing dsos have build id's set that originate from the header and then copy that build-id onto the new dso if the name matches. Another way to do it would be to stop comparing the mmap id so it matches on filename only, but I think we do want to differentiate between different mmaps, even if they have the same name, which is how it works in this version. Applies to perf/core 859f7e4554 Thanks James James Clark (1): perf: Set build-id using build-id header on new mmap records tools/perf/util/dso.h | 1 + tools/perf/util/header.c | 1 + tools/perf/util/map.c | 16 ++++++++++++++-- 3 files changed, 16 insertions(+), 2 deletions(-) -- 2.28.0

2 years, 8 months

[PATCH 1/2] perf: cs-etm: No-op refactor of synth opt usage

by James Clark

sample_branches and sample_instructions are already saved in the synth_opts struct. Other usages like synth_opts.last_branch don't save a value, so make this more consistent by always going through synth_opts and not saving duplicate values. Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/util/cs-etm.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 4f672f7d008c..796a065a500e 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -50,8 +50,6 @@ struct cs_etm_auxtrace { u8 timeless_decoding; u8 snapshot_mode; u8 data_queued; - u8 sample_branches; - u8 sample_instructions; int num_cpu; u64 latest_kernel_timestamp; @@ -410,8 +408,8 @@ static void cs_etm__packet_swap(struct cs_etm_auxtrace *etm, { struct cs_etm_packet *tmp; - if (etm->sample_branches || etm->synth_opts.last_branch || - etm->sample_instructions) { + if (etm->synth_opts.branches || etm->synth_opts.last_branch || + etm->synth_opts.instructions) { /* * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for * the next incoming packet. @@ -1365,7 +1363,6 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, err = cs_etm__synth_event(session, &attr, id); if (err) return err; - etm->sample_branches = true; etm->branches_sample_type = attr.sample_type; etm->branches_id = id; id += 1; @@ -1389,7 +1386,6 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, err = cs_etm__synth_event(session, &attr, id); if (err) return err; - etm->sample_instructions = true; etm->instructions_sample_type = attr.sample_type; etm->instructions_id = id; id += 1; @@ -1420,7 +1416,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, tidq->prev_packet->last_instr_taken_branch) cs_etm__update_last_branch_rb(etmq, tidq); - if (etm->sample_instructions && + if (etm->synth_opts.instructions && tidq->period_instructions >= etm->instructions_sample_period) { /* * Emit instruction sample periodically @@ -1503,7 +1499,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, } } - if (etm->sample_branches) { + if (etm->synth_opts.branches) { bool generate_sample = false; /* Generate sample for tracing on packet */ @@ -1582,7 +1578,7 @@ static int cs_etm__flush(struct cs_etm_queue *etmq, } - if (etm->sample_branches && + if (etm->synth_opts.branches && tidq->prev_packet->sample_type == CS_ETM_RANGE) { err = cs_etm__synth_branch_sample(etmq, tidq); if (err) -- 2.28.0

2 years, 8 months

Re: [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250

by Mike Leach

Hi, It would appear here that normal coresight funnels appear between tpdm and tpda devices. This is contrary to my understanding of your hardware and the descriptions and conversations we had in patch 00/10 in this set. trace path appears to be tpdm_mm => funnel@6c0b000 => funnel@6c2d000 => tpda@6004000 => funnel@6005000 => rest of ATB The documentation states that the TPDA is responsible for for funneling and packetising - so why do we have extra funnels? I have no way of knowing if that topology is right or wrong. Are the funnels between tpdm and tpda actual coresight funnels, a component that is register compatible with CS funnels but designed for the TPDM / TPDA transport, or the funnels are being used, but without driving ATID from the sources. It is difficult to review this set without better information on the hardware represented. Regards Mike On Wed, 9 Feb 2022 at 10:58, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > Add coresight device tree for sm8250. STM/ETM/TPDM are added. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++ > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + > 2 files changed, 692 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > new file mode 100644 > index 000000000000..732dab7f8674 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi > @@ -0,0 +1,690 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +&soc { > + > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x06002000 0 0x1000>, > + <0 0x16280000 0 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06041000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@6 { > + reg = <6>; > + funnel_in0_in_funnel_qatb: endpoint { > + remote-endpoint = > + <&funnel_qatb_out_funnel_in0>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6042000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06042000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <4>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6b04000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + arm,primecell-periphid = <0x000bb908>; > + > + reg = <0 0x6b04000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel_swao_in_funnel_merg: endpoint { > + remote-endpoint= > + <&funnel_merg_out_funnel_swao>; > + }; > + }; > + }; > + > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06045000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_merg_out_funnel_swao: endpoint { > + remote-endpoint = <&funnel_swao_in_funnel_merg>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@2 { > + reg = <1>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + replicator@6046000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0 0x06046000 0 0x1000>; > + > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + replicator_out: endpoint { > + remote-endpoint = <&etr_in>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_cx_in_swao_out: endpoint { > + remote-endpoint = <&replicator_swao_out_cx_in>; > + }; > + }; > + }; > + }; > + > + replicator@6b06000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0 0x06b06000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + replicator_swao_out_cx_in: endpoint { > + remote-endpoint = <&replicator_cx_in_swao_out>; > + }; > + }; > + }; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = <&etf_out>; > + }; > + }; > + }; > + }; > + > + etf@6b05000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x6b05000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + etf_out: endpoint { > + remote-endpoint = > + <&replicator_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <0>; > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etr@6048000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x06048000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,scatter-gather; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = > + <&replicator_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07040000 0 0x1000>; > + > + cpu = <&CPU0>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07140000 0 0x1000>; > + > + cpu = <&CPU1>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07240000 0 0x1000>; > + > + cpu = <&CPU2>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07340000 0 0x1000>; > + > + cpu = <&CPU3>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07440000 0 0x1000>; > + > + cpu = <&CPU4>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07540000 0 0x1000>; > + > + cpu = <&CPU5>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07640000 0 0x1000>; > + > + cpu = <&CPU6>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07740000 0 0x1000>; > + > + cpu = <&CPU7>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07800000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07810000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port@1 { > + reg = <0>; > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > + > + tpdm_mm: mm.tpdm@6c08000 { > + compatible = "arm,primecell"; > + reg = <0 0x6c08000 0 0x1000>; > + reg-names = "tpdm-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + qcom,msr-fix-req; > + > + out-ports { > + port { > + tpdm_mm_out_funnel_dl_mm: endpoint { > + remote-endpoint = > + <&funnel_dl_mm_in_tpdm_mm>; > + }; > + }; > + }; > + }; > + > + funnel@6c0b000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + > + reg = <0 0x6c0b000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_dl_mm_out_funnel_dl_center: endpoint { > + remote-endpoint = > + <&funnel_dl_center_in_funnel_dl_mm>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@3 { > + reg = <3>; > + funnel_dl_mm_in_tpdm_mm: endpoint { > + remote-endpoint = > + <&tpdm_mm_out_funnel_dl_mm>; > + }; > + }; > + }; > + }; > + > + funnel@6c2d000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + > + reg = <0 0x6c2d000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port { > + tpdm_mm_out_tpda9: endpoint { > + remote-endpoint = > + <&tpda_9_in_tpdm_mm>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@2 { > + reg = <2>; > + funnel_dl_center_in_funnel_dl_mm: endpoint { > + remote-endpoint = > + <&funnel_dl_mm_out_funnel_dl_center>; > + }; > + }; > + }; > + }; > + > + tpda@6004000 { > + compatible = "arm,primecell"; > + reg = <0 0x6004000 0 0x1000>; > + reg-names = "tpda-base"; > + > + qcom,tpda-atid = <65>; > + > + qcom,dsb-elem-size = <9 32>, > + <10 32>, > + <14 32>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + reg = <0>; > + tpda_out_funnel_qatb: endpoint { > + remote-endpoint = > + <&funnel_qatb_in_tpda>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@9 { > + reg = <9>; > + tpda_9_in_tpdm_mm: endpoint { > + remote-endpoint = > + <&tpdm_mm_out_tpda9>; > + }; > + }; > + }; > + }; > + > + funnel@6005000 { > + compatible = "arm,primecell"; > + > + reg = <0 0x6005000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel_qatb_out_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel_in0_in_funnel_qatb>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + funnel_qatb_in_tpda: endpoint { > + remote-endpoint = > + <&tpda_out_funnel_qatb>; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 5617a46e5ccd..d1837e3df30a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -5323,3 +5323,5 @@ > }; > }; > }; > + > +#include "sm8250-coresight.dtsi" > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 8 months

Re: [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support

by Mike Leach

Hi This patch does not apply cleanly:- ======================================= git apply -v ../patch.in/qcom/qcom-05.patch Checking patch drivers/hwtracing/coresight/coresight-tpdm.c... error: while searching for: DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); /** TPDM enable operations **/ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { error: patch failed: drivers/hwtracing/coresight/coresight-tpdm.c:20 error: drivers/hwtracing/coresight/coresight-tpdm.c: patch does not apply Checking patch drivers/hwtracing/coresight/coresight-tpdm.h... ======================================= In patch 3 - the first time coresight-tpdm.c. is added the comment line is /* TPDM enable operations */ Note the single * in the comment. This would seem to indicate missing intermediate patches, or patches from different trees / times. A coherent patch set is needed for review Regards Mike On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > > TPDM serves as data collection component for various dataset types. > DSB(Discrete Single Bit) is one of the dataset types. DSB subunit > can be enabled for data collection by writing 1 to the first bit of > DSB_CR register. This change is to add enable/disable function for > DSB dataset by writing DSB_CR register. > > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-tpdm.c | 57 ++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++++++ > 2 files changed, 78 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 51b8b17e6a80..c6480b7389b0 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -20,7 +20,28 @@ > > DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); > > +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) > +{ > + u32 val; > + > + /* Set the enable bit of DSB control register to 1 */ > + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); > + val = val | BIT(0); > + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); > +} > + > /** TPDM enable operations **/ > +static void _tpdm_enable(struct tpdm_drvdata *drvdata) > +{ > + CS_UNLOCK(drvdata->base); > + > + /* Check if DSB datasets is present for TPDM. */ > + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) > + tpdm_enable_dsb(drvdata); > + > + CS_LOCK(drvdata->base); > +} > + > static int tpdm_enable(struct coresight_device *csdev, > struct perf_event *event, u32 mode) > { > @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, > return -EBUSY; > } > > + _tpdm_enable(drvdata); > drvdata->enable = true; > mutex_unlock(&drvdata->lock); > > @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev, > return 0; > } > > +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) > +{ > + u32 val; > + > + /* Set the enable bit of DSB control register to 0 */ > + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); > + val = val & ~BIT(0); > + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); > +} > + > /** TPDM disable operations **/ > +static void _tpdm_disable(struct tpdm_drvdata *drvdata) > +{ > + CS_UNLOCK(drvdata->base); > + > + /* Check if DSB datasets is present for TPDM. */ > + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) > + tpdm_disable_dsb(drvdata); > + > + CS_LOCK(drvdata->base); > + > +} > + > static void tpdm_disable(struct coresight_device *csdev, > struct perf_event *event) > { > @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev, > return; > } > > + _tpdm_disable(drvdata); > drvdata->enable = false; > mutex_unlock(&drvdata->lock); > > @@ -76,7 +121,19 @@ static const struct coresight_ops tpdm_cs_ops = { > > static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) > { > + int i; > + u32 pidr; > + > drvdata->traceid = coresight_get_system_trace_id(); > + > + CS_UNLOCK(drvdata->base); > + /* Get the datasets present on the TPDM. */ > + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); > + for (i = 0; i < TPDM_DATASETS; i++) { > + if (pidr & BIT(i)) > + __set_bit(i, drvdata->datasets); > + } > + CS_LOCK(drvdata->base); > } > > static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index 2effbabf349b..cb3ddc6c89ae 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -6,6 +6,25 @@ > #ifndef _CORESIGHT_CORESIGHT_TPDM_H > #define _CORESIGHT_CORESIGHT_TPDM_H > > +/* The max number of the datasets that TPDM supports */ > +#define TPDM_DATASETS 7 > + > +/* DSB Subunit Registers */ > +#define TPDM_DSB_CR (0x780) > + > +/** > + * This enum is for PERIPHIDR0 register of TPDM. > + * The fields [6:0] of PERIPHIDR0 are used to determine what > + * interfaces and subunits are present on a given TPDM. > + * > + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 > + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 > + */ > +enum tpdm_dataset { > + TPDM_DS_IMPLDEF, > + TPDM_DS_DSB, > +}; > + > /** > * struct tpdm_drvdata - specifics associated to an TPDM component > * @base: memory mapped base address for this component. > @@ -13,6 +32,7 @@ > * @csdev: component vitals needed by the framework. > * @lock: lock for the enable value. > * @enable: enable status of the component. > + * @datasets: The datasets types present of the TPDM. > * @traceid: value of the current ID for this component. > */ > > @@ -22,6 +42,7 @@ struct tpdm_drvdata { > struct coresight_device *csdev; > struct mutex lock; > bool enable; > + DECLARE_BITMAP(datasets, TPDM_DATASETS); > int traceid; > }; > > -- > 2.17.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 8 months

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