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Re: [PATCH v2] coresight: trbe: Move check for kernel page table isolation from EL0 to probe

by Suzuki K Poulose

On 03/02/2022 19:01, Sudeep Holla wrote: > Currently with the check present in the module initialisation, it shouts > on all the systems irrespective of presence of coresight trace buffer > extensions. > > Similar to Arm SPE perf driver, move the check for kernel page table > isolation from EL0 to the device probe stage instead of the module > initialisation so that it complains only on the systems that support TRBE. > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> > Cc: coresight(a)lists.linaro.org > Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> Thanks, I have now queued this. https://git.kernel.org/coresight/c/ebbce265bba164c4f0d5271c277a540bd3b2fd3c Kind regards Suzuki

2 years, 9 months

[PATCH 00/15] Make ETM register accesses consistent with sysreg.h

by James Clark

While working on the branch broadcast change I found it difficult to search for usages of registers and fields because of the magic numbers. I also found it difficult to decide which style to make new code in because of the varying ones used. There was also a code review comment from Suzuki about replacing a magic number so I'm proposing to refactor as many as possible into the style used in sysreg.h which seems to be the new and most consistently used method. For example it was used in the SPE and TRBE drivers. This isn't an exhaustive refactor, but it does get all the basic accesses. There are a couple of odd other cases remaining, mainly in the ETM3x code. These can be found by searching for BMVAL. There is one compromise to ensure this is a complete no-op and has binary equivalence with the old version. I needed to keep two register accesses here, where something like etmidr0 & TRCIDR0_INSTP0_LOAD_STORE would be better: - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) - drvdata->instrp0 = true; - else - drvdata->instrp0 = false; - + drvdata->instrp0 = !!((REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b01) && + (REG_VAL(etmidr0, TRCIDR0_INSTP0) & 0b10)); I think this change fixes quite a few issues like: * Some registers aren't referred to by name but a different variable name. For example eventctrl1 in mode_store() where TRCEVENTCTL1R isn't mentioned in that function. * Some bits aren't referred to by the name in the manual, even in the comments. For example TRCCONFIGR.RS only occurs as /* bit[12], Return stack enable bit */. * Some bits in the same register are referred to either as magic numbers or the publicly exported config macros, neiher of which are consistent with any other register accesses. For example config->cfg |= BIT(11); config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); * Some fields are already partially referred to in the sysfs.h style way: TRCVICTLR_EXLEVEL_... etc. But other fields in the same register are not * Some fields are magic numbers that are repeated many times in different functions. For example vinst_ctrl |= BIT(9) * Some fields were referred to by magic numbers, even when there were already existing #defines. For example ETMTECR1_INC_EXC * Another benefit is that the #defines could be automatically checked against the reference manual because the style is uniform. Testing ======= To test this I used gcc-11 which doesn't have a quirk about changing register widths in some cases (as in w -> x). I also used elf_diff which showed me exactly where I'd made a mistake when I did (https://github.com/noseglasses/elf_diff). But now that there is no difference, objdump and diff also work for validation. make CC=gcc-11 modules diff <(objdump -d drivers/hwtracing/coresight/coresight-etm4x.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight-etm4x.ko) diff <(objdump -d drivers/hwtracing/coresight/coresight.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight.ko) And for ETM3x (doesn't need gcc 11): make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- modules diff <(objdump -d drivers/hwtracing/coresight/coresight-etm3x.ko) <(objdump -d ../linux2/drivers/hwtracing/coresight/coresight-etm3x.ko) When there are no differences, the diff output looks like this with only the filename listed: < drivers/hwtracing/coresight/coresight-etm4x.ko: file format elf64-littleaarch64 --- > ../linux2/drivers/hwtracing/coresight/coresight-etm4x.ko: file format elf64-littleaarch64 Applies to coresight/next 30d1f1c71b James Clark (15): coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR2 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR3 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR4 register accesses consistent with sysreg.h coresight: Make ETM4x TRCIDR5 register accesses consistent with sysreg.h coresight: Make ETM4x TRCCONFIGR register accesses consistent with sysreg.h coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with sysreg.h coresight: Make ETM4x TRCSTALLCTLR register accesses consistent with sysreg.h coresight: Make ETM4x TRCVICTLR register accesses consistent with sysreg.h coresight: Make ETM3x ETMTECR1 register accesses consistent with sysreg.h coresight: Make ETM4x TRCACATRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCSSPCICRn register accesses consistent with sysreg.h coresight: Make ETM4x TRCBBCTLR register accesses consistent with sysreg.h coresight: Make ETM4x TRCRSCTLRn register accesses consistent with sysreg.h .../coresight/coresight-etm3x-core.c | 2 +- .../coresight/coresight-etm3x-sysfs.c | 2 +- .../coresight/coresight-etm4x-core.c | 135 +++++-------- .../coresight/coresight-etm4x-sysfs.c | 178 +++++++++--------- drivers/hwtracing/coresight/coresight-etm4x.h | 159 ++++++++++++++-- drivers/hwtracing/coresight/coresight-priv.h | 1 + 6 files changed, 283 insertions(+), 194 deletions(-) -- 2.28.0

2 years, 9 months

Re: [PATCH] coresight: trbe: Move check for kernelspace unmapped at EL0 to probe

by Suzuki K Poulose

On 03/02/2022 12:04, Sudeep Holla wrote: > On Thu, Feb 03, 2022 at 11:55:58AM +0530, Anshuman Khandual wrote: >> >> >> On 2/1/22 5:52 PM, Sudeep Holla wrote: >>> Currently with the check present in the module initialisation, it shouts >>> on all the systems irrespective of presence of coresight trace buffer >>> extensions. >> >> IIUC a system with CONFIG_CORESIGHT_TRBE enabled but without a TRBE DT >> i.e "arm,trace-buffer-extension" complains about kernel space unmapping >> at EL0 (even though it does not even really have TRBE HW to initialize). > > > Correct. Basically, this error will be seen on all systems(DT and ACPI) when > the module is compiled. It really doesn't matter if the system supports TRBE. > >>> >>> Similar to Arm SPE perf driver, move the check for kernelspace unmapping >>> when running at EL0 to the device probe instead of module initialisation. >> >> Makes sense. >> > > Thanks. > >>> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> Cc: Mike Leach <mike.leach(a)linaro.org> >>> Cc: Leo Yan <leo.yan(a)linaro.org> >>> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> Cc: coresight(a)lists.linaro.org >>> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> >>> --- >>> drivers/hwtracing/coresight/coresight-trbe.c | 10 +++++----- >>> 1 file changed, 5 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>> index 276862c07e32..3fe2ce1ba5bf 100644 >>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>> @@ -1423,6 +1423,11 @@ static int arm_trbe_device_probe(struct platform_device *pdev) >>> struct device *dev = &pdev->dev; >>> int ret; >>> >> >> Could you please add a similar comment like SPE driver regarding how >> the TRBE buffer will be inaccessible, if kernel gets unmapped at EL0 >> and trace capture will terminate. >> > > Sure I can add that. But if the device probe fails, will you be able to even > start the trace capture, sorry I didn't get what you mean by "trace capture > will terminate". I assume it must be "trace capture is not possible or not > allowed" IIUC. > "Trace capture is not possible with kernel page table isolation" is good enough. Thanks for making these changes Cheers Suzuki

2 years, 9 months

[PATCH 0/1] coresight: no-op refactor to make INSTP0 check more idiomatic

by James Clark

In preparation for the bigger register refactor, simplify one of the accesses otherwise it looked even more obfuscated after the refactor. This can't be included in the main set because it causes a small change in the binary, although functionally this refactor is also a no-op. Applies to coresight/next 30d1f1c71b James Clark (1): coresight: no-op refactor to make INSTP0 check more idiomatic drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.28.0

2 years, 9 months

[PATCH v2 0/6] coresight: syscfg: Extend configfs for config load

by Mike Leach

This set extends the configfs support to allow loading and unloading of configurations as binary files via configfs. Additional attributes - load, unload and last_load_status are provided to implement the load functionality. Routines to generate binary configuration files are supplied in ./samples/coresight. Example generator and reader applications are provided. Additional Makefile.host supplied to build the generator and reader applications on the host system separate from a cross compiled kernel. Documentation is updated to describe feature usage. Applies and tested on latest coresight/next that includes the previous coresight configuration dynamic load patchset. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (6): coresight: configfs: Add in functionality for load via configfs coresight: configfs: Add in binary attributes to load files coresight: configfs: Modify config files to allow userspace use coresight: samples: Add an example config writer for configfs load coresight: samples: Add coresight file reader sample program Documentation: coresight: docs for config load via configfs .../trace/coresight/coresight-config.rst | 151 +++++- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-config-file.c | 472 ++++++++++++++++++ .../coresight/coresight-config-file.h | 158 ++++++ .../hwtracing/coresight/coresight-config.h | 38 ++ .../coresight/coresight-syscfg-configfs.c | 148 +++++- .../coresight/coresight-syscfg-configfs.h | 8 + .../hwtracing/coresight/coresight-syscfg.c | 36 ++ .../hwtracing/coresight/coresight-syscfg.h | 2 + samples/coresight/Makefile | 23 + samples/coresight/Makefile.host | 47 ++ samples/coresight/coresight-cfg-bufw.c | 302 +++++++++++ samples/coresight/coresight-cfg-bufw.h | 24 + samples/coresight/coresight-cfg-file-read.c | 191 +++++++ samples/coresight/coresight-cfg-filegen.c | 89 ++++ 15 files changed, 1677 insertions(+), 14 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-file.c create mode 100644 drivers/hwtracing/coresight/coresight-config-file.h create mode 100644 samples/coresight/Makefile.host create mode 100644 samples/coresight/coresight-cfg-bufw.c create mode 100644 samples/coresight/coresight-cfg-bufw.h create mode 100644 samples/coresight/coresight-cfg-file-read.c create mode 100644 samples/coresight/coresight-cfg-filegen.c -- 2.17.1

2 years, 9 months

Re: [PATCH v2] coresight: syscfg: Fix memleak on registration failure in cscfg_create_device

by Mathieu Poirier

On Mon, Jan 24, 2022 at 12:41:21PM +0000, Miaoqian Lin wrote: > device_register() calls device_initialize(), > according to doc of device_initialize: > > Use put_device() to give up your reference instead of freeing > * @dev directly once you have called this function. > > To prevent potential memleak, use put_device() for error handling. > > Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> > --- > Changes in v2: > - simply call put_device() instead of cscfg_dev_release() in the error > path of cscfg_create_device. > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 43054568430f..c30989e0675f 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -791,7 +791,7 @@ static int cscfg_create_device(void) > > err = device_register(dev); > if (err) > - cscfg_dev_release(dev); > + put_device(dev); Applied. Thanks, Mathieu > > create_dev_exit_unlock: > mutex_unlock(&cscfg_mutex); > -- > 2.17.1 >

2 years, 9 months

[PATCH v2 0/1] coresight: Fix TRCCONFIGR.QE sysfs interface

by James Clark

Changes since v1: * Add Mike's reviewed by tag * Also make it impossible to write the reserved value of 0b10, regardless of what is supplied by the user. James Clark (1): coresight: Fix TRCCONFIGR.QE sysfs interface drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.28.0

2 years, 9 months

Re: [RFC PATCH] ACPI / amba: Skip creating amba device when associated cpu is not online

by Suzuki K Poulose

On 28/01/2022 15:28, Robin Murphy wrote: > On 2022-01-28 11:00, Suzuki K Poulose wrote: >> Hi Xiang >> >> On 07/01/2022 08:41, chenxiang wrote: >>> From: Xiang Chen <chenxiang66(a)hisilicon.com> >>> >>> If not up all the cpus with command line "maxcpus=x", system will be >>> blocked. >>> We find that some amba devices such as ETM devices, are associated with >>> special cpus, and if the cpu is not up, the register of associated >>> device >>> is not allowed to access. BIOS reports all the ETM device nodes and a >>> amba device is created for every ETM device, so even if one cpu is >>> not up, >>> the amba device will still be created for the associated device, and >>> also >>> the register of device (pid and cid) will be accessed when adding amba >>> device which will cause the issue. >>> To fix it, skip creating amba device if it is associated with a cpu >>> which >>> is not online. >> >> I understand the issue. We do not have an issue at least on DT based >> platforms with a similar environment (Juno). The key is the power >> management for the components. >> >> There are two separate issues at play here : >> >> 1) Power management with ACPI. I believe there is a solution in progress >> to address this. >> >> 2) The ETM is in the same power domain as that of the CPU and normal >> device power management may not work without the CPU being online. >> >> 3) Additionally we have other issue of supporting system instructions >> with ACPI, which do not appear on the AMBA bus. >> >> Considering all of these, the ideal solution is to : >> >> 1) Implement power management for ACPI, which is anyway in progress >> (at least for SCMI based systems) >> 2) Move the ETM driver away from the AMBA framework. That would make >> the CPU online problem and the (3) above easier to solve. >> Anshuman is going to look into this. >> >> In the meantime, we could have this temporary fix in and solve it >> forever by moving away from the AMBA. > > Out of curiosity, what happens when you boot with "maxcpus=" and then > manually bring up the extra cpus from userspace later? Is there a chance > that tracing will explode if some online CPUs have ETM initialised but > others don't? No. At the moment, we don't bring the ETMs online for hotplugged CPUs. i.e., ETM is not registered for the CPU. So any attempt to trace on that CPU will fail. Probe deferral doesn't go beyond the userspace init. But we plan to add hotplug support, by defering the ETM probe. At present, the ETMs are bound to the AMBA frame work and I am not sure if there is a way to explicitly trigger a probe from the AMBA layer on CPU hotplug. The other option is to always create the AMBA device and defer the "etm" probe to a cpu hotplug notifier in the ETM driver. This is something we plan to add. Suzuki > > Robin. > >>> >>> Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> >>> --- >>> drivers/acpi/acpi_amba.c | 36 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 36 insertions(+) >>> >>> diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c >>> index ab8a4e0191b1..2369198f734b 100644 >>> --- a/drivers/acpi/acpi_amba.c >>> +++ b/drivers/acpi/acpi_amba.c >>> @@ -16,6 +16,7 @@ >>> #include <linux/ioport.h> >>> #include <linux/kernel.h> >>> #include <linux/module.h> >>> +#include <acpi/processor.h> >>> #include "internal.h" >>> @@ -45,6 +46,35 @@ static void amba_register_dummy_clk(void) >>> clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL); >>> } >>> +static int acpi_handle_to_cpuid(acpi_handle handle) >>> +{ >>> + int cpu = -1; >>> + struct acpi_processor *pr; >>> + >>> + for_each_possible_cpu(cpu) { >>> + pr = per_cpu(processors, cpu); >>> + if (pr && pr->handle == handle) >>> + break; >>> + } >>> + >>> + return cpu; >>> +} >>> + >> >> Please could we reuse the function in coresight-platform.c ? >> i.e, move it to a generic location and share it, rather than >> duplicating it ? >> >> >>> +static int acpi_dev_get_cpu(struct acpi_device *adev) >>> +{ >>> + acpi_handle cpu_handle; >>> + acpi_status status; >>> + int cpu; >>> + >>> + status = acpi_get_parent(adev->handle, &cpu_handle); >>> + if (ACPI_FAILURE(status)) >>> + return -1; >>> + cpu = acpi_handle_to_cpuid(cpu_handle); >>> + if (cpu >= nr_cpu_ids) >>> + return -1; >>> + return cpu; >>> +} >>> + >>> static int amba_handler_attach(struct acpi_device *adev, >>> const struct acpi_device_id *id) >>> { >>> @@ -54,11 +84,17 @@ static int amba_handler_attach(struct acpi_device >>> *adev, >>> bool address_found = false; >>> int irq_no = 0; >>> int ret; >>> + int cpu; >>> /* If the ACPI node already has a physical device attached, >>> skip it. */ >>> if (adev->physical_node_count) >>> return 0; >>> + /* If the cpu associated with the device is not online, skip it. */ >>> + cpu = acpi_dev_get_cpu(adev); >>> + if (cpu >= 0 && !cpu_online(cpu)) >>> + return 0; >>> + >> >> Except for the comment above, the patch looks good to me. >> >> Suzuki >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel(a)lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

2 years, 9 months

Re: [PATCH V3 RESEND 0/7] coresight: trbe: Workaround Cortex-A510 erratas

by Mathieu Poirier

On Fri, 28 Jan 2022 at 03:51, Catalin Marinas <catalin.marinas(a)arm.com> wrote: > > Hi Mathieu, > > On Thu, Jan 27, 2022 at 01:22:20PM -0700, Mathieu Poirier wrote: > > On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > > > Anshuman Khandual (7): > > > arm64: Add Cortex-A510 CPU part definition > > > arm64: errata: Add detection for TRBE ignored system register writes > > > arm64: errata: Add detection for TRBE invalid prohibited states > > > arm64: errata: Add detection for TRBE trace data corruption > > > coresight: trbe: Work around the ignored system register writes > > > coresight: trbe: Work around the invalid prohibited states > > > coresight: trbe: Work around the trace data corruption > > > > > > Documentation/arm64/silicon-errata.rst | 6 + > > > arch/arm64/Kconfig | 59 ++++++++++ > > > arch/arm64/include/asm/cputype.h | 2 + > > > arch/arm64/kernel/cpu_errata.c | 27 +++++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > > > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > > > 7 files changed, 183 insertions(+), 36 deletions(-) > > > > I have applied this set and sent a pull request to Catalin for the arm64 > > portion. > > Well, I'm happy for the whole series to go in via Greg's tree or however > the coresight patches go in (that's why I acked them). The last three > patches depend on the first four, so you might as well send them all > together. I'd split the series only if there's a conflict with the arm64 > tree (I haven't checked). > Very well - thanks for the follow up. > -- > Catalin

2 years, 9 months

Re: [RFC PATCH] ACPI / amba: Skip creating amba device when associated cpu is not online

by Suzuki K Poulose

Hi Xiang On 07/01/2022 08:41, chenxiang wrote: > From: Xiang Chen <chenxiang66(a)hisilicon.com> > > If not up all the cpus with command line "maxcpus=x", system will be > blocked. > We find that some amba devices such as ETM devices, are associated with > special cpus, and if the cpu is not up, the register of associated device > is not allowed to access. BIOS reports all the ETM device nodes and a > amba device is created for every ETM device, so even if one cpu is not up, > the amba device will still be created for the associated device, and also > the register of device (pid and cid) will be accessed when adding amba > device which will cause the issue. > To fix it, skip creating amba device if it is associated with a cpu which > is not online. I understand the issue. We do not have an issue at least on DT based platforms with a similar environment (Juno). The key is the power management for the components. There are two separate issues at play here : 1) Power management with ACPI. I believe there is a solution in progress to address this. 2) The ETM is in the same power domain as that of the CPU and normal device power management may not work without the CPU being online. 3) Additionally we have other issue of supporting system instructions with ACPI, which do not appear on the AMBA bus. Considering all of these, the ideal solution is to : 1) Implement power management for ACPI, which is anyway in progress (at least for SCMI based systems) 2) Move the ETM driver away from the AMBA framework. That would make the CPU online problem and the (3) above easier to solve. Anshuman is going to look into this. In the meantime, we could have this temporary fix in and solve it forever by moving away from the AMBA. > > Signed-off-by: Xiang Chen <chenxiang66(a)hisilicon.com> > --- > drivers/acpi/acpi_amba.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c > index ab8a4e0191b1..2369198f734b 100644 > --- a/drivers/acpi/acpi_amba.c > +++ b/drivers/acpi/acpi_amba.c > @@ -16,6 +16,7 @@ > #include <linux/ioport.h> > #include <linux/kernel.h> > #include <linux/module.h> > +#include <acpi/processor.h> > > #include "internal.h" > > @@ -45,6 +46,35 @@ static void amba_register_dummy_clk(void) > clk_register_clkdev(amba_dummy_clk, "apb_pclk", NULL); > } > > +static int acpi_handle_to_cpuid(acpi_handle handle) > +{ > + int cpu = -1; > + struct acpi_processor *pr; > + > + for_each_possible_cpu(cpu) { > + pr = per_cpu(processors, cpu); > + if (pr && pr->handle == handle) > + break; > + } > + > + return cpu; > +} > + Please could we reuse the function in coresight-platform.c ? i.e, move it to a generic location and share it, rather than duplicating it ? > +static int acpi_dev_get_cpu(struct acpi_device *adev) > +{ > + acpi_handle cpu_handle; > + acpi_status status; > + int cpu; > + > + status = acpi_get_parent(adev->handle, &cpu_handle); > + if (ACPI_FAILURE(status)) > + return -1; > + cpu = acpi_handle_to_cpuid(cpu_handle); > + if (cpu >= nr_cpu_ids) > + return -1; > + return cpu; > +} > + > static int amba_handler_attach(struct acpi_device *adev, > const struct acpi_device_id *id) > { > @@ -54,11 +84,17 @@ static int amba_handler_attach(struct acpi_device *adev, > bool address_found = false; > int irq_no = 0; > int ret; > + int cpu; > > /* If the ACPI node already has a physical device attached, skip it. */ > if (adev->physical_node_count) > return 0; > > + /* If the cpu associated with the device is not online, skip it. */ > + cpu = acpi_dev_get_cpu(adev); > + if (cpu >= 0 && !cpu_online(cpu)) > + return 0; > + Except for the comment above, the patch looks good to me. Suzuki

2 years, 9 months

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