Hi Mike,
thank you very much for your quick answer and your suggestions. From comparing the first trace bytes with the documentation of ETM packet types I had already assumed that this should be a trace-enable-i-sync-packet at the beginning, but I wasn’t sure.
I tried some debugging around your suggestions, but unfortunately I had no success. For your first suggestion:
I am not sure if I have understood you correctly, but from the code it looks like the ETF is enabled before the ETMs (I did not modify this in the tracedemo)
```c static int do_configure_trace(const struct board *board) { int i, r;
printf("CSDEMO: Configuring trace...\n"); /* Ensure TPIU isn't generating back-pressure */ cs_disable_tpiu(); /* While programming, ensure we are not collecting trace */ cs_sink_disable(devices.etb); if (devices.itm_etb != NULL) { cs_sink_disable(devices.itm_etb); } for (i = 0; i < board->n_cpu; ++i) { printf ("CSDEMO: Configuring trace source id for CPU #%d ETM/PTM...\n", i); devices.ptm[i] = cs_cpu_get_device(i, CS_DEVCLASS_SOURCE); if (devices.ptm[i] == CS_ERRDESC) { fprintf(stderr, "** Failed to get trace source for CPU #%d\n", i); return -1; } if (cs_set_trace_source_id(devices.ptm[i], 0x10 + i) < 0) { return -1; } if (do_init_etm(devices.ptm[i]) < 0) { return -1; } } if (itm) { cs_set_trace_source_id(devices.itm, 0x20); } cs_checkpoint();
for (i = 0; i < board->n_cpu; ++i) { if (CS_ETMVERSION_MAJOR(cs_etm_get_version(devices.ptm[i])) >= CS_ETMVERSION_ETMv4) r = do_config_etmv4(i); else r = do_config_etmv3_ptm(i); if (r != 0) return r; }
printf("CSDEMO: Enabling trace...\n"); if (cs_sink_enable(devices.etb) != 0) { printf ("CSDEMO: Could not enable trace buffer - not running demo\n"); return -1; } if (devices.itm_etb != NULL) { if (cs_sink_enable(devices.itm_etb) != 0) { printf("CSDEMO: Could not enable ITM trace buffer\n"); } }
for (i = 0; i < board->n_cpu; ++i) { if (trace_timestamps) cs_trace_enable_timestamps(devices.ptm[i], 1); if (trace_cycle_accurate) cs_trace_enable_cycle_accurate(devices.ptm[i], 1); cs_trace_enable(devices.ptm[i]); } ```
I played around with positioning the enabling of the ETM earlier in the code, but this did not change anything.
About your second suggestion: This is the CSAL Output when reading the trace buffer:
```c CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/ ```
So the Readpointer has the value 0 and Writepointer is at 0x30 I set the readpointer manually to 0xFFFF to see what data is there before what is output, but this does not look interesting either.
```c read 08844988, read ptr now 00001ff0 read 15be9408, read ptr now 00001ff0 read 88c4bcc0, read ptr now 00001ff0 read 44a84a9a, read ptr now 00000000 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020 ```
So I assume the data extraction works correctly, as the a-sync packet is already missing at the extraction of the trace from memory. My Full CSAL Output with debugging enabled looks like this:
CSAL Log
```c root@stm32mp1:~/csal_new/bin/arm/rel# ./tracedemo -filter -trace-start 0x103a0 -trace-stop 0x103f8 -board-name ST M32 Trace filtering active. CoreSight demonstrator ** Currently affine CPUs: #0 #1 ** csaccess: Registering ROM table at 50080000 ** csaccess: Scanning ROM table at 50080000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50082000 50082000: type=13 O TIMESTAMP ** csaccess: Registering device or ROM table at 50083000 50083000: 1.1 914 00000EA0 00/0F type= 9 - SINK PORT [SWO] ** csaccess: Registering device or ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ff7000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500A0000 500A0000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 64-bit, 128 masters] ** csaccess: Registering device or ROM table at 500D0000 500D0000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D1000 500D1000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D2000 500D2000: 5.1 C07 01110F13 00/FF type=11 - CPU 0.0 DEBUG v7.1 (4 wpt) (6 bkpt) sample:PC,CXID,VMID; Secure, running auth=FF ** csaccess: Registering device or ROM table at 500D3000 500D3000: 6.1 9A7 00000000 00/00 type=12 - CPU 0.0 PMU (4 counters) auth=CC ** csaccess: Registering device or ROM table at 500D8000 500D8000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500D9000 500D9000: 4.1 906 00040800 00/0F type=10 - CTI ** csaccess: Registering device or ROM table at 500DC000 500DC000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering device or ROM table at 500DD000 500DD000: 3.1 956 00000000 00/FF type= 1 - CPU 0.0 SOURCE ETMv3.5 ** csaccess: Registering ROM table at 50090000 ** csaccess: Scanning ROM table at 50090000 (mapped to 0xb6ffa000) ** csaccess: Registering device or ROM table at 50091000 50091000: 2.1 908 00000035 00/0F type= 4 - LINK [FUNNEL: 5 in ports] ** csaccess: Registering device or ROM table at 50092000 50092000: 2.3 961 00000480 00/0F type= 6 - LINK SINK BUFFER(8K) [TMC: ETF configuration] ** csaccess: Registering device or ROM table at 50093000 50093000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] ** csaccess: Registering device or ROM table at 50094000 50094000: 4.1 906 00040800 00/0F type=10 - CTI CSREG: Registration complete. CSDEMO: Configuring trace... ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50093000: write 304 (off) = 00001000 ** csaccess: 50093000: bit 300.00000002 set after 0 iterations ** csaccess: 50092000: write 018 (CS_ETB_RAM_WR_PTR) = 00000000 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: 50092000: write 304 (off) = 00001003 ** csaccess: 50092000: write 020 (CS_ETB_CTRL) = 00000001 CSDEMO: Configuring trace source id for CPU #0 ETM/PTM... ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 200 (CS_ETMTRACEIDR) = 00000010 CSDEMO: Initialising ETM/PTM ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DC000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DC000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DC000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DC000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DC000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DC000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 CSDEMO: Configuring trace source id for CPU #1 ETM/PTM... ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 200 (CS_ETMTRACEIDR) = 00000011 CSDEMO: Initialising ETM/PTM ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000406F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 0000406F ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 008 (CS_ETMTRIGGER) = 0000406F ** csaccess: 500DD000: write 1F8 (CS_ETMTSEVR) = 0000406F ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 048 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 088 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 04C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 08C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 050 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 090 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 054 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 094 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 058 (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 098 (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 05C (CS_ETMACVR(i)) = 00000000 ** csaccess: 500DD000: write 09C (CS_ETMACTR(i)) = 00000001 ** csaccess: 500DD000: write 0C0 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 100 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 0C8 (CS_ETMDCVR(i)) = 00000000 ** csaccess: 500DD000: write 108 (CS_ETMDCMR(i)) = 00000000 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00000000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 0002406F ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 0000406F ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00000000 ** csaccess: 500DD000: write 1BC (CS_ETMCIDCMR) = 00000000 ** csaccess: 500DD000: write 1B0 (CS_ETMCIDCVR(i)) = 00000000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 1A0 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 1A4 (CS_ETMEXTOUTEVR(i)) = 0000406F ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 000 (CS_ETMCR) = 00000460 ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 01000000 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: 500DC000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DC000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DC000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DC000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DC000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DC000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DC000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DC000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DC000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DC000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DC000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DC000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DC000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DC000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DC000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DC000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DC000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DC000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DC000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DC000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DC000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DC000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000000 Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: 500DD000: write 020 (CS_ETMTEEVR) = 0000006F ** csaccess: 500DD000: write 018 (CS_ETMTSSCR) = 00000000 ** csaccess: 500DD000: write 024 (CS_ETMTECR1) = 00000001 ** csaccess: 500DD000: write 01C (CS_ETMTECR2) = 00000000 ** csaccess: 500DD000: write 030 (CS_ETMVDEVR) = 00000000 ** csaccess: 500DD000: write 034 (CS_ETMVDCR(0)) = 00000000 ** csaccess: 500DD000: write 038 (CS_ETMVDCR(1)) = 00000000 ** csaccess: 500DD000: write 03C (CS_ETMVDCR(2)) = 00000000 ** csaccess: 500DD000: write 040 (CS_ETMACVR(i)) = 000103A0 ** csaccess: 500DD000: write 080 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 044 (CS_ETMACVR(i)) = 000103F8 ** csaccess: 500DD000: write 084 (CS_ETMACTR(i)) = 00000019 ** csaccess: 500DD000: write 140 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 150 (CS_ETMCNTENR(i)) = 0002006F ** csaccess: 500DD000: write 160 (CS_ETMCNTRLDEVR(i)) = 00000040 ** csaccess: 500DD000: write 170 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 144 (CS_ETMCNTRLDVR(i)) = 00002000 ** csaccess: 500DD000: write 154 (CS_ETMCNTENR(i)) = 00020051 ** csaccess: 500DD000: write 164 (CS_ETMCNTRLDEVR(i)) = 00000041 ** csaccess: 500DD000: write 174 (CS_ETMCNTVR(i)) = 00001000 ** csaccess: 500DD000: write 19C (CS_ETMSQR) = 00000000 ** csaccess: 500DD000: write 180 (CS_ETMSQEVRRAW(i)) = 00000000 ** csaccess: 500DD000: write 184 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 188 (CS_ETMSQEVRRAW(i)) = 00000001 ** csaccess: 500DD000: write 18C (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 190 (CS_ETMSQEVRRAW(i)) = 0000406F ** csaccess: 500DD000: write 194 (CS_ETMSQEVRRAW(i)) = 0000406F CSDEMO: Reading back configuration after programming... ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00001000 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSDEMO: Enabling trace... ** csaccess: enable path from 500DC000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000301 ** csaccess: funnel inputs now 00000301 ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DC000: write 000 (off) = 00000860 ** csaccess: enable path from 500DD000 ** csaccess: enable path from 50091000 ** csaccess: enable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000303 ** csaccess: funnel inputs now 00000303 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: bit 010.00000002 clear after 0 iterations ** csaccess: 500DD000: write 000 (off) = 00000860 CSDEMO: CTI settings.... CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CTI at 500D9000 (cpu #1) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 500D8000 (cpu #0) (disabled): TIN=10 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): #4: (active) outgoing triggers (8): CTI at 50094000 (disabled): TIN=00 TOUT=00 CIN=00 COUT=00 CACTIVE=00 CGATE=0F channels (4): none in use incoming triggers (8): outgoing triggers (8): CSDEMO: Configured and enabled trace. CSDEMO: Trace configured dumping config with No ITM CSUTIL: Created trace configuration export files CSDEMO: trace buffer contents: 0 bytes [press RETURN to stop tracing or q/Q to quit] CSDEMO: Disable trace... ** csaccess: 500DC000: write 000 (off) = 00000060 ** csaccess: 500DC000: write 000 (off) = 00000460 ** csaccess: 500DC000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DC000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 0 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000302 ** csaccess: funnel inputs now 00000302 ** csaccess: 500DD000: write 000 (off) = 00000060 ** csaccess: 500DD000: write 000 (off) = 00000460 ** csaccess: 500DD000: bit 010.00000002 set after 0 iterations ** csaccess: disable path from 500DD000 ** csaccess: disable path from 50091000 ** csaccess: disable input port 1 of funnel 50091000 ** csaccess: 50091000: write 000 (off) = 00000300 ** csaccess: funnel inputs now 00000300 ** csaccess: 50092000: bit 00C.00000004 set after 0 iterations CSDEMO: trace buffer contents: 48 bytes ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=00000364 enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00000DEC enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 3 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false ETM static configuration: ETMCCR = 8D294024 ETMCCER = 344008F2 ETMSCR = 00020C0C ETMIDR = 410CF250 ETM dynamic configuration: ETMCR = 00000460 Cycle accurate: 0 Branch output: 0 Timestamp enabled: 0 CONTEXTID size: 0 bytes Trace enable event: true Trace enable control: CR1=00000001 CR2=00000000 Trace start comparators: 0000 Trace stop comparators: 0000 ViewData event: single-addr-comp-0 ViewData control 1: 00000000 ViewData control 2: 00000000 ViewData control 3: 00000000 Trigger event: false Timestamp event: false Counters: 2 #0: value=000016BD enable=true reload_value=00002000 reload_event=counter-zero-0 #1: value=00001000 enable=sequencer-state-2 reload_value=00002000 reload_event=counter-zero-1 Address comparators: 8 #0: address=000103A0 type=00000019 (execute) (size=4) (S:all) (NS:all) #1: address=000103F8 type=00000019 (execute) (size=4) (S:all) (NS:all) #2: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #3: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #4: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #5: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #6: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) #7: address=00000000 type=00000001 (execute) (size=1) (S:all) (NS:all) Data comparators: 2 Sequencer present: 1 Sequencer: Current state: 1 1 -> 2: single-addr-comp-0 1 -> 3: false 2 -> 1: false 2 -> 3: single-addr-comp-1 3 -> 1: false 3 -> 2: false CONTEXTID comparators: 1 Mask: 00000000 #0: contextid: 00000000 External outputs: #0: false #1: false CSUTIL: Fetching trace from core ETB: Buffer RAM size: 8192 Bytes to read in buffer: 48 Buffer has wrapped: 0 ** csaccess: 50092000: write 014 (CS_ETB_RAM_RD_PTR) = 00000000 ** csaccess: ctrl=00000001 status=0000000C flstatus=00000002 readptr=00000000 writeptr=00000030 unread=0030 read a1280821, read ptr now 00000000 read bc000102, read ptr now 00000000 read bcb8bcbc, read ptr now 00000000 read 06bcb8bc, read ptr now 00000010 read bcbcd4bc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read bcbcbcbc, read ptr now 00000010 read 000194ec, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000020 read 00000000, read ptr now 00000030 ** csaccess: 50092000: write 020 (off) = 00000000 ** 48 bytes of trace The first 48 bytes of trace are: 21 08 28 A1 02 01 00 BC BC BC B8 BC BC B8 BC 06 BC D4 BC BC BC BC BC BC BC BC BC BC EC 94 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CSDEMO: shutdown... ** csaccess: unclaiming device at 500DD000** csaccess: unclaiming device at 500DC000root@stm32mp1:~/csal_new/bin/arm/rel# ```
Thanks for your input so far, I would be happy about any other suggestions, as I am really out of ideas.
Best regards, Finn