- Get reserved region from device tree node for metadata - Define metadata format for TMC - Add TMC ETR panic sync handler that syncs register snapshot to metadata region - Add TMC ETF panic sync handler that syncs register snapshot to metadata region and internal SRAM to reserved trace buffer region.
Signed-off-by: Anil Kumar Reddy areddy3@marvell.com Signed-off-by: Tanmay Jagdale tanmay@marvell.com Signed-off-by: Linu Cherian lcherian@marvell.com --- .../hwtracing/coresight/coresight-tmc-core.c | 29 +++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etf.c | 19 ++++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 12 ++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 16 ++++++++++ 4 files changed, 76 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 22d33a2233b8..0c1319851182 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -370,6 +370,7 @@ static int tmc_get_reserved_region(struct device *parent, void *dev_caps) struct resource res; int rc;
+ /* Trace buffer region */ node = of_parse_phandle(parent->of_node, "memory-region", 0); if (!node) { dev_dbg(parent, "No memory-region specified\n"); @@ -397,6 +398,34 @@ static int tmc_get_reserved_region(struct device *parent, void *dev_caps) drvdata->tmc_resrv_buf.size = resource_size(&res); /* Size of contiguous buffer space for TMC ETR */ drvdata->size = drvdata->tmc_resrv_buf.size; + } + + /* Metadata region */ + node = of_parse_phandle(parent->of_node, "memory-region", 1); + if (!node) { + dev_dbg(parent, "No memory-region specified\n"); + goto out; + } + + rc = of_address_to_resource(node, 0, &res); + of_node_put(node); + if (rc) { + dev_err(parent, "No address assigned to the memory-region\n"); + goto out; + } + + if (res.start != 0 && resource_size(&res) != 0) { + drvdata->tmc_metadata.vaddr = memremap(res.start, + resource_size(&res), MEMREMAP_WC); + if (IS_ERR(drvdata->tmc_metadata.vaddr)) { + dev_err(parent, "Failed to map destination address for reserved memory\n"); + rc = PTR_ERR(drvdata->tmc_metadata.vaddr); + goto out; + } + + drvdata->tmc_metadata.paddr = res.start; + drvdata->tmc_metadata.size = resource_size(&res); + return 0; }
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 0ab1f73c2d06..6c84b9ca3318 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -586,6 +586,20 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, return to_read; }
+static int tmc_sync_etf_sink(struct coresight_device *csdev) +{ + /* + * TODO: + * 1. Sync registers from hardware to metadata region + */ + + /* + * TODO: + * 2. Sync Internal SRAM to reserved trace buffer region + */ + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops = { .enable = tmc_enable_etf_sink, .disable = tmc_disable_etf_sink, @@ -599,6 +613,10 @@ static const struct coresight_ops_link tmc_etf_link_ops = { .disable = tmc_disable_etf_link, };
+static const struct coresight_ops_panic tmc_etf_sync_ops = { + .sync = tmc_sync_etf_sink, +}; + const struct coresight_ops tmc_etb_cs_ops = { .sink_ops = &tmc_etf_sink_ops, }; @@ -606,6 +624,7 @@ const struct coresight_ops tmc_etb_cs_ops = { const struct coresight_ops tmc_etf_cs_ops = { .sink_ops = &tmc_etf_sink_ops, .link_ops = &tmc_etf_link_ops, + .panic_ops = &tmc_etf_sync_ops, };
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 82d0e3840b50..dc6146012c8c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1780,10 +1780,22 @@ static const struct coresight_ops_sink tmc_etr_sink_ops = { .free_buffer = tmc_free_etr_buffer, };
+static int tmc_sync_etr_sink(struct coresight_device *csdev) +{ + /* TODO: Sync registers from hardware to metadata region */ + return 0; +} + +static const struct coresight_ops_panic tmc_etr_sync_ops = { + .sync = tmc_sync_etr_sink, +}; + const struct coresight_ops tmc_etr_cs_ops = { .sink_ops = &tmc_etr_sink_ops, + .panic_ops = &tmc_etr_sync_ops, };
+ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret = 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index c96b53b5cf89..b5208af10c56 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -133,6 +133,20 @@ enum tmc_mem_intf_width { #define CORESIGHT_SOC_600_ETR_CAPS \ (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
+/* TMC metadata region for ETR and ETF configurations */ +struct tmc_register_snapshot { + uint32_t valid; /* Indicate if this ETF/ETR was enabled */ + uint32_t size; /* Size of trace data */ + uint32_t rrphi; /* Read Pointer High Address bits */ + uint32_t rrp; /* Read Pointer */ + uint32_t rwphi; /* Write Pointer High Address bits */ + uint32_t rwp; /* Write Pointer */ + uint32_t sts; /* Status Register */ + uint32_t trc_addrhi; /* High Address bits of trace data in preserved region */ + uint32_t trc_addr; /* Address bits of trace data in preserved region */ + uint32_t reserved[7]; +}; + enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ @@ -202,6 +216,7 @@ struct resrv_buf { * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. * @tmc_resrv_buf: Reserved Memory for trace data buffer. Used by ETR/ETF. + * @tmc_metadata: Reserved memory for metadata. Used by ETR/ETF. */ struct tmc_drvdata { void __iomem *base; @@ -227,6 +242,7 @@ struct tmc_drvdata { struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; struct resrv_buf tmc_resrv_buf; + struct resrv_buf tmc_metadata; };
struct etr_buf_operations {