On Mon, Sep 02, 2019 at 02:22:47PM +0100, Mike Leach wrote:
Hi Leo,
On Mon, 2 Sep 2019 at 08:44, Leo Yan leo.yan@linaro.org wrote:
On Mon, Aug 19, 2019 at 10:13:48PM +0100, Mike Leach wrote:
Adds sysfs access to the coresight management registers.
Signed-off-by: Mike Leach mike.leach@linaro.org
.../hwtracing/coresight/coresight-cti-sysfs.c | 67 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a832b8c6b866..20a9b30c9755 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,7 @@ static ssize_t enable_show(struct device *dev, return size; }
-static ssize_t enable_store(struct device *dev,
struct device_attribute *attr,+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,
Redundant change?
The rest code in this patch looks good to me.
Fixup for function parameter alignment mentioned in v3 comments
In this set the alignment for function enable_store() in patch 1/15 is correct and doesn't need modification.
Thanks
Mike
Thanks, Leo Yan
const char *buf, size_t size){ int ret = 0; @@ -56,9 +55,67 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable);
+static ssize_t ctmid_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.ctm_id);+} +static DEVICE_ATTR_RO(ctmid);
/* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr,
&dev_attr_ctmid.attr,NULL,+};
+/* register based attributes */
+/* macro to access RO registers with power check only (no enable check). */ +#define coresight_cti_reg(name, offset) \ +static ssize_t name##_show(struct device *dev, \
struct device_attribute *attr, char *buf) \+{ \
struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \u32 val = 0; \pm_runtime_get_sync(dev->parent); \spin_lock(&drvdata->spinlock); \if (drvdata->config.hw_powered) \val = readl_relaxed(drvdata->base + offset); \spin_unlock(&drvdata->spinlock); \pm_runtime_put_sync(dev->parent); \return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \+} \ +static DEVICE_ATTR_RO(name)
+/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);
+static struct attribute *coresight_cti_mgmt_attrs[] = {
&dev_attr_devaff0.attr,&dev_attr_devaff1.attr,&dev_attr_authstatus.attr,&dev_attr_devarch.attr,&dev_attr_devid.attr,&dev_attr_devtype.attr,&dev_attr_pidr0.attr,&dev_attr_pidr1.attr,&dev_attr_pidr2.attr,&dev_attr_pidr3.attr,&dev_attr_pidr4.attr, NULL,};
@@ -66,7 +123,13 @@ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, };
+static const struct attribute_group coresight_cti_mgmt_group = {
.attrs = coresight_cti_mgmt_attrs,.name = "mgmt",+};
const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group,
&coresight_cti_mgmt_group, NULL,}; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 82e563cdc879..aba6b789c969 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -22,6 +22,7 @@ #define CORESIGHT_CLAIMCLR 0xfa4 #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_AUTHSTATUS 0xfb8 #define CORESIGHT_DEVID 0xfc8
#define CORESIGHT_DEVTYPE 0xfcc
2.17.1
CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK