Hey Mike,

On Mon, Aug 19, 2019 at 10:13:47PM +0100, Mike Leach wrote:

This introduces a baseline CTI driver and associated configuration files.

Uses the platform agnostic naming standard for CoreSight devices, along with a generic platform probing method that currently supports device tree descriptions, but allows for the ACPI bindings to be added once these have been defined for the CTI devices.

Driver will probe for the device on the AMBA bus, and load the CTI driver on CoreSight ID match to CTI IDs in tables.

Initial sysfs support for enable / disable provided.

Default CTI interconnection data is generated based on hardware register signal counts, with no additional connection information.

This is really coming along well - please see minor comments below.

Signed-off-by: Mike Leach mike.leach@linaro.org

drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 4 + .../coresight/coresight-cti-platform.c | 75 +++ .../hwtracing/coresight/coresight-cti-sysfs.c | 72 +++ drivers/hwtracing/coresight/coresight-cti.c | 451 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.h | 192 ++++++++ drivers/hwtracing/coresight/coresight.c | 4 + include/linux/coresight.h | 23 + 8 files changed, 833 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-cti-platform.c create mode 100644 drivers/hwtracing/coresight/coresight-cti-sysfs.c create mode 100644 drivers/hwtracing/coresight/coresight-cti.c create mode 100644 drivers/hwtracing/coresight/coresight-cti.h

diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 14638db4991d..98c525848662 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -109,4 +109,16 @@ config CORESIGHT_CPU_DEBUG properly, please refer Documentation/trace/coresight-cpu-debug.txt for detailed description and the example for usage. +config CORESIGHT_CTI

• bool "CoreSight Cross Trigger Interface (CTI) driver"
• depends on ARM || ARM64
• help

•  This driver provides support for CoreSight CTI and CTM components.
  

•  These provide hardware triggering events between CoreSight trace
  

•  source and sink components. These can be used to halt trace or
  

•  inject events into the trace stream. CTI also provides a software
  

•  control to trigger the same halt events. This can provide fast trace
  

•  halt compared to disabling sources and sinks normally in driver
  

•  software.
  

endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 3c0ac421e211..43d563705e98 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -17,3 +17,7 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o +obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o \

• 		coresight-cti-platform.o \
  

• 		coresight-cti-sysfs.o
  

diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c new file mode 100644 index 000000000000..eb4f8a835c10 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019, The Linux Foundation. All rights reserved.

Leo already commented on the Linux Foundation part.

• */

+#include <linux/of.h>

+#include "coresight-cti.h"

+#ifdef CONFIG_OF +/* get the hardware configuration & connection data. */ +int of_cti_get_hw_data(struct device *dev,

•        struct device_node *np,
  

•        struct cti_drvdata *drvdata)
  

+{

• int rc = 0;
• struct cti_device *cti_dev = &drvdata->ctidev;
• /* if no connections, just add a single default based on max IN-OUT */
• if (cti_dev->nr_trig_con == 0)

• rc = cti_add_default_connection(dev, drvdata);
  

• return rc;

+}

+/*

• • Platform data for the CTI does not have the same connection info
• • as the trace path components. Implement specific function to
• • avoid warnings of missing connections.
• */

+int of_get_coresight_cti_platform_data(struct device *dev,

• 		       struct coresight_platform_data *pdata)
  

+{

• int ret = 0;
• struct device_node *node = dev->of_node;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev);
• /* get some CTI specifics */
• ret = of_cti_get_hw_data(dev, node, drvdata);
• return ret;

+} +#else +inline int +of_get_coresight_cti_platform_data(struct device *dev,

• 		   struct coresight_platform_data *pdata)
  

+{

• return -ENOENT;

+}

+#endif

+struct coresight_platform_data * +coresight_cti_get_platform_data(struct device *dev) +{

• int ret = -ENOENT;
• struct coresight_platform_data *pdata = NULL;
• struct fwnode_handle *fwnode = dev_fwnode(dev);
• if (IS_ERR_OR_NULL(fwnode))

• goto error;
  

• pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
• if (!pdata) {

• ret = -ENOMEM;
  

• goto error;
  

• }
• if (is_of_node(fwnode))

• ret = of_get_coresight_cti_platform_data(dev, pdata);
  

• if (!ret)

• return pdata;
  

+error:

• return ERR_PTR(ret);

+} diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c new file mode 100644 index 000000000000..a832b8c6b866 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019 Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#include <linux/coresight.h>

+#include "coresight-cti.h"

+/* basic attributes */ +static ssize_t enable_show(struct device *dev,

• 	   struct device_attribute *attr,
  

• 	   char *buf)
  

+{

• int enable_req;
• bool enabled, powered;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ssize_t size = 0;
• enable_req = atomic_read(&drvdata->config.enable_req_count);
• spin_lock(&drvdata->spinlock);
• powered = drvdata->config.hw_powered;
• enabled = drvdata->config.hw_enabled;
• spin_unlock(&drvdata->spinlock);
• if (powered) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; powered;\n",
  

• 		 enabled ? "enabled" : "disabled");
  

• } else {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; unpowered;\n",
  

• 		 enable_req ? "enable req" : "disabled");
  

• }
• return size;

+}

+static ssize_t enable_store(struct device *dev,

• 	    struct device_attribute *attr,
  

• 	    const char *buf, size_t size)
  

+{

• int ret = 0;
• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ret = kstrtoul(buf, 0, &val);
• if (ret)

• return ret;
  

• if (val)

• ret = cti_enable(drvdata->csdev);
  

• else

• ret = cti_disable(drvdata->csdev);
  

• if (ret)

• return ret;
  

• return size;

+} +static DEVICE_ATTR_RW(enable);

+/* attribute and group sysfs tables. */ +static struct attribute *coresight_cti_attrs[] = {

• &dev_attr_enable.attr,
• NULL,

+};

+static const struct attribute_group coresight_cti_group = {

• .attrs = coresight_cti_attrs,

+};

+const struct attribute_group *coresight_cti_groups[] = {

• &coresight_cti_group,
• NULL,

+}; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c new file mode 100644 index 000000000000..b56d9a02c4b4 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019 Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org

This is 2019 but in coresight-cti.c it is 2018.

• */

+#include "coresight-cti.h"

+/**

• • CTI devices can be associated with a PE, or be connected to CoreSight
• • hardware. We have a list of all CTIs irrespective of CPU bound or
• • otherwise.
• • We assume that the non-CPU CTIs are always powered as we do with sinks etc.
• • We leave the client to figure out if all the CTIs are interconnected with
• • the same CTM, in general this is the case but does not always have to be.
• */

+/* net of CTI devices connected via CTM */ +LIST_HEAD(ect_net);

+/* protect the list */ +static DEFINE_MUTEX(ect_mutex);

+#define csdev_to_cti_drvdata(csdev) \

• dev_get_drvdata(csdev->dev.parent)

+/*

• • CTI naming. CTI bound to cores will have the name cti_cpu<N> where
• • N is the CPU ID. System CTIs will have the name cti_sys<I> where I
• • is an index allocated by order of discovery.
• • CTI device name list - for CTI not bound to cores.
• */

+DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys");

+/* write set of regs to hardware - call with spinlock claimed */ +static void cti_write_all_hw_regs(struct cti_drvdata *drvdata) +{

• struct cti_config *config = &drvdata->config;
• int i;
• CS_UNLOCK(drvdata->base);
• /* disable CTI before writing registers */
• writel_relaxed(0, drvdata->base + CTICONTROL);
• /* write the CTI trigger registers */
• for (i = 0; i < config->nr_trig_max; i++) {

• writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
  

• writel_relaxed(config->ctiouten[i],
  

• 	       drvdata->base + CTIOUTEN(i));
  

• }
• /* other regs */
• writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
• writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
• writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
• /* re-enable CTI */
• writel_relaxed(1, drvdata->base + CTICONTROL);
• CS_LOCK(drvdata->base);

+}

+static void cti_enable_hw_smp_call(void *info) +{

• struct cti_drvdata *drvdata = info;
• cti_write_all_hw_regs(drvdata);

+}

+/* write regs to hardware and enable */ +static int cti_enable_hw(struct cti_drvdata *drvdata, bool update_refcount) +{

Just like Leo and Suzuki, I am perplexed about the @update_refcount part. Even after applying all the patches function cti_enable/disable_hw() are always called the same way.

• struct cti_config *config = &drvdata->config;
• struct device *dev = &drvdata->csdev->dev;
• int rc = 0;
• pm_runtime_get_sync(dev->parent);
• spin_lock(&drvdata->spinlock);
• /* no need to do anything if enabled or unpowered*/
• if (config->hw_enabled || !config->hw_powered)

• goto cti_state_unchanged;
  

• /* claim the device */
• rc = coresight_claim_device(drvdata->base);
• if (rc)

• goto cti_err_not_enabled;
  

• if (drvdata->ctidev.cpu >= 0) {

• rc = smp_call_function_single(drvdata->ctidev.cpu,
  

• 			 cti_enable_hw_smp_call,
  

• 			 drvdata, 1);
  

Alignment problem - the second and third line have to be aligned with drvdata.

• if (rc)
  

• 	goto cti_err_not_enabled;
  

• } else

• cti_write_all_hw_regs(drvdata);
  

Add curly braces, normally checkpatch will catch those.

• config->hw_enabled = true;
• if (update_refcount)

• atomic_inc(&drvdata->config.enable_req_count);
  

• spin_unlock(&drvdata->spinlock);
• return rc;

+cti_state_unchanged:

• if (update_refcount)

• atomic_inc(&drvdata->config.enable_req_count);
  

• /* cannot enable due to error */

+cti_err_not_enabled:

• spin_unlock(&drvdata->spinlock);
• pm_runtime_put(dev->parent);
• return rc;

+}

+/* disable hardware */ +static int cti_disable_hw(struct cti_drvdata *drvdata, bool update_refcount) +{

• struct cti_config *config = &drvdata->config;
• struct device *dev = &drvdata->csdev->dev;
• spin_lock(&drvdata->spinlock);
• /* check refcount - disable on 0 */
• if (update_refcount &&

•    (atomic_dec_return(&drvdata->config.enable_req_count) > 0))
  

• goto cti_not_disabled;
  

• /* no need to do anything if disabled or cpu unpowered */
• if (!config->hw_enabled || !config->hw_powered)

• goto cti_not_disabled;
  

• CS_UNLOCK(drvdata->base);
• /* disable CTI */
• writel_relaxed(0, drvdata->base + CTICONTROL);
• config->hw_enabled = false;
• coresight_disclaim_device_unlocked(drvdata->base);
• CS_LOCK(drvdata->base);
• spin_unlock(&drvdata->spinlock);
• pm_runtime_put(dev);
• return 0;
• /* not disabled this call */

+cti_not_disabled:

• spin_unlock(&drvdata->spinlock);
• return 0;

+}

+/*

• • Look at the HW DEVID register for some of the HW settings.
• • DEVID[15:8] - max number of in / out triggers.
• */

+#define CTI_DEVID_MAXTRIGS(devid_val) (int)((devid_val & 0xFF00) >> 8)

+/* DEVID[19:16] - number of CTM channels */ +#define CTI_DEVID_CTMCHANNELS(devid_val) (int)((devid_val & 0xF0000) >> 16)

+static void cti_set_default_config(struct device *dev,

• 		   struct cti_drvdata *drvdata)
  

+{

• struct cti_config *config = &drvdata->config;
• u32 devid;
• devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
• config->nr_trig_max = CTI_DEVID_MAXTRIGS(devid);
• /*

• * no current hardware should exceed this, but protect the driver
  

• * in case of fault / out of spec hw
  

• */
  

• if (config->nr_trig_max > CTIINOUTEN_MAX) {

• dev_warn_once(dev,
  

• 	"Limiting HW MaxTrig value(%d) to driver max(%d)\n",
  

• 	config->nr_trig_max, CTIINOUTEN_MAX);
  

• config->nr_trig_max = CTIINOUTEN_MAX;
  

• }
• config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid);
• /* Most regs default to 0 as zalloc'ed except...*/
• config->trig_filter_enable = true;
• config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0);
• atomic_set(&config->enable_req_count, 0);

+}

+/*

• • Add a connection entry to the list of connections for this
• • CTI device.
• */

+int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,

• 	     struct cti_trig_con *tc,
  

• 	     struct coresight_device *csdev,
  

• 	     const char *assoc_dev_name)
  

+{

• struct cti_device *cti_dev = &drvdata->ctidev;
• tc->con_dev = csdev;
• /*

• * Prefer actual associated CS device dev name to supplied value -
  

• * which is likely to be node name / other conn name.
  

• */
  

• if (csdev)

• tc->con_dev_name = devm_kstrdup(dev,
  

• 				dev_name(&csdev->dev),
  

• 				GFP_KERNEL);
  

• else if (assoc_dev_name != NULL)

• tc->con_dev_name = devm_kstrdup(dev,
  

• 				assoc_dev_name, GFP_KERNEL);
  

• list_add_tail(&tc->node, &cti_dev->trig_cons);
• cti_dev->nr_trig_con++;
• /* add connection usage bit info to overall info */
• drvdata->config.trig_in_use |= tc->con_in->used_mask;
• drvdata->config.trig_out_use |= tc->con_out->used_mask;
• return 0;

+}

+/* create a trigger connection with appropriately sized signal groups */ +struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,

• 			   int out_sigs)
  

+{

• struct cti_trig_con *tc = NULL;
• struct cti_trig_grp *in = NULL, *out = NULL;
• tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL);
• if (!tc)

• return tc;
  

• in = devm_kzalloc(dev,

• 	  offsetof(struct cti_trig_grp, sig_types[in_sigs]),
  

• 	  GFP_KERNEL);
  

• if (!in)

• return NULL;
  

• out = devm_kzalloc(dev,

• 	   offsetof(struct cti_trig_grp, sig_types[out_sigs]),
  

• 	   GFP_KERNEL);
  

• if (!out)

• return NULL;
  

• tc->con_in = in;
• tc->con_out = out;
• tc->con_in->nr_sigs = in_sigs;
• tc->con_out->nr_sigs = out_sigs;
• return tc;

+}

+/*

• • Add a default connection if nothing else is specified.
• • single connection based on max in/out info, no assoc device
• */

+int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) +{

• int ret = 0;
• int n_trigs = drvdata->config.nr_trig_max;
• u32 n_trig_mask = GENMASK(n_trigs - 1, 0);
• struct cti_trig_con *tc = NULL;
• /*

• * Assume max trigs for in and out,
  

• * all used, default sig types allocated
  

• */
  

• tc = cti_allocate_trig_con(dev, n_trigs, n_trigs);
• if (!tc)

• return -ENOMEM;
  

• tc->con_in->used_mask = n_trig_mask;
• tc->con_out->used_mask = n_trig_mask;
• ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default");
• return ret;

+}

+/** cti ect operations **/ +int cti_enable(struct coresight_device *csdev) +{

• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• /* enable hardware with refcount */
• return cti_enable_hw(drvdata, true);

+}

+int cti_disable(struct coresight_device *csdev) +{

• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• /* disable hardware with refcount */
• return cti_disable_hw(drvdata, true);

+}

+const struct coresight_ops_ect cti_ops_ect = {

• .enable = cti_enable,
• .disable = cti_disable,

+};

+const struct coresight_ops cti_ops = {

• .ect_ops = &cti_ops_ect,

+};

+/*

• • Free up CTI specific resources
• • called by dev->release, need to call down to underlying csdev release.
• */

+static void cti_device_release(struct device *dev) +{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_drvdata *ect_item, *ect_tmp;
• mutex_lock(&ect_mutex);
• /* remove from the list */
• list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) {

• if (ect_item == drvdata) {
  

• 	list_del(&ect_item->node);
  

• 	goto ect_list_item_removed;
  

• }
  

• }

+ect_list_item_removed:

• mutex_unlock(&ect_mutex);
• if (drvdata->csdev_release)

• drvdata->csdev_release(dev);
  

+}

+static int cti_probe(struct amba_device *adev, const struct amba_id *id) +{

• int ret = 0;
• void __iomem *base;
• struct device *dev = &adev->dev;
• struct cti_drvdata *drvdata = NULL;
• struct coresight_desc cti_desc;
• struct coresight_platform_data *pdata = NULL;
• struct resource *res = &adev->res;
• /* driver data*/
• drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
• if (!drvdata) {

• ret = -ENOMEM;
  

• dev_info(dev, "%s, mem err\n", __func__);
  

• goto err_out;
  

• }
• /* Validity for the resource is already checked by the AMBA core */
• base = devm_ioremap_resource(dev, res);
• if (IS_ERR(base)) {

• ret = PTR_ERR(base);
  

• dev_info(dev, "%s, remap err\n", __func__);
  

• goto err_out;
  

• }
• drvdata->base = base;
• dev_set_drvdata(dev, drvdata);
• /* default CTI device info */
• drvdata->ctidev.cpu = -1;
• drvdata->ctidev.nr_trig_con = 0;
• drvdata->ctidev.ctm_id = 0;
• INIT_LIST_HEAD(&drvdata->ctidev.trig_cons);
• spin_lock_init(&drvdata->spinlock);
• /* initialise CTI driver config values */
• cti_set_default_config(dev, drvdata);
• /* Parse the .dts for connections and signals */
• pdata = coresight_cti_get_platform_data(dev);
• if (IS_ERR(pdata)) {

• dev_info(dev, "coresight_cti_get_platform_data err\n");
  

• ret =  PTR_ERR(pdata);
  

• goto err_out;
  

• }
• /* default to powered - could change on PM notifications */
• drvdata->config.hw_powered = true;
• /* set up device name - will depend if cpu bound or otherwise */
• if (drvdata->ctidev.cpu >= 0)

• cti_desc.name = devm_kasprintf(dev, GFP_KERNEL, "cti_cpu%d",
  

• 			       drvdata->ctidev.cpu);
  

• else

• cti_desc.name = coresight_alloc_device_name(&cti_sys_devs, dev);
  

• if (!cti_desc.name) {

• ret = -ENOMEM;
  

• goto err_out;
  

• }
• /* set up coresight component description */
• cti_desc.pdata = pdata;
• cti_desc.type = CORESIGHT_DEV_TYPE_ECT;
• cti_desc.subtype.ect_subtype = CORESIGHT_DEV_SUBTYPE_ECT_CTI;
• cti_desc.ops = &cti_ops;
• cti_desc.groups = coresight_cti_groups;
• cti_desc.dev = dev;
• drvdata->csdev = coresight_register(&cti_desc);
• if (IS_ERR(drvdata->csdev)) {

• ret = PTR_ERR(drvdata->csdev);
  

• goto err_out;
  

• }
• /* add to list of CTI devices */
• mutex_lock(&ect_mutex);
• list_add(&drvdata->node, &ect_net);
• mutex_unlock(&ect_mutex);
• /* set up release chain */
• drvdata->csdev_release = drvdata->csdev->dev.release;
• drvdata->csdev->dev.release = cti_device_release;

I really like what you've done here.

• /* all done - dec pm refcount */
• pm_runtime_put(&adev->dev);
• dev_info(dev, "%s: CTI initialized\n", cti_desc.name);
• return 0;

+err_out:

• return ret;

+}

+static struct amba_cs_uci_id uci_id_cti[] = {

• {

• /*  CTI UCI data */
  

• .devarch	= 0x47701a14, /* CTI v2 */
  

• .devarch_mask	= 0xfff0ffff,
  

• .devtype	= 0x00000014, /* maj(0x4-debug) min(0x1-ECT) */
  

• }

+};

+static const struct amba_id cti_ids[] = {

• CS_AMBA_ID(0x000bb906), /* Coresight CTI (SoC 400), C-A72, C-A57 */
• CS_AMBA_ID(0x000bb922), /* CTI - C-A8 */
• CS_AMBA_ID(0x000bb9a8), /* CTI - C-A53 */
• CS_AMBA_ID(0x000bb9aa), /* CTI - C-A73 */
• CS_AMBA_UCI_ID(0x000bb9da, uci_id_cti), /* CTI - C-A35 */
• CS_AMBA_UCI_ID(0x000bb9ed, uci_id_cti), /* Coresight CTI (SoC 600) */
• { 0, 0},

+};

+static struct amba_driver cti_driver = {

• .drv = {

• .name	= "coresight-cti",
  

• .owner = THIS_MODULE,
  

• .suppress_bind_attrs = true,
  

• },
• .probe = cti_probe,
• .id_table = cti_ids,

+}; +builtin_amba_driver(cti_driver); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h new file mode 100644 index 000000000000..717035a9aa72 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (c) 2018 Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#ifndef _CORESIGHT_CORESIGHT_CTI_H +#define _CORESIGHT_CORESIGHT_CTI_H

+#include <asm/local.h> +#include <linux/spinlock.h> +#include "coresight-priv.h"

+/*

• • Device registers
• • 0x000 - 0x144: CTI programming and status
• • 0xEDC - 0xEF8: CTI integration test.
• • 0xF00 - 0xFFC: Coresight management registers.
• */

+/* CTI programming registers */ +#define CTICONTROL 0x000 +#define CTIINTACK 0x010 +#define CTIAPPSET 0x014 +#define CTIAPPCLEAR 0x018 +#define CTIAPPPULSE 0x01C +#define CTIINEN(n) (0x020 + (4 * n)) +#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTITRIGINSTATUS 0x130 +#define CTITRIGOUTSTATUS 0x134 +#define CTICHINSTATUS 0x138 +#define CTICHOUTSTATUS 0x13C +#define CTIGATE 0x140 +#define ASICCTL 0x144 +/* Integration test registers */ +#define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/ +#define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/ +#define ITCHOUT 0xEE4 /* WO RW-600 */ +#define ITTRIGOUT 0xEE8 /* WO RW-600 */ +#define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/ +#define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/ +#define ITCHIN 0xEF4 /* RO */ +#define ITTRIGIN 0xEF8 /* RO */ +/* management registers */ +#define CTIDEVAFF0 0xFA8 +#define CTIDEVAFF1 0xFAC

+/*

• • CTI CSSoc 600 has a max of 32 trigger signals per direction.
• • CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
• • Max of in and out defined in the DEVID register.
• • • pick up actual number used from .dts parameters if present.
• */

+#define CTIINOUTEN_MAX 32

+/**

• • Group of related trigger signals
• • @nr_sigs: number of signals in the group.
• • @used_mask: bitmask representing the signal indexes in the group.
• • @sig_types: array of types for the signals, length nr_sigs.
• */

+struct cti_trig_grp {

• int nr_sigs;
• u32 used_mask;
• int sig_types[0];

+};

+/**

• • Trigger connection - connection between a CTI and other (coresight) device
• • lists input and output trigger signals for the device
• • @con_in: connected CTIIN signals for the device.
• • @con_out: connected CTIOUT signals for the device.
• • @con_dev: coresight device connected to the CTI, NULL if not CS device
• • @con_dev_name: name of connected device (CS or CPU)
• • @node: entry node in list of connections.
• */

+struct cti_trig_con {

• struct cti_trig_grp *con_in;
• struct cti_trig_grp *con_out;
• struct coresight_device *con_dev;
• char *con_dev_name;
• struct list_head node;

+};

+/**

• • struct cti_device - description of CTI device properties.
• • @nt_trig_con: Number of external devices connected to this device.
• • @ctm_id: which CTM this device is connected to (by default it is

• •      assumed there is a single CTM per SoC, ID 0).
    

• • @trig_cons: list of connections to this device.
• • @cpu: CPU ID if associated with CPU, -1 otherwise.
• */

+struct cti_device {

• int nr_trig_con;
• u32 ctm_id;
• struct list_head trig_cons;
• int cpu;

+};

+/**

• • struct cti_config - configuration of the CTI device hardware
• • Hardware description from RO ID regs
• • @nr_trig_max: Max number of trigger signals implemented on device.

• • (max of trig_in or trig_out)
    

• • @nr_ctm_channels: number of available CTM channels
• • Cti enable control

Are the above 2 lines supposed to be part of @nr_ctm_channels? If so there is a spurious newline and the beginning of the second line needs to be aligned with the 'n' of number.

• • @enable_req_count: CTI is enabled alongside >=1 associated devices.
• • @hw_enabled: true if hw is currently enabled.
• • @hw_powered: true if associated cpu powered on, or no cpu.
• • Registered triggers and filtering

Same here

• • @trig_in_use: bitfield of in triggers registered as in use.
• • @trig_out_use: bitfield of out triggers registered as in use.
• • @trig_out_filter: bitfield of out triggers that are blocked if filter
• • enabled. Typically this would be dbgreq / restart on a core CTI.

Align the second line with "bitfield".

• • @trig_filter_enable: 1 if filtering enabled.
• • @xtrig_rchan_sel: channel selection for xtrigger connection show.
• • Cti software programmable regs:

Same as above

• • @ctiappset: CTI Software application channel set.
• • @ctiinout_sel: register selector for INEN and OUTEN regs.
• • @ctiinen: enable input trigger to a channel.
• • @ctiouten: enable output trigger from a channel.
• • @ctigate: gate channel output from CTI to CTM.
• • @asicctl: asic control register.
• */

+struct cti_config {

• /* hardware description */
• int nr_ctm_channels;
• int nr_trig_max;
• /* cti enable control */
• atomic_t enable_req_count;
• bool hw_enabled;
• bool hw_powered;
• /* registered triggers and filtering */
• u32 trig_in_use;
• u32 trig_out_use;
• u32 trig_out_filter;
• bool trig_filter_enable;
• u8 xtrig_rchan_sel;
• /* cti cross trig programmable regs */
• u32 ctiappset;
• u8 ctiinout_sel;
• u32 ctiinen[CTIINOUTEN_MAX];
• u32 ctiouten[CTIINOUTEN_MAX];
• u32 ctigate;
• u32 asicctl;

+};

+/**

• • struct cti_drvdata - specifics for the CTI device
• • @base: Memory mapped base address for this component..
• • @csdev: Standard CoreSight device information.
• • @ctidev: Extra information needed by the CTI/CTM framework.
• • @spinlock: Control data access to one at a time.
• • @config: Configuration data for this CTI device.
• • @node: List entry of this device in the list of CTI devices.
• • @csdev_release: release function for underlying coresight_device.
• */

+struct cti_drvdata {

• void __iomem *base;
• struct coresight_device *csdev;
• struct cti_device ctidev;
• spinlock_t spinlock;
• struct cti_config config;
• struct list_head node;
• void (*csdev_release)(struct device *dev);

+};

+/* private cti driver fns & vars */ +extern const struct attribute_group *coresight_cti_groups[]; +int cti_add_default_connection(struct device *dev,

• 	       struct cti_drvdata *drvdata);
  

+int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,

• 	     struct cti_trig_con *tc,
  

• 	     struct coresight_device *csdev,
  

• 	     const char *assoc_dev_name);
  

+struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,

• 			   int out_sigs);
  

+int cti_enable(struct coresight_device *csdev); +int cti_disable(struct coresight_device *csdev); +struct coresight_platform_data * +coresight_cti_get_platform_data(struct device *dev);

+#endif /* _CORESIGHT_CORESIGHT_CTI_H */ diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 6453c67a4d01..64ff810394f9 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -972,6 +972,9 @@ static struct device_type coresight_dev_type[] = { { .name = "helper", },

• {

• .name = "ect",
  

• },

}; static void coresight_device_release(struct device *dev) @@ -979,6 +982,7 @@ static void coresight_device_release(struct device *dev) struct coresight_device *csdev = to_coresight_device(dev); fwnode_handle_put(csdev->dev.fwnode);

Spurious newline

kfree(csdev->refcnt); kfree(csdev); } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index a2b68823717b..2a23c3cdf8e4 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -41,6 +41,7 @@ enum coresight_dev_type { CORESIGHT_DEV_TYPE_LINKSINK, CORESIGHT_DEV_TYPE_SOURCE, CORESIGHT_DEV_TYPE_HELPER,

• CORESIGHT_DEV_TYPE_ECT,

}; enum coresight_dev_subtype_sink { @@ -68,6 +69,12 @@ enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_CATU, }; +/* Embedded Cross Trigger (ECT) sub-types */ +enum coresight_dev_subtype_ect {

• CORESIGHT_DEV_SUBTYPE_ECT_NONE,
• CORESIGHT_DEV_SUBTYPE_ECT_CTI,

+};

/**

• union coresight_dev_subtype - further characterisation of a type
• @sink_subtype: type of sink this component is, as defined

@@ -78,6 +85,8 @@ enum coresight_dev_subtype_helper {

• 	by @coresight_dev_subtype_source.
  

• @helper_subtype: type of helper this component is, as defined

• 	by @coresight_dev_subtype_helper.
  

• • @ect_subtype: type of cross trigger this component is, as

• • 	defined by @coresight_dev_subtype_ect
    

  */

union coresight_dev_subtype { /* We have some devices which acts as LINK and SINK */ @@ -87,6 +96,7 @@ union coresight_dev_subtype { }; enum coresight_dev_subtype_source source_subtype; enum coresight_dev_subtype_helper helper_subtype;

• enum coresight_dev_subtype_ect ect_subtype;

}; /** @@ -196,6 +206,7 @@ static struct coresight_dev_list (var) = { \ #define sink_ops(csdev) csdev->ops->sink_ops #define link_ops(csdev) csdev->ops->link_ops #define helper_ops(csdev) csdev->ops->helper_ops +#define ect_ops(csdev) csdev->ops->ect_ops /**

• struct coresight_ops_sink - basic operations for a sink

@@ -262,11 +273,23 @@ struct coresight_ops_helper { int (*disable)(struct coresight_device *csdev, void *data); }; +/**

• • struct coresight_ops_ect - Ops for an embedded cross trigger device
• • @enable : Enable the device
• • @disable : Disable the device
• */

+struct coresight_ops_ect {

• int (*enable)(struct coresight_device *csdev);
• int (*disable)(struct coresight_device *csdev);

+};

struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops;

• const struct coresight_ops_ect *ect_ops;

};

#ifdef CONFIG_CORESIGHT

2.17.1

Hi Mike

On 08/19/2019 10:13 PM, Mike Leach wrote:

This introduces a baseline CTI driver and associated configuration files.

Uses the platform agnostic naming standard for CoreSight devices, along with a generic platform probing method that currently supports device tree descriptions, but allows for the ACPI bindings to be added once these have been defined for the CTI devices.

Driver will probe for the device on the AMBA bus, and load the CTI driver on CoreSight ID match to CTI IDs in tables.

Initial sysfs support for enable / disable provided.

Default CTI interconnection data is generated based on hardware register signal counts, with no additional connection information.

Signed-off-by: Mike Leach mike.leach@linaro.org

diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c new file mode 100644 index 000000000000..eb4f8a835c10 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019, The Linux Foundation. All rights reserved.
• */

+#include <linux/of.h>

+#include "coresight-cti.h"

+#ifdef CONFIG_OF +/* get the hardware configuration & connection data. */ +int of_cti_get_hw_data(struct device *dev,

•        struct device_node *np,
  

•        struct cti_drvdata *drvdata)
  

nit: The parameter np seems superfluous. You don't use it now. Even if you wanted to use it, you could grab it from the dev already.

+{

• int rc = 0;
• struct cti_device *cti_dev = &drvdata->ctidev;
• /* if no connections, just add a single default based on max IN-OUT */
• if (cti_dev->nr_trig_con == 0)

• rc = cti_add_default_connection(dev, drvdata);
  

• return rc;

+}

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c new file mode 100644 index 000000000000..a832b8c6b866 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c

+/* basic attributes */ +static ssize_t enable_show(struct device *dev,

• 	   struct device_attribute *attr,
  

• 	   char *buf)
  

+{

• int enable_req;
• bool enabled, powered;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ssize_t size = 0;
• enable_req = atomic_read(&drvdata->config.enable_req_count);
• spin_lock(&drvdata->spinlock);
• powered = drvdata->config.hw_powered;
• enabled = drvdata->config.hw_enabled;
• spin_unlock(&drvdata->spinlock);
• if (powered) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; powered;\n",
  

• 		 enabled ? "enabled" : "disabled");
  

• } else {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; unpowered;\n",
  

• 		 enable_req ? "enable req" : "disabled");
  

• }
• return size;

+}

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c new file mode 100644 index 000000000000..b56d9a02c4b4 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti.c

+#include "coresight-cti.h"

+/**

• • CTI devices can be associated with a PE, or be connected to CoreSight
• • hardware. We have a list of all CTIs irrespective of CPU bound or
• • otherwise.
• • We assume that the non-CPU CTIs are always powered as we do with sinks etc.
• • We leave the client to figure out if all the CTIs are interconnected with
• • the same CTM, in general this is the case but does not always have to be.
• */

+/* net of CTI devices connected via CTM */ +LIST_HEAD(ect_net);

+/* protect the list */ +static DEFINE_MUTEX(ect_mutex);

+#define csdev_to_cti_drvdata(csdev) \

• dev_get_drvdata(csdev->dev.parent)

+/* disable hardware */ +static int cti_disable_hw(struct cti_drvdata *drvdata, bool update_refcount) +{

• struct cti_config *config = &drvdata->config;
• struct device *dev = &drvdata->csdev->dev;
• spin_lock(&drvdata->spinlock);
• /* check refcount - disable on 0 */
• if (update_refcount &&

•    (atomic_dec_return(&drvdata->config.enable_req_count) > 0))
  

• goto cti_not_disabled;
  

If you really need to do something like this, you could refactor the function as follows :

/* Called with drvdata->spinlock held */

static int __cti_disable_hw(drvdata) {

• /* no need to do anything if disabled or cpu unpowered */
• if (!config->hw_enabled || !config->hw_powered)

• goto cti_not_disabled;
  

• CS_UNLOCK(drvdata->base);
• /* disable CTI */
• writel_relaxed(0, drvdata->base + CTICONTROL);
• config->hw_enabled = false;
• coresight_disclaim_device_unlocked(drvdata->base);
• CS_LOCK(drvdata->base);
• spin_unlock(&drvdata->spinlock);
• pm_runtime_put(dev);
• return 0;

}

And make the decision of calling this from cti_disable_hw() based on refcount. And where you may not want to check the refcount call the __cti_disable_hw() directly.

• /* not disabled this call */

+cti_not_disabled:

• spin_unlock(&drvdata->spinlock);
• return 0;

+}

+/*

• • Add a connection entry to the list of connections for this
• • CTI device.
• */

+int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,

• 	     struct cti_trig_con *tc,
  

• 	     struct coresight_device *csdev,
  

• 	     const char *assoc_dev_name)
  

+{

• struct cti_device *cti_dev = &drvdata->ctidev;
• tc->con_dev = csdev;
• /*

• * Prefer actual associated CS device dev name to supplied value -
  

• * which is likely to be node name / other conn name.
  

• */
  

• if (csdev)

• tc->con_dev_name = devm_kstrdup(dev,
  

• 				dev_name(&csdev->dev),
  

• 				GFP_KERNEL);
  

• else if (assoc_dev_name != NULL)

• tc->con_dev_name = devm_kstrdup(dev,
  

• 				assoc_dev_name, GFP_KERNEL);
  

• list_add_tail(&tc->node, &cti_dev->trig_cons);
• cti_dev->nr_trig_con++;
• /* add connection usage bit info to overall info */
• drvdata->config.trig_in_use |= tc->con_in->used_mask;
• drvdata->config.trig_out_use |= tc->con_out->used_mask;
• return 0;

+}

+/* create a trigger connection with appropriately sized signal groups */ +struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,

• 			   int out_sigs)
  

+{

• struct cti_trig_con *tc = NULL;
• struct cti_trig_grp *in = NULL, *out = NULL;
• tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL);
• if (!tc)

• return tc;
  

• in = devm_kzalloc(dev,

• 	  offsetof(struct cti_trig_grp, sig_types[in_sigs]),
  

• 	  GFP_KERNEL);
  

• if (!in)

• return NULL;
  

• out = devm_kzalloc(dev,

• 	   offsetof(struct cti_trig_grp, sig_types[out_sigs]),
  

• 	   GFP_KERNEL);
  

• if (!out)

• return NULL;
  

• tc->con_in = in;
• tc->con_out = out;
• tc->con_in->nr_sigs = in_sigs;
• tc->con_out->nr_sigs = out_sigs;
• return tc;

+}

+/*

• • Add a default connection if nothing else is specified.
• • single connection based on max in/out info, no assoc device
• */

+int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) +{

• int ret = 0;
• int n_trigs = drvdata->config.nr_trig_max;
• u32 n_trig_mask = GENMASK(n_trigs - 1, 0);
• struct cti_trig_con *tc = NULL;
• /*

• * Assume max trigs for in and out,
  

• * all used, default sig types allocated
  

• */
  

• tc = cti_allocate_trig_con(dev, n_trigs, n_trigs);
• if (!tc)

• return -ENOMEM;
  

• tc->con_in->used_mask = n_trig_mask;
• tc->con_out->used_mask = n_trig_mask;
• ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default");
• return ret;

+}

+/** cti ect operations **/ +int cti_enable(struct coresight_device *csdev) +{

• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• /* enable hardware with refcount */
• return cti_enable_hw(drvdata, true);

+}

+int cti_disable(struct coresight_device *csdev) +{

• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• /* disable hardware with refcount */
• return cti_disable_hw(drvdata, true);

+}

+const struct coresight_ops_ect cti_ops_ect = {

• .enable = cti_enable,
• .disable = cti_disable,

+};

+const struct coresight_ops cti_ops = {

• .ect_ops = &cti_ops_ect,

+};

+/*

• • Free up CTI specific resources
• • called by dev->release, need to call down to underlying csdev release.
• */

+static void cti_device_release(struct device *dev) +{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_drvdata *ect_item, *ect_tmp;
• mutex_lock(&ect_mutex);
• /* remove from the list */
• list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) {

• if (ect_item == drvdata) {
  

• 	list_del(&ect_item->node);
  

• 	goto ect_list_item_removed;
  

nit: s/goto ../break ?

• }
  

• }

+ect_list_item_removed:

• mutex_unlock(&ect_mu tex);
• if (drvdata->csdev_release)

• drvdata->csdev_release(dev);
  

+}

Rest looks good to me.

Cheers Suzuki

On Mon, Aug 19, 2019 at 10:13:48PM +0100, Mike Leach wrote:

Adds sysfs access to the coresight management registers.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 67 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a832b8c6b866..20a9b30c9755 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,7 @@ static ssize_t enable_show(struct device *dev, return size; } -static ssize_t enable_store(struct device *dev,

• 	    struct device_attribute *attr,
  

+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,

Redundant change?

The rest code in this patch looks good to me.

Thanks, Leo Yan

	    const char *buf, size_t size)

{ int ret = 0; @@ -56,9 +55,67 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable); +static ssize_t ctmid_show(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.ctm_id);

+} +static DEVICE_ATTR_RO(ctmid);

/* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr,

• &dev_attr_ctmid.attr,
• NULL,

+};

+/* register based attributes */

+/* macro to access RO registers with power check only (no enable check). */ +#define coresight_cti_reg(name, offset) \ +static ssize_t name##_show(struct device *dev, \

• 	   struct device_attribute *attr, char *buf)	\
  

+{ \

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
• u32 val = 0; \
• pm_runtime_get_sync(dev->parent); \
• spin_lock(&drvdata->spinlock); \
• if (drvdata->config.hw_powered) \

• val = readl_relaxed(drvdata->base + offset);		\
  

• spin_unlock(&drvdata->spinlock); \
• pm_runtime_put_sync(dev->parent); \
• return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \

+} \ +static DEVICE_ATTR_RO(name)

+/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);

+static struct attribute *coresight_cti_mgmt_attrs[] = {

• &dev_attr_devaff0.attr,
• &dev_attr_devaff1.attr,
• &dev_attr_authstatus.attr,
• &dev_attr_devarch.attr,
• &dev_attr_devid.attr,
• &dev_attr_devtype.attr,
• &dev_attr_pidr0.attr,
• &dev_attr_pidr1.attr,
• &dev_attr_pidr2.attr,
• &dev_attr_pidr3.attr,
• &dev_attr_pidr4.attr, NULL,

}; @@ -66,7 +123,13 @@ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, }; +static const struct attribute_group coresight_cti_mgmt_group = {

• .attrs = coresight_cti_mgmt_attrs,
• .name = "mgmt",

+};

const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group,

• &coresight_cti_mgmt_group, NULL,

}; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 82e563cdc879..aba6b789c969 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -22,6 +22,7 @@ #define CORESIGHT_CLAIMCLR 0xfa4 #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_AUTHSTATUS 0xfb8 #define CORESIGHT_DEVID 0xfc8

#define CORESIGHT_DEVTYPE 0xfcc

2.17.1

---

CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight

On Mon, Sep 02, 2019 at 02:22:47PM +0100, Mike Leach wrote:

Hi Leo,

On Mon, 2 Sep 2019 at 08:44, Leo Yan leo.yan@linaro.org wrote:

...

On Mon, Aug 19, 2019 at 10:13:48PM +0100, Mike Leach wrote:

...

Adds sysfs access to the coresight management registers.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 67 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a832b8c6b866..20a9b30c9755 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,7 @@ static ssize_t enable_show(struct device *dev, return size; }

-static ssize_t enable_store(struct device *dev,

•                     struct device_attribute *attr,
  

+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,

Redundant change?

The rest code in this patch looks good to me.

Fixup for function parameter alignment mentioned in v3 comments

Ah, if so it's better to fixup in the first place in patch 01.

Thanks, Leo Yan

On Mon, Aug 19, 2019 at 10:13:48PM +0100, Mike Leach wrote:

Adds sysfs access to the coresight management registers.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 67 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index a832b8c6b866..20a9b30c9755 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,7 @@ static ssize_t enable_show(struct device *dev, return size; } -static ssize_t enable_store(struct device *dev,

• 	    struct device_attribute *attr,
  

+static ssize_t enable_store(struct device *dev, struct device_attribute *attr,

This line doesn't bring anything to the patch - please revert.

	    const char *buf, size_t size)

{ int ret = 0; @@ -56,9 +55,67 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable); +static ssize_t ctmid_show(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.ctm_id);

+} +static DEVICE_ATTR_RO(ctmid);

/* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr,

• &dev_attr_ctmid.attr,
• NULL,

+};

+/* register based attributes */

+/* macro to access RO registers with power check only (no enable check). */ +#define coresight_cti_reg(name, offset) \ +static ssize_t name##_show(struct device *dev, \

• 	   struct device_attribute *attr, char *buf)	\
  

+{ \

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
• u32 val = 0; \
• pm_runtime_get_sync(dev->parent); \
• spin_lock(&drvdata->spinlock); \
• if (drvdata->config.hw_powered) \

• val = readl_relaxed(drvdata->base + offset);		\
  

• spin_unlock(&drvdata->spinlock); \
• pm_runtime_put_sync(dev->parent); \
• return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \

+} \ +static DEVICE_ATTR_RO(name)

+/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);

+static struct attribute *coresight_cti_mgmt_attrs[] = {

• &dev_attr_devaff0.attr,
• &dev_attr_devaff1.attr,
• &dev_attr_authstatus.attr,
• &dev_attr_devarch.attr,
• &dev_attr_devid.attr,
• &dev_attr_devtype.attr,
• &dev_attr_pidr0.attr,
• &dev_attr_pidr1.attr,
• &dev_attr_pidr2.attr,
• &dev_attr_pidr3.attr,
• &dev_attr_pidr4.attr, NULL,

}; @@ -66,7 +123,13 @@ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, }; +static const struct attribute_group coresight_cti_mgmt_group = {

• .attrs = coresight_cti_mgmt_attrs,
• .name = "mgmt",

+};

const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group,

• &coresight_cti_mgmt_group, NULL,

}; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 82e563cdc879..aba6b789c969 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -22,6 +22,7 @@ #define CORESIGHT_CLAIMCLR 0xfa4 #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 +#define CORESIGHT_DEVARCH 0xfbc

With the above change:

Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org

#define CORESIGHT_AUTHSTATUS 0xfb8 #define CORESIGHT_DEVID 0xfc8

#define CORESIGHT_DEVTYPE 0xfcc

2.17.1

On Fri, 27 Sep 2019 at 07:49, Suzuki K Poulose suzuki.poulose@arm.com wrote:

Hi Mike,

Looks good overall. I have some comments about how we mix integer and string output for write/read for sysfs handles.

On 19/08/2019 22:13, Mike Leach wrote:

...

Adds a user API to allow programming of CTI by trigger ID and channel number. This will take the channel and trigger ID supplied by the user and program the appropriate register values.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 355 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.c | 157 +++++++- drivers/hwtracing/coresight/coresight-cti.h | 34 ++ 3 files changed, 545 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 4055e392530d..dbbfd1de58b3 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -480,6 +480,355 @@ static struct attribute *coresight_cti_regs_attrs[] = { NULL, };

+/* CTI channel x-trigger programming */ +static int +cti_trig_op_parse(struct device *dev, enum cti_chan_op op,

•           enum cti_trig_dir dir, const char *buf, size_t size)
  

+{

• u32 chan_idx;
  

• u32 trig_idx;
  

• int items, err = size;
  

nit: If we set this to -EINVAL, you could remove the else case below. We can overwrite the err with size only when we have parsed properly.

...

• /* extract chan idx and trigger idx */
  

• items = sscanf(buf, "%d %d", &chan_idx, &trig_idx);
  

• if (items) {
  

To make sure we have got two values parsed, the above check must be :

    if (items == 2) {

...

•         err = cti_channel_trig_op(dev, op, dir, chan_idx, trig_idx);
  

•         if (!err)
  

•                 err = size;
  

• } else
  

•         err = -EINVAL;
  

• return err;
  

+}

...

+static ssize_t gate_enable_store(struct device *dev,

•                          struct device_attribute *attr,
  

•                          const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
  

• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {
  

Could we make it strict by making this (size == 4) ? But more on that below.

...

•         err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE_ALL, 0);
  

• } else {
  

•         if (kstrtoint(buf, 0, &channel))
  

•                 return -EINVAL;
  

•         err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE, channel);
  

• }
  

In general I am a bit concerned over mixing string and integer as input for an ABI. I don't have a perfect solution for "all" option, other than using -1 ! What do others think ?

There is only 4 channel so it would not be overly cumbersome to simply iterate over them. That would fix the mix between integer and strings along with removing the CTI_GATE_CHAN_ENABLE_ALL option.

...

• return err ? err : size;
  

+} +static DEVICE_ATTR_WO(gate_enable);

+static ssize_t gate_disable_store(struct device *dev,

•                           struct device_attribute *attr,
  

•                           const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
  

• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {
  

•         err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE_ALL, 0);
  

• } else {
  

•         if (kstrtoint(buf, 0, &channel))
  

•                 return -EINVAL;
  

•         err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE, channel);
  

• }
  

• return err ? err : size;
  

+} +static DEVICE_ATTR_WO(gate_disable);

...

+static ssize_t trig_filter_enable_show(struct device *dev,

•                                struct device_attribute *attr,
  

•                                char *buf)
  

+{

• unsigned long val;
  

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
  

• spin_lock(&drvdata->spinlock);
  

• val = drvdata->config.trig_filter_enable;
  

• spin_unlock(&drvdata->spinlock);
  

• return scnprintf(buf, PAGE_SIZE, "%s\n", val ? "enabled" : "disabled");
  

nit: I am not sure if "enabled"/"disabled" is preferred over 1/0. We follow the latter for enable_sink/source etc. Also for the "store" below for this field. So it may be a good idea to keep this consistent with the rest. e.g this might be more helpful for scripting.

I agree with Suzuki.

On Mon, Aug 19, 2019 at 10:13:50PM +0100, Mike Leach wrote:

Adds a user API to allow programming of CTI by trigger ID and channel number. This will take the channel and trigger ID supplied by the user and program the appropriate register values.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 355 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.c | 157 +++++++- drivers/hwtracing/coresight/coresight-cti.h | 34 ++ 3 files changed, 545 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 4055e392530d..dbbfd1de58b3 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -480,6 +480,355 @@ static struct attribute *coresight_cti_regs_attrs[] = { NULL, }; +/* CTI channel x-trigger programming */ +static int +cti_trig_op_parse(struct device *dev, enum cti_chan_op op,

•   enum cti_trig_dir dir, const char *buf, size_t size)
  

+{

• u32 chan_idx;
• u32 trig_idx;
• int items, err = size;
• /* extract chan idx and trigger idx */
• items = sscanf(buf, "%d %d", &chan_idx, &trig_idx);
• if (items) {

• err = cti_channel_trig_op(dev, op, dir, chan_idx, trig_idx);
  

• if (!err)
  

• 	err = size;
  

• } else

• err = -EINVAL;
  

• return err;

+}

+static ssize_t trigin_attach_store(struct device *dev,

• 		   struct device_attribute *attr,
  

• 		   const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_IN,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigin_attach);

+static ssize_t trigin_detach_store(struct device *dev,

• 		   struct device_attribute *attr,
  

• 		   const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_IN,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigin_detach);

+static ssize_t trigout_attach_store(struct device *dev,

• 		    struct device_attribute *attr,
  

• 		    const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_OUT,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigout_attach);

+static ssize_t trigout_detach_store(struct device *dev,

• 		    struct device_attribute *attr,
  

• 		    const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_OUT,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigout_detach);

+static ssize_t gate_enable_store(struct device *dev,

• 		 struct device_attribute *attr,
  

• 		 const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE_ALL, 0);
  

• } else {

• if (kstrtoint(buf, 0, &channel))
  

• 	return -EINVAL;
  

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE, channel);
  

• }
• return err ? err : size;

+} +static DEVICE_ATTR_WO(gate_enable);

+static ssize_t gate_disable_store(struct device *dev,

• 		  struct device_attribute *attr,
  

• 		  const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE_ALL, 0);
  

• } else {

• if (kstrtoint(buf, 0, &channel))
  

• 	return -EINVAL;
  

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE, channel);
  

• }
• return err ? err : size;

+} +static DEVICE_ATTR_WO(gate_disable);

+static int +chan_op_parse(struct device *dev, enum cti_chan_set_op op, const char *buf) +{

• int err = 0, channel = 0;
• if (kstrtoint(buf, 0, &channel))

• return -EINVAL;
  

• err = cti_channel_setop(dev, op, channel);
• return err;

+}

+static ssize_t chan_set_store(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_SET, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_set);

+static ssize_t chan_clear_store(struct device *dev,

• 		struct device_attribute *attr,
  

• 		const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_CLR, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_clear);

+static ssize_t chan_pulse_store(struct device *dev,

• 		struct device_attribute *attr,
  

• 		const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_PULSE, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_pulse);

+static ssize_t trig_filter_enable_show(struct device *dev,

• 		       struct device_attribute *attr,
  

• 		       char *buf)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• spin_lock(&drvdata->spinlock);
• val = drvdata->config.trig_filter_enable;
• spin_unlock(&drvdata->spinlock);
• return scnprintf(buf, PAGE_SIZE, "%s\n", val ? "enabled" : "disabled");

+}

+static ssize_t trig_filter_enable_store(struct device *dev,

• 			struct device_attribute *attr,
  

• 			const char *buf, size_t size)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (kstrtoul(buf, 0, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->config.trig_filter_enable = !!val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(trig_filter_enable);

+/* clear all xtrigger / channel programming */ +static ssize_t reset_xtrigs_store(struct device *dev,

• 		  struct device_attribute *attr,
  

• 		  const char *buf, size_t size)
  

+{

• int i;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• spin_lock(&drvdata->spinlock);
• /* clear the CTI trigger / channel programming registers */
• for (i = 0; i < config->nr_trig_max; i++) {

• config->ctiinen[i] = 0;
  

• config->ctiouten[i] = 0;
  

• }
• /* clear the other regs */
• config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0);
• config->asicctl = 0;
• config->ctiappset = 0;
• config->ctiinout_sel = 0;
• config->xtrig_rchan_sel = 0;
• /* if enabled then write through */
• if (CTI_PWR_ENA(config))

• cti_write_all_hw_regs(drvdata);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(reset_xtrigs);

+static ssize_t show_chan_sel_show(struct device *dev,

• 		  struct device_attribute *attr,
  

• 		  char *buf)
  

+{

• u32 val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• val = (u32)drvdata->config.xtrig_rchan_sel;
• return scnprintf(buf, PAGE_SIZE, "%d\n", val);

+}

+/* select a channel for the show_chan_xtrig function */ +static ssize_t show_chan_sel_store(struct device *dev,

• 		   struct device_attribute *attr,
  

• 		   const char *buf, size_t size)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (kstrtoul(buf, 0, &val))

• return -EINVAL;
  

• if (val > (drvdata->config.nr_ctm_channels - 1))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->config.xtrig_rchan_sel = val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(show_chan_sel);

+/* for the selected channel - show the signals attached. */ +static ssize_t show_chan_xtrigs_show(struct device *dev,

• 		     struct device_attribute *attr,
  

• 		     char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• int used = 0, reg_idx;
• int buf_sz = PAGE_SIZE;
• u32 chan_mask = BIT(cfg->xtrig_rchan_sel);
• used += scnprintf(buf, buf_sz, "IN: ");
• for (reg_idx = 0;

•     reg_idx < drvdata->config.nr_trig_max;
  

•     reg_idx++) {
  

• if (chan_mask & cfg->ctiinen[reg_idx]) {
  

• 	used += scnprintf(buf + used, buf_sz - used, "%d ",
  

• 			  reg_idx);
  

• }
  

• }
• used += scnprintf(buf + used, buf_sz - used, "OUT: ");
• for (reg_idx = 0;

•     reg_idx < drvdata->config.nr_trig_max;
  

•     reg_idx++) {
  

• if (chan_mask & cfg->ctiouten[reg_idx]) {
  

• 	used += scnprintf(buf + used, buf_sz - used, "%d ",
  

• 			  reg_idx);
  

• }
  

• }
• used += scnprintf(buf + used, buf_sz - used, "\n");
• return used;

+} +static DEVICE_ATTR_RO(show_chan_xtrigs);

+static ssize_t print_chan_list(struct device *dev,

• 	       char *buf, bool inuse)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• int size, i;
• unsigned long inuse_bits = 0, chan_mask;
• /* scan regs to get bitmap of channels in use. */
• spin_lock(&drvdata->spinlock);
• for (i = 0; i < config->nr_trig_max; i++) {

• inuse_bits |= config->ctiinen[i];
  

• inuse_bits |= config->ctiouten[i];
  

• }
• spin_unlock(&drvdata->spinlock);
• /* inverse bits if printing free channels */
• if (!inuse)

• inuse_bits = ~inuse_bits;
  

• /* list of channels, or 'none' */
• chan_mask = GENMASK(config->nr_ctm_channels - 1, 0);
• if (inuse_bits & chan_mask)

• size = bitmap_print_to_pagebuf(true, buf, &inuse_bits,
  

• 			       config->nr_ctm_channels);
  

• else

• size = scnprintf(buf, PAGE_SIZE, "none\n");
  

• return size;

+}

+static ssize_t list_inuse_show(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       char *buf)
  

+{

• return print_chan_list(dev, buf, true);

+} +static DEVICE_ATTR_RO(list_inuse);

+static ssize_t list_free_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• return print_chan_list(dev, buf, false);

+} +static DEVICE_ATTR_RO(list_free);

+static ssize_t list_gate_enable_show(struct device *dev,

• 		     struct device_attribute *attr,
  

• 		     char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• unsigned long ctigate_bitmask = cfg->ctigate;
• int size = 0;
• if (cfg->ctigate == 0)

• size = scnprintf(buf, PAGE_SIZE, "none\n");
  

• else

• size = bitmap_print_to_pagebuf(true, buf, &ctigate_bitmask,
  

• 			       cfg->nr_ctm_channels);
  

• return size;

+} +static DEVICE_ATTR_RO(list_gate_enable);

+static struct attribute *coresight_cti_channel_attrs[] = {

• &dev_attr_trigin_attach.attr,
• &dev_attr_trigin_detach.attr,
• &dev_attr_trigout_attach.attr,
• &dev_attr_trigout_detach.attr,
• &dev_attr_gate_enable.attr,
• &dev_attr_gate_disable.attr,
• &dev_attr_chan_set.attr,
• &dev_attr_chan_clear.attr,
• &dev_attr_chan_pulse.attr,
• &dev_attr_trig_filter_enable.attr,
• &dev_attr_reset_xtrigs.attr,
• &dev_attr_show_chan_sel.attr,
• &dev_attr_show_chan_xtrigs.attr,
• &dev_attr_list_inuse.attr,
• &dev_attr_list_free.attr,
• &dev_attr_list_gate_enable.attr,
• NULL,

+};

/* sysfs groups */ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, @@ -495,9 +844,15 @@ static const struct attribute_group coresight_cti_regs_group = { .name = "regs", }; +static const struct attribute_group coresight_cti_channels_group = {

• .attrs = coresight_cti_channel_attrs,
• .name = "channels",

+};

const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group, &coresight_cti_mgmt_group, &coresight_cti_regs_group,

• &coresight_cti_channels_group, NULL,

}; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 0368fa7c6179..9b0441d8be61 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -36,7 +36,7 @@ static DEFINE_MUTEX(ect_mutex); DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); /* write set of regs to hardware - call with spinlock claimed */ -static void cti_write_all_hw_regs(struct cti_drvdata *drvdata) +void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; int i; @@ -295,6 +295,161 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) return ret; } +/** cti channel api **/ +/* attach/detach channel from trigger - write through if enabled. */ +int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,

• 	enum cti_trig_dir direction, u32 channel_idx,
  

• 	u32 trigger_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 trig_bitmask;
• u32 chan_bitmask;
• u32 reg_value;
• int reg_offset;
• /* ensure indexes in range */
• if ((channel_idx >= config->nr_ctm_channels) ||

•   (trigger_idx >= config->nr_trig_max))
  

• return -EINVAL;
  

• trig_bitmask = BIT(trigger_idx);
• /* ensure registered triggers and not out filtered */
• if (direction == CTI_TRIG_IN) {

• if (!(trig_bitmask & config->trig_in_use))
  

• 	return -EINVAL;
  

• } else {

• if (!(trig_bitmask & config->trig_out_use))
  

• 	return -EINVAL;
  

• if ((config->trig_filter_enable) &&
  

•     (config->trig_out_filter & trig_bitmask))
  

• 	return -EINVAL;
  

• }
• /* update the local register values */
• chan_bitmask = BIT(channel_idx);
• reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :

•       CTIOUTEN(trigger_idx));
  

• spin_lock(&drvdata->spinlock);
• /* read - modify write - the trigger / channel enable value */
• reg_value = direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] :

•      config->ctiouten[trigger_idx];
  

• if (op == CTI_CHAN_ATTACH)

• reg_value |= chan_bitmask;
  

• else

• reg_value &= ~chan_bitmask;
  

• /* write local copy */
• if (direction == CTI_TRIG_IN)

• config->ctiinen[trigger_idx] = reg_value;
  

• else

• config->ctiouten[trigger_idx] = reg_value;
  

• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, reg_offset, reg_value);
  

• spin_unlock(&drvdata->spinlock);
• return 0;

+}

+int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op,

• 	u32 channel_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 chan_bitmask;
• u32 reg_value;
• int err = 0;
• if (channel_idx >= config->nr_ctm_channels)

• return -EINVAL;
  

• chan_bitmask = BIT(channel_idx);
• spin_lock(&drvdata->spinlock);
• reg_value = config->ctigate;
• switch (op) {
• case CTI_GATE_CHAN_ENABLE:

• reg_value |= chan_bitmask;
  

• break;
  

• case CTI_GATE_CHAN_DISABLE:

• reg_value &= ~chan_bitmask;
  

• break;
  

• case CTI_GATE_CHAN_ENABLE_ALL:

• reg_value = GENMASK(config->nr_ctm_channels - 1, 0);
  

• break;
  

• case CTI_GATE_CHAN_DISABLE_ALL:

• reg_value = 0x0;
  

• break;
  

• default:

• err = -EINVAL;
  

• break;
  

• }
• if (err == 0) {

• config->ctigate = reg_value;
  

• if (CTI_PWR_ENA(config))
  

• 	cti_write_single_reg(drvdata, CTIGATE, reg_value);
  

• }
• spin_unlock(&drvdata->spinlock);
• return err;

+}

+int cti_channel_setop(struct device *dev, enum cti_chan_set_op op,

•       u32 channel_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 chan_bitmask;
• u32 reg_value;
• u32 reg_offset;
• int err = 0;
• if (channel_idx >= config->nr_ctm_channels)

• return -EINVAL;
  

• chan_bitmask = BIT(channel_idx);
• spin_lock(&drvdata->spinlock);
• reg_value = config->ctiappset;
• switch (op) {
• case CTI_CHAN_SET:

• config->ctiappset |= chan_bitmask;
  

• reg_value  = config->ctiappset;
  

• reg_offset = CTIAPPSET;
  

• break;
  

• case CTI_CHAN_CLR:

• config->ctiappset &= ~chan_bitmask;
  

• reg_value = chan_bitmask;
  

• reg_offset = CTIAPPCLEAR;
  

• break;
  

• case CTI_CHAN_PULSE:

• config->ctiappset &= ~chan_bitmask;
  

I understand managing config->ctiappset for CTI_CHAN_SET and CTI_CHAN_CLR operations but not for CTI_CHAN_PULSE. From what I read in the documentation setting a bit in CTIAPPPULSE will create a pulse for that channel regardless of the value of register CTIAPPSET.

• reg_value = chan_bitmask;
  

• reg_offset = CTIAPPPULSE;
  

• break;
  

• default:

• err = -EINVAL;
  

• break;
  

• }
• if ((err == 0) && CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, reg_offset, reg_value);
  

• spin_unlock(&drvdata->spinlock);
• return err;

+}

/** cti ect operations **/ int cti_enable(struct coresight_device *csdev) { diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index db8667a2691c..865d3d0ffb11 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -174,6 +174,32 @@ struct cti_drvdata { void (*csdev_release)(struct device *dev); }; +/*

• • Channel operation types.
• */

+enum cti_chan_op {

• CTI_CHAN_ATTACH,
• CTI_CHAN_DETACH,

+};

+enum cti_trig_dir {

• CTI_TRIG_IN,
• CTI_TRIG_OUT,

+};

+enum cti_chan_gate_op {

• CTI_GATE_CHAN_ENABLE,
• CTI_GATE_CHAN_DISABLE,
• CTI_GATE_CHAN_ENABLE_ALL,
• CTI_GATE_CHAN_DISABLE_ALL,

+};

+enum cti_chan_set_op {

• CTI_CHAN_SET,
• CTI_CHAN_CLR,
• CTI_CHAN_PULSE,

+};

/* private cti driver fns & vars */ extern const struct attribute_group *coresight_cti_groups[]; int cti_add_default_connection(struct device *dev, @@ -186,8 +212,16 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, int out_sigs); int cti_enable(struct coresight_device *csdev); int cti_disable(struct coresight_device *csdev); +void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); +int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,

• 	enum cti_trig_dir direction, u32 channel_idx,
  

• 	u32 trigger_idx);
  

+int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op,

• 	u32 channel_idx);
  

+int cti_channel_setop(struct device *dev, enum cti_chan_set_op op,

•       u32 channel_idx);
  

struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); -- 2.17.1

On Mon, Aug 19, 2019 at 10:13:51PM +0100, Mike Leach wrote:

Adds new .txt file describing the bindings required to define CTI in the device trees.

Adds an include file to dt-bindings/arm to define constants describing common signal functionality used in CoreSight and generic usage.

As we talked about, this will need to comply with the new DT schema format but I decided to give it a read anyway.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../bindings/arm/coresight-ect-cti.txt | 396 ++++++++++++++++++ .../devicetree/bindings/arm/coresight.txt | 7 + MAINTAINERS | 2 + include/dt-bindings/arm/coresight-cti-dt.h | 36 ++ 4 files changed, 441 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-ect-cti.txt create mode 100644 include/dt-bindings/arm/coresight-cti-dt.h

diff --git a/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt new file mode 100644 index 000000000000..5f78b610be4d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt @@ -0,0 +1,396 @@ +*CoreSight Embedded Cross Trigger Components

+The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected +to one or more CoreSight components and/or a CPU, with CTIs interconnected in +a star topology via the CTM (which is not programmable). The ECT components +are not part of the trace generation data path and are thus not part of the +CoreSight graph described in the general CoreSight bindings file coresight.txt.

+The CTI component properties define the connections between the individual CTI +and the components it is directly connected to, consisting of input and output +hardware trigger signals. CTIs can have a maximum number of input and output +hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The number is +defined at design time, the maximum of each defined in the DEVID register. +Note that some hardware trigger signals can be connected to non-CoreSight +components (e.g. UART etc) depending on hardware implementation.

+CTIs are interconnected in a star topology via the CTM, using a number of +programmable channels usually 4, but again implementation defined and described +in the DEVID register. The star topology is not required to be described in the +bindings as the actual connections are software programmable.

+In general the connections between CTI and components via the trigger signals +are implementation defined, other than when v8 core and ETM is present. The v8 +architecture defines the required signal connections between CPU core and CTI, +and ETM and CTI, if the ETM if present.

+Certain triggers between CoreSight devices and the CTI have specific types / +usages. These can be defined along with the signal indexes with the constants +defined in <dt-bindings/arm/coresight-cti-dt.h>

+For example a CTI connected to a core will usually have a DBGREQ signal. This +is defined in the binding as type PE_EDBGREQ. These types will appear in an +optional array alongside the signal indexes. Omitting types will default all +signals to GEN_IO.

+The minimum required binding for a CTI consists of only the following required +properties defined in coresight.txt:-

+* Required properties:

• • compatible: These have to be supplemented with "arm,primecell" as

•  drivers are using the AMBA bus interface.
  

• - Coresight Cross Trigger Interface (CTI):
  

• 	"arm,coresight-cti", "arm,primecell";
  

I think the above requires better formatting.

• • reg
• • clocks
• • clock-names

+e.g.(1) +/* sys cti 0 */ +cti0: cti@20020000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x20020000 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;

+};

+This will result in the driver using the DEVID register to set the +input and output triggers and channels in use. Any user / client +application will require additional information on the connections +between the CTI and other components for correct operation.

+Where information is immediately available for the component connections then +a series of trigger connection nodes can be defined (trig-conns).

+These connections explicitly define the input and output triggers between the +CTI and a connected component. Connections to an cpu use the standard "cpu"

s/an cpu/a cpu

+property, connections to other CoreSight components use the arm,cs-dev-assoc +property.

+e.g.(2) +/* CPU CTI connected to Core and ETM */ +cti@858000 {

•   compatible = "arm,coresight-cti", "arm,primecell";
  

•   reg = <0x858000 0x1000>;
  

•   clocks = <&rpmcc RPM_QDSS_CLK>;
  

•   clock-names = "apb_pclk";
  

•   trig-conns@0 {
  

• 	arm,trig-in-sigs = <4 5 6 7>;
  

• 	arm,trig-in-types = <ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT>;
  

• 	arm,trig-out-sigs = <4 5 6 7>;
  

• 	arm,trig-out-types = <ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN>;
  

• 	arm,cs-dev-assoc = <&etm0>;
  

•   };
  

•   trig-conns@1 {
  

•        cpu = <&CPU0>;
  

•        arm,trig-in-sigs = <0 1>;
  

•        arm,trig-in-types = <PE_DBGTRIGGER
  

• 			   PE_PMUIRQ>;
  

•        arm,trig-out-sigs=<0 1 2 >;
  

•        arm,trig-out-types = <PE_EDBGREQ
  

• 			  PE_DBGRESTART
  

• 			  PE_CTIIRQ>;
  

•        arm,trig-filters = <0>;
  

•   };
  

+};

+Note that where input and output triggers are defined as above, then the driver +will limit the channel connection sysfs API to using only the defined signals.

+The arm,trig-filters property blocks output signals that could cause system +issues if set - such as the PE_EDBGREQ signal into a CPU. The filtering is +enabled by default, but can be disabled at runtime.

+Where the signals are connected to a device that is not CoreSight device then +no association is registered. In this case a name can be used to identify the +component (arm,trig-conn-name)

+e.g.(3) +/* CTI connected to none coresight devices */ +cti@20110000 { /* Juno sys_cti_1 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20110000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<0>;
  

• arm,trig-in-types=<GEN_INTREQ>;
  

• arm,trig-out-sigs=<0>;
  

• arm,trig-out-types=<GEN_HALTREQ>;
  

• arm,trig-conn-name = "sys_profiler";
  

• };
• trig-conns@1 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "watchdog";
  

• };
• trig-conns@2 {

• arm,trig-out-sigs=<1 6>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "g_counter";
  

• };

+};

+Finally, a CTI that is an architecturally defined v8 CTI connected to a cpu

To be consistent with what you have in the previous paragraphs:

s/cpu/CPU

+and optional ETM may be declared as:

+e.g.(4) +/* v8 architectural CTI, connected to core and ETM */ +cti@859000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x859000 0x1000>;
• clocks = <&rpmcc RPM_QDSS_CLK>;
• clock-names = "apb_pclk";
• arm,cti-v8-arch;
• cpu = <&CPU1>;
• arm,cs-dev-assoc = <&etm1>;

+};

+This example will result in the same internal structure as e.g.(2)

+The arm,cti-v8-arch property declares this as a v8 CTI, the cpu property must +be present, and a single arm,cs-dev-assoc may be present to define an attached +ETM. No additional trig-conns nodes are permitted. The driver will build a +connection model according to architectural requirements. This will include +a filter on the CPU dbgreq signal as described above.

s/dbgreq/DBGREQ

+All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by +a CTM. On these systems a CTM index is declared to associate CTI devices that +are interconnected via the CTM.

• e.g.
• arm,cti-ctm-id=<2>

+CTI devices with the same CTM ID are considered connected by the CTM. If this +parameter is absent then all CTIs are considered interconnected by the same +CTM.

+*Summary of CTI required properties:

• • compatible : should be "arm,coresight-cti"; supplemented with

•  "arm,primecell" since this driver is using the AMBA bus
  

•  interface.
  

• • reg: physical base address and length of the register

•  set(s) of the component.
  

• • clocks: the clocks associated to this component.
• • clock-names: the name of the clocks referenced by the code.

•  Since we are using the AMBA framework, the name of the clock
  

•  providing the interconnect should be "apb_pclk", and some
  

•  coresight blocks also have an additional clock "atclk", which
  

•  clocks the core of that coresight component. The latter clock
  

•  is optional.
  

+*Summary of CTI optional properties:

• • trig-conns: defines a connection node between CTI and a component.

•  Component may be a CPU, CoreSight device, any other hardware device
  

•  or simple external IO lines.
  

• • arm,cti-v8-arch: Declares this CTI device as a v8 architecturally

•  defined device. Use in CTI base node only, no additional trig-conns
  

•  nodes permitted if this is declared.
  

• • cpu: defines a phandle reference to an associated CPU. Used in

•  trig-conns node, or in CTI base node when arm,cti-v8-arch present.
  

• • arm,cs-dev-assoc: defines a phandle reference to an associated

•  CoreSight trace device. When the associated trace device is enabled,
  

•  then the respective CTI will be enabled. Use in a trig-conns node,
  

•  or in CTI base node when arm,cti-v8-arch present. If the associated
  

•  device has not been registered then the node name will be stored as
  

•  the connection name for later resolution. If the associated device is
  

•  not a CoreSight device or not registered then the node name will
  

•  remain the connection name and automatic enabling will not occur.
  

• • arm,cti-ctm-id: Defines the interconnecting CTM for this device.

•  Use in CTI base node.
  

• • Properties valid in the trig-conns node:

• * arm,trig-in-sigs: List of CTI trigger in signals in use by a
  

•   trig-conns node.
  

• * arm,trig-in-types: List of types for the CTI trigger in
  

•   signals. Types in this array match to the corresponding signal
  

•   in the arm,trig-in-sigs array. If the -types array is smaller,
  

•   or omitted completely, then the types will default to GEN_IO.
  

• * arm,trig-out-sigs: List of CTI trigger out signals in use by a
  

•   trig-conns node.
  

• * arm,trig-out-types: List of types for the CTI trigger out
  

•   signals. Types in this array match to the corresponding signal
  

•   in the arm,trig-out-sigs array. If the "-types" array is
  

•   smaller, or omitted completely, then the types will default
  

•   to GEN_IO.
  

• * arm-trig-filters: List of CTI trigger out signals that will be
  

•   blocked from becoming active, unless filtering is disabled on
  

•   the driver.
  

•  *arm,trig-conn-name: defines a connection name that will be
  

•  displayed, if not overridden by the name of associated device
  

•  from arm,cs-dev-assoc or the CPU. Principle use for CTI that
  

•  are connected to non-CoreSight devices, or external IO.
  

The above lines need to be shifted to the right by one to align with "arm".

+e.g.(5) Combined examples showing all properties:

+a) Minimum CTI definition +cti0: cti@20020000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x20020000 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";

+};

+b) v8 architecturally defined CTI - CPU + ETM connections. +cti@859000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x859000 0x1000>;
• clocks = <&rpmcc RPM_QDSS_CLK>;
• clock-names = "apb_pclk";
• arm,cti-v8-arch;
• cpu = <&CPU1>;
• arm,cs-dev-assoc = <&etm1>;

+};

+c) Implementation defined CTI - CPU + ETM connections. +cti@858000 {

•   compatible = "arm,coresight-cti", "arm,primecell";
  

•   reg = <0x858000 0x1000>;
  

•   clocks = <&rpmcc RPM_QDSS_CLK>;
  

•   clock-names = "apb_pclk";
  

•   trig-conns@0 {
  

• 	arm,trig-in-sigs = <4 5 6 7>;
  

• 	arm,trig-in-types = <ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT>;
  

• 	arm,trig-out-sigs = <4 5 6 7>;
  

• 	arm,trig-out-types = <ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN>;
  

• 	arm,cs-dev-assoc = <&etm0>;
  

•   };
  

•   trig-conns@1 {
  

•        cpu = <&CPU0>;
  

•        arm,trig-in-sigs = <0 1>;
  

•        arm,trig-in-types = <PE_DBGTRIGGER
  

• 			   PE_PMUIRQ>;
  

•        arm,trig-out-sigs=<0 1 2 >;
  

•        arm,trig-out-types = <PE_EDBGREQ
  

• 			  PE_DBGRESTART
  

• 			  PE_CTIIRQ>;
  

•        arm,trig-filters = <0>;
  

•   };
  

•   arm,cti-ctm-id = <1>;
  

+};

+d) Implementation defined CTI - Coresight STM, ETF, ETR connections. +cti@20020000 { /*Juno sys_cti_0 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20020000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<2 3>;
  

• arm,trig-in-types=<SNK_FULL
  

• 		   SNK_ACQCOMP>;
  

• arm,trig-out-sigs=<0 1>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&etr_sys>;
  

• };
• trig-conns@1 {

• arm,trig-in-sigs=<0 1>;
  

• arm,trig-in-types=<SNK_FULL
  

• 		   SNK_ACQCOMP>;
  

• arm,trig-out-sigs=<7 6>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&etf_sys0>;
  

• };
• trig-conns@2 {

• arm,trig-in-sigs=<4 5 6 7>;
  

• arm,trig-in-types=<STM_TOUT_SPTE
  

• 		   STM_TOUT_SW
  

• 		   STM_TOUT_HETE
  

• 		   STM_ASYNCOUT>;
  

• arm,trig-out-sigs=<4 5>;
  

• arm,trig-out-types=<STM_HWEVENT
  

• 		    STM_HWEVENT>;
  

• arm,cs-dev-assoc = <&stm_sys>;
  

• };
• trig-conns@3 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&tpiu_sys>;
  

• };

+};

+e) Implementation defined CTI - none CoreSight component connections. +cti@20110000 { /* Juno sys_cti_1 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20110000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<0>;
  

• arm,trig-in-types=<GEN_INTREQ>;
  

• arm,trig-out-sigs=<0>;
  

• arm,trig-out-types=<GEN_HALTREQ>;
  

• arm,trig-conn-name = "sys_profiler";
  

• };
• trig-conns@1 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "watchdog";
  

• };
• trig-conns@2 {

• arm,trig-out-sigs=<1 6>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "g_counter";
  

• };

+}; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..a24713e48304 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -45,6 +45,10 @@ its hardware characteristcs. - Coresight Address Translation Unit (CATU) "arm,coresight-catu", "arm,primecell";

• - Coresight Cross Trigger Interface (CTI):
  

•   	"arm,coresight-cti", "arm,primecell";
  

• 	See coresight-ect-cti.txt for full CTI definitions.
  

• • reg: physical base address and length of the register set(s) of the component.

@@ -72,6 +76,9 @@ its hardware characteristcs.

• reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg".

+* Required properties for Coresight Cross Trigger Interface (CTI)

•   See coresight-ect-cti.txt for full CTI definitions.
  

• Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators and non-configurable funnels:

diff --git a/MAINTAINERS b/MAINTAINERS index 783569e3c4b4..a81f3bd8340a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1582,10 +1582,12 @@ R: Suzuki K Poulose suzuki.poulose@arm.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* +F: include/dt-bindings/arm/coresight-cti-dt.h F: Documentation/trace/coresight.txt F: Documentation/trace/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +F: Documentation/devicetree/bindings/arm/coresight-ect-cti.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: tools/perf/arch/arm/util/pmu.c F: tools/perf/arch/arm/util/auxtrace.c diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index 000000000000..88580b5a0388 --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • This header provides constants for the defined trigger signal
• • types on CoreSight CTI.
• */

+#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H

+#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ 3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP 13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN 15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW 19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT 21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24

+#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */

2.17.1