On 25/10/2023 03:53, Tao Zhang wrote:
CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit can be enabled for data collection by writing 1 to the first bit of CMB_CR register. This change is to add enable/disable function for CMB dataset by writing CMB_CR register.
Signed-off-by: Tao Zhang quic_taozha@quicinc.com Signed-off-by: Jinlong Mao quic_jinlmao@quicinc.com
drivers/hwtracing/coresight/coresight-tpdm.c | 31 ++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 8 +++++++ 2 files changed, 39 insertions(+)
Reviewed-by: James Clark james.clark@arm.com
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 97654aa..c8bb388 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -131,6 +131,11 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) return (drvdata->datasets & TPDM_PIDR0_DS_DSB); } +static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata) +{
- return (drvdata->datasets & TPDM_PIDR0_DS_CMB);
+}
static umode_t tpdm_dsb_is_visible(struct kobject *kobj, struct attribute *attr, int n) { @@ -267,6 +272,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) +{
- u32 val;
- val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
- val |= TPDM_CMB_CR_ENA;
- /* Set the enable bit of CMB control register to 1 */
- writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
/*
- TPDM enable operations
- The TPDM or Monitor serves as data collection component for various
@@ -281,6 +297,8 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) if (tpdm_has_dsb_dataset(drvdata)) tpdm_enable_dsb(drvdata);
- if (tpdm_has_cmb_dataset(drvdata))
tpdm_enable_cmb(drvdata);CS_LOCK(drvdata->base); } @@ -314,6 +332,17 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) +{
- u32 val;
- val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
- val &= ~TPDM_CMB_CR_ENA;
- /* Set the enable bit of CMB control register to 0 */
- writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
/* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { @@ -321,6 +350,8 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata) if (tpdm_has_dsb_dataset(drvdata)) tpdm_disable_dsb(drvdata);
- if (tpdm_has_cmb_dataset(drvdata))
tpdm_disable_cmb(drvdata);CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4115b2a1..0098c58 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -9,6 +9,12 @@ /* The max number of the datasets that TPDM supports */ #define TPDM_DATASETS 7 +/* CMB Subunit Registers */ +#define TPDM_CMB_CR (0xA00)
+/* Enable bit for CMB subunit */ +#define TPDM_CMB_CR_ENA BIT(0)
/* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) @@ -79,10 +85,12 @@
- PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
- PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
*/
- PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0
#define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) +#define TPDM_PIDR0_DS_CMB BIT(2) #define TPDM_DSB_MAX_LINES 256 /* MAX number of EDCR registers */