Remove the unnecessary lock "CS_{UN,}LOCK" in TPDM driver. This lock is only needed while writing the data to Coresight registers.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- drivers/hwtracing/coresight/coresight-tpdm.c | 2 -- 1 file changed, 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f4854af..b645612 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -114,11 +114,9 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) { u32 pidr;

- CS_UNLOCK(drvdata->base); /* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); - CS_LOCK(drvdata->base); }

/*

Introduce the new subtype of "CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM" for TPDM components in driver.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- drivers/hwtracing/coresight/coresight-core.c | 3 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 2 +- include/linux/coresight.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 118fcf2..661a5ea 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1093,6 +1093,7 @@ static int coresight_validate_source(struct coresight_device *csdev,

if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM && subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; @@ -1162,6 +1163,7 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM: case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: /* * Use the hash of source's device name as ID @@ -1212,6 +1214,7 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM: case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); /* Find the path by the hash. */ diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index b645612..abaff0b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -203,7 +203,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; desc.type = CORESIGHT_DEV_TYPE_SOURCE; - desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index bf70987..dc19a44 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -62,6 +62,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, };

DSB is used for monitoring “events”. Events are something that occurs at some point in time. It could be a state decode, the act of writing/reading a particular address, a FIFO being empty, etc. This decoding of the event desired is done outside TPDM. DSB subunit need to be configured in enablement and disablement. A struct that specifics associated to dsb dataset is needed. It saves the configuration and parameters of the dsb datasets. This change is to add this struct and initialize the configuration of DSB subunit.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++++++---- drivers/hwtracing/coresight/coresight-tpdm.h | 18 ++++++++ 2 files changed, 74 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index abaff0b..951ad4d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,23 +20,57 @@

DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");

+static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_DSB); +} + +static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) +{ + if (tpdm_has_dsb_dataset(drvdata)) { + memset(drvdata->dsb, 0, sizeof(struct dsb_dataset)); + + drvdata->dsb->trig_ts = true; + drvdata->dsb->trig_type = false; + } +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val;

- /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + writel_relaxed(val, drvdata->base + TPDM_DSB_TIER); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + /* Set trigger type */ + if (drvdata->dsb->trig_type) + val |= TPDM_DSB_CR_TRIG_TYPE; + else + val &= ~TPDM_DSB_CR_TRIG_TYPE; + /* Set the enable bit of DSB control register to 1 */ val |= TPDM_DSB_CR_ENA; writel_relaxed(val, drvdata->base + TPDM_DSB_CR); }

-/* TPDM enable operations */ +/* + * TPDM enable operations + * The TPDM or Monitor serves as data collection component for various + * dataset types. It covers Basic Counts(BC), Tenure Counts(TC), + * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single + * Bit(DSB). This function will initialize the configuration according + * to the dataset type supported by the TPDM. + */ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base);

- /* Check if DSB datasets is present for TPDM. */ - if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + if (tpdm_has_dsb_dataset(drvdata)) tpdm_enable_dsb(drvdata);

CS_LOCK(drvdata->base); @@ -76,8 +110,7 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base);

- /* Check if DSB datasets is present for TPDM. */ - if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + if (tpdm_has_dsb_dataset(drvdata)) tpdm_disable_dsb(drvdata);

CS_LOCK(drvdata->base); @@ -110,13 +143,23 @@ static const struct coresight_ops tpdm_cs_ops = { .source_ops = &tpdm_source_ops, };

-static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) { u32 pidr;

/* Get the datasets present on the TPDM. */ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + + if (tpdm_has_dsb_dataset(drvdata) && (!drvdata->dsb)) { + drvdata->dsb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->dsb), GFP_KERNEL); + if (!drvdata->dsb) + return -ENOMEM; + } + tpdm_reset_datasets(drvdata); + + return 0; }

/* @@ -179,6 +222,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) struct coresight_platform_data *pdata; struct tpdm_drvdata *drvdata; struct coresight_desc desc = { 0 }; + int ret;

pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) @@ -198,6 +242,10 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)

drvdata->base = base;

+ ret = tpdm_datasets_setup(drvdata); + if (ret) + return ret; + /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); if (!desc.name) @@ -214,7 +262,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(drvdata->csdev);

spin_lock_init(&drvdata->spinlock); - tpdm_init_default_data(drvdata); + /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev);

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 5438540..f59e751 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -11,8 +11,14 @@

/* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +#define TPDM_DSB_TIER (0x784) + /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) +/* Enable bit for DSB subunit trigger type */ +#define TPDM_DSB_CR_TRIG_TYPE BIT(12) +/* Enable bit for DSB subunit trigger timestamp */ +#define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1)

/* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) @@ -41,6 +47,16 @@ #define TPDM_PIDR0_DS_DSB BIT(1)

/** + * struct dsb_dataset - specifics associated to dsb dataset + * @trig_ts: Enable/Disable trigger timestamp. + * @trig_type: Enable/Disable trigger type. + */ +struct dsb_dataset { + bool trig_ts; + bool trig_type; +}; + +/** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. * @dev: The device entity associated to this component. @@ -48,6 +64,7 @@ * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. + * @dsb Specifics associated to TPDM DSB. */

struct tpdm_drvdata { @@ -57,6 +74,7 @@ struct tpdm_drvdata { spinlock_t spinlock; bool enable; unsigned long datasets; + struct dsb_dataset *dsb; };

#endif /* _CORESIGHT_CORESIGHT_TPDM_H */

The nodes are needed to set or show the trigger timestamp and trigger type. This change is to add these nodes to achieve these function.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 22 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 95 ++++++++++++++++++++++ 2 files changed, 117 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 2936226..9e26e30 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,25 @@ Description:

Accepts only one value - 1. 1 : Reset the dataset of the tpdm + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the trigger type of the DSB for tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the trigger timestamp of the DSB for tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB trigger type to false + 1 : Set the DSB trigger type to true diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d6e7c8c..8e11c9b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -25,6 +25,18 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) return (drvdata->datasets & TPDM_PIDR0_DS_DSB); }

+static umode_t tpdm_dsb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && tpdm_has_dsb_dataset(drvdata)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) { @@ -232,8 +244,91 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, };

+static ssize_t dsb_trig_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_type); +} + +/* + * Trigger type (boolean): + * false - Disable trigger type. + * true - Enable trigger type. + */ +static ssize_t dsb_trig_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_type = true; + else + drvdata->dsb->trig_type = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_type); + +static ssize_t dsb_trig_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->trig_ts); +} + +/* + * Trigger timestamp (boolean): + * false - Disable trigger timestamp. + * true - Enable trigger timestamp. + */ +static ssize_t dsb_trig_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + if (val) + drvdata->dsb->trig_ts = true; + else + drvdata->dsb->trig_ts = false; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_trig_ts); + +static struct attribute *tpdm_dsb_attrs[] = { + &dev_attr_dsb_trig_ts.attr, + &dev_attr_dsb_trig_type.attr, + NULL, +}; + +static struct attribute_group tpdm_dsb_attr_grp = { + .attrs = tpdm_dsb_attrs, + .is_visible = tpdm_dsb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, + &tpdm_dsb_attr_grp, NULL, };

Add the nodes to set value for DSB edge control and DSB edge control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control.

Add the nodes to configure DSB edge control and DSB edge control mask. Each DSB subunit TPDM maximum of 256 edge detections can be configured. The index and value sysfs files need to be paired and written to order. The index sysfs file is to set the index number of the edge detection which needs to be configured. And the value sysfs file is to set the control or mask for the edge detection. DSB edge detection control should be set as the following values. 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And DSB edge mask should be set as 0 or 1. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask.

Add the nodes to read a set of the edge control value and mask of the DSB in TPDM.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 51 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 177 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 63 ++++++++ 3 files changed, 288 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e17d1b4..097fdc4 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -57,3 +57,54 @@ Description: Bit[3] : Set to 0 for low performance mode. Set to 1 for high performance mode. Bit[4:8] : Select byte lane for high performance mode. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the index number of the edge detection for the DSB + subunit TPDM. Since there are at most 256 edge detections, this + value ranges from 0 to 255. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + Write a data to control the edge detection corresponding to + the index number. Before writing data to this sysfs file, + "ctrl_idx" should be written first to configure the index + number of the edge detection which needs to be controlled. + + Accepts only one of the following values. + 0 - Rising edge detection + 1 - Falling edge detection + 2 - Rising and falling edge detection (toggle detection) + + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + Write a data to mask the edge detection corresponding to the index + number. Before writing data to this sysfs file, "ctrl_idx" should + be written first to configure the index number of the edge detection + which needs to be masked. + + Accepts only one of the 2 values - 0 or 1. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + Read a set of the edge control value of the DSB in TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + Read a set of the edge control mask of the DSB in TPDM. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 2424eb7..ba61e6a 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -21,6 +21,29 @@

DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");

+/* Read dataset array member with the index number */ +static ssize_t tpdm_simple_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct tpdm_dataset_attribute *tpdm_attr = + container_of(attr, struct tpdm_dataset_attribute, attr); + + if (tpdm_attr->idx >= tpdm_attr->max) + return -EINVAL; + + switch (tpdm_attr->mem) { + case DSB_EDGE_CTRL: + return sysfs_emit(buf, "0x%x\n", + drvdata->dsb->edge_ctrl[tpdm_attr->idx]); + case DSB_EDGE_CTRL_MASK: + return sysfs_emit(buf, "0x%x\n", + drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]); + default: + return -EINVAL; + } +} + static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) { return (drvdata->datasets & TPDM_PIDR0_DS_DSB); @@ -71,7 +94,14 @@ static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val)

static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { - u32 val; + u32 val, i; + + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl[i], + drvdata->base + TPDM_DSB_EDCR(i)); + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], + drvdata->base + TPDM_DSB_EDCMR(i));

val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ @@ -296,6 +326,109 @@ static ssize_t dsb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_mode);

+static ssize_t ctrl_idx_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->edge_ctrl_idx); +} + +/* + * The EDCR registers can include up to 16 32-bit registers, and each + * one can be configured to control up to 16 edge detections(2 bits + * control one edge detection). So a total 256 edge detections can be + * configured. This function provides a way to set the index number of + * the edge detection which needs to be configured. + */ +static ssize_t ctrl_idx_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_DSB_MAX_LINES)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->edge_ctrl_idx = val; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_RW(ctrl_idx); + +/* + * This function is used to control the edge detection according + * to the index number that has been set. + * "edge_ctrl" should be one of the following values. + * 0 - Rising edge detection + * 1 - Falling edge detection + * 2 - Rising and falling edge detection (toggle detection) + */ +static ssize_t ctrl_val_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val, edge_ctrl; + int reg; + + if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * There are 2 bit per DSB Edge Control line. + * Thus we have 16 lines in a 32bit word. + */ + reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); + val = drvdata->dsb->edge_ctrl[reg]; + val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx); + val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx); + drvdata->dsb->edge_ctrl[reg] = val; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(ctrl_val); + +static ssize_t ctrl_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + u32 set; + int reg; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* + * There is 1 bit per DSB Edge Control Mark line. + * Thus we have 32 lines in a 32bit word. + */ + reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); + set = drvdata->dsb->edge_ctrl_mask[reg]; + if (val) + set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); + else + set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); + drvdata->dsb->edge_ctrl_mask[reg] = set; + spin_unlock(&drvdata->spinlock); + + return size; +} +static DEVICE_ATTR_WO(ctrl_mask); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -367,6 +500,37 @@ static ssize_t dsb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_trig_ts);

+static struct attribute *tpdm_dsb_edge_attrs[] = { + &dev_attr_ctrl_idx.attr, + &dev_attr_ctrl_val.attr, + &dev_attr_ctrl_mask.attr, + DSB_EDGE_CTRL_ATTR(0), + DSB_EDGE_CTRL_ATTR(1), + DSB_EDGE_CTRL_ATTR(2), + DSB_EDGE_CTRL_ATTR(3), + DSB_EDGE_CTRL_ATTR(4), + DSB_EDGE_CTRL_ATTR(5), + DSB_EDGE_CTRL_ATTR(6), + DSB_EDGE_CTRL_ATTR(7), + DSB_EDGE_CTRL_ATTR(8), + DSB_EDGE_CTRL_ATTR(9), + DSB_EDGE_CTRL_ATTR(10), + DSB_EDGE_CTRL_ATTR(11), + DSB_EDGE_CTRL_ATTR(12), + DSB_EDGE_CTRL_ATTR(13), + DSB_EDGE_CTRL_ATTR(14), + DSB_EDGE_CTRL_ATTR(15), + DSB_EDGE_CTRL_MASK_ATTR(0), + DSB_EDGE_CTRL_MASK_ATTR(1), + DSB_EDGE_CTRL_MASK_ATTR(2), + DSB_EDGE_CTRL_MASK_ATTR(3), + DSB_EDGE_CTRL_MASK_ATTR(4), + DSB_EDGE_CTRL_MASK_ATTR(5), + DSB_EDGE_CTRL_MASK_ATTR(6), + DSB_EDGE_CTRL_MASK_ATTR(7), + NULL, +}; + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr, @@ -374,14 +538,21 @@ static struct attribute *tpdm_dsb_attrs[] = { NULL, };

-static struct attribute_group tpdm_dsb_attr_grp = { +static struct attribute_group tpdm_dsb_attrs_grp = { .attrs = tpdm_dsb_attrs, .is_visible = tpdm_dsb_is_visible, };

+static struct attribute_group tpdm_dsb_edge_grp = { + .attrs = tpdm_dsb_edge_attrs, + .is_visible = tpdm_dsb_is_visible, + .name = "dsb_edge", +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, - &tpdm_dsb_attr_grp, + &tpdm_dsb_attrs_grp, + &tpdm_dsb_edge_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index f57c9fe..9736e00 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) +#define TPDM_DSB_EDCMR(n) (0x848 + (n * 4))

/* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -37,6 +39,16 @@ /* High performance mode */ #define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4))

+#define EDCRS_PER_WORD 16 +#define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD) +#define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2) +#define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r)) +#define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r) + +#define EDCMRS_PER_WORD 32 +#define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD) +#define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD) + /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00) @@ -63,14 +75,44 @@ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1)

+#define TPDM_DSB_MAX_LINES 256 +/* MAX number of EDCR registers */ +#define TPDM_DSB_MAX_EDCR 16 +/* MAX number of EDCMR registers */ +#define TPDM_DSB_MAX_EDCMR 8 + +#define tpdm_simple_dataset_ro(name, mem, idx, max) \ + (&((struct tpdm_dataset_attribute[]) { \ + { \ + __ATTR(name, 0444, tpdm_simple_dataset_show, NULL), \ + mem, \ + idx, \ + max, \ + } \ + })[0].attr.attr) + +#define DSB_EDGE_CTRL_ATTR(nr) \ + tpdm_simple_dataset_ro(edcr##nr, \ + DSB_EDGE_CTRL, nr, TPDM_DSB_MAX_EDCR) + +#define DSB_EDGE_CTRL_MASK_ATTR(nr) \ + tpdm_simple_dataset_ro(edcmr##nr, \ + DSB_EDGE_CTRL_MASK, nr, TPDM_DSB_MAX_EDCMR) + /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode + * @edge_ctrl_idx Index number of the edge control + * @edge_ctrl: Save value for edge control + * @edge_ctrl_mask: Save value for edge control mask * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ struct dsb_dataset { u32 mode; + u32 edge_ctrl_idx; + u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; + u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; bool trig_ts; bool trig_type; }; @@ -96,4 +138,25 @@ struct tpdm_drvdata { struct dsb_dataset *dsb; };

+/* Enumerate members of various datasets */ +enum dataset_mem { + DSB_EDGE_CTRL, + DSB_EDGE_CTRL_MASK, +}; + +/** + * struct tpdm_dataset_attribute - Record the member variables and + * index number of datasets that need to be operated by sysfs file + * @attr: The device attribute + * @mem: The member in the dataset data structure + * @idx: The index number of the array data + * @max: The maximal number of the array data + */ +struct tpdm_dataset_attribute { + struct device_attribute attr; + enum dataset_mem mem; + u32 idx; + u32 max; +}; + #endif /* _CORESIGHT_CORESIGHT_TPDM_H */

Add nodes to configure the timestamp request based on input pattern match. Each TPDM that support DSB subunit has maximum of n(n<7) TPR registers to configure value for timestamp request based on input pattern match. Eight 32 bit registers providing DSB interface timestamp request pattern match comparison. And each TPDM that support DSB subunit has maximum of m(m<7) TPMR registers to configure pattern mask for timestamp request. Eight 32 bit registers providing DSB interface timestamp request pattern match mask generation. Add nodes to enable/disable pattern timestamp and set pattern timestamp type.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 40 ++++++- drivers/hwtracing/coresight/coresight-tpdm.c | 133 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 24 ++++ 3 files changed, 191 insertions(+), 6 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index f5cd302..46a5535 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -123,4 +123,42 @@ KernelVersion 6.5 Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com Description: (RW) Set/Get the mask of the trigger pattern for the DSB - subunit TPDM. \ No newline at end of file + subunit TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the value of the pattern for the DSB subunit TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt_ts +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (Write) Set the pattern timestamp of DSB tpdm. Read + the pattern timestamp of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Disable DSB pattern timestamp. + 1 : Enable DSB pattern timestamp. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt_type +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (Write) Set the pattern type of DSB tpdm. Read + the pattern type of DSB tpdm. + + Accepts only one of the 2 values - 0 or 1. + 0 : Set the DSB pattern type to value. + 1 : Set the DSB pattern type to toggle. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 6521019..9b0e060 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -45,6 +45,12 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, case DSB_TRIG_PATT_MASK: return sysfs_emit(buf, "0x%x\n", drvdata->dsb->trig_patt_mask[tpdm_attr->idx]); + case DSB_PATT: + return sysfs_emit(buf, "0x%x\n", + drvdata->dsb->patt_val[tpdm_attr->idx]); + case DSB_PATT_MASK: + return sysfs_emit(buf, "0x%x\n", + drvdata->dsb->patt_mask[tpdm_attr->idx]); default: return -EINVAL; } @@ -72,6 +78,12 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, case DSB_TRIG_PATT_MASK: drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val; break; + case DSB_PATT: + drvdata->dsb->patt_val[tpdm_attr->idx] = val; + break; + case DSB_PATT_MASK: + drvdata->dsb->patt_mask[tpdm_attr->idx] = val; + break; default: spin_unlock(&drvdata->spinlock); return -EINVAL; @@ -129,6 +141,27 @@ static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val) *val &= ~TPDM_DSB_CR_MODE; }

+static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) +{ + /* Set pattern timestamp type and enablement */ + if (drvdata->dsb->patt_ts) { + *val |= TPDM_DSB_TIER_PATT_TSENAB; + if (drvdata->dsb->patt_type) + *val |= TPDM_DSB_TIER_PATT_TYPE; + else + *val &= ~TPDM_DSB_TIER_PATT_TYPE; + } else { + *val &= ~TPDM_DSB_TIER_PATT_TSENAB; + } + + /* Set trigger timestamp */ + if (drvdata->dsb->trig_ts) + *val |= TPDM_DSB_TIER_XTRIG_TSENAB; + else + *val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -140,17 +173,17 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], drvdata->base + TPDM_DSB_EDCMR(i)); for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { + writel_relaxed(drvdata->dsb->patt_val[i], + drvdata->base + TPDM_DSB_TPR(i)); + writel_relaxed(drvdata->dsb->patt_mask[i], + drvdata->base + TPDM_DSB_TPMR(i)); writel_relaxed(drvdata->dsb->trig_patt[i], drvdata->base + TPDM_DSB_XPR(i)); writel_relaxed(drvdata->dsb->trig_patt_mask[i], drvdata->base + TPDM_DSB_XPMR(i)); } val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); - /* Set trigger timestamp */ - if (drvdata->dsb->trig_ts) - val |= TPDM_DSB_TIER_XTRIG_TSENAB; - else - val &= ~TPDM_DSB_TIER_XTRIG_TSENAB; + set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);

val = readl_relaxed(drvdata->base + TPDM_DSB_CR); @@ -471,6 +504,67 @@ static ssize_t ctrl_mask_store(struct device *dev, } static DEVICE_ATTR_WO(ctrl_mask);

+static ssize_t dsb_patt_ts_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_ts); +} + +/* + * value 1: Enable/Disable DSB pattern timestamp + */ +static ssize_t dsb_patt_ts_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_ts = !!val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_ts); + +static ssize_t dsb_patt_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->dsb->patt_type); +} + +/* + * value 1: Set DSB pattern type + */ +static ssize_t dsb_patt_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->dsb->patt_type = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(dsb_patt_type); + static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -593,8 +687,30 @@ static struct attribute *tpdm_dsb_trig_patt_attrs[] = { NULL, };

+static struct attribute *tpdm_dsb_patt_attrs[] = { + DSB_PATT_ATTR(0), + DSB_PATT_ATTR(1), + DSB_PATT_ATTR(2), + DSB_PATT_ATTR(3), + DSB_PATT_ATTR(4), + DSB_PATT_ATTR(5), + DSB_PATT_ATTR(6), + DSB_PATT_ATTR(7), + DSB_PATT_MASK_ATTR(0), + DSB_PATT_MASK_ATTR(1), + DSB_PATT_MASK_ATTR(2), + DSB_PATT_MASK_ATTR(3), + DSB_PATT_MASK_ATTR(4), + DSB_PATT_MASK_ATTR(5), + DSB_PATT_MASK_ATTR(6), + DSB_PATT_MASK_ATTR(7), + NULL, +}; + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, + &dev_attr_dsb_patt_ts.attr, + &dev_attr_dsb_patt_type.attr, &dev_attr_dsb_trig_ts.attr, &dev_attr_dsb_trig_type.attr, NULL, @@ -617,11 +733,18 @@ static struct attribute_group tpdm_dsb_trig_patt_grp = { .name = "dsb_trig_patt", };

+static struct attribute_group tpdm_dsb_patt_grp = { + .attrs = tpdm_dsb_patt_attrs, + .is_visible = tpdm_dsb_is_visible, + .name = "dsb_patt", +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attrs_grp, &tpdm_dsb_edge_grp, &tpdm_dsb_trig_patt_grp, + &tpdm_dsb_patt_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 9e1b0a4..9173e80 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_TPR(n) (0x788 + (n * 4)) +#define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4)) #define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) @@ -28,8 +30,12 @@ /* Data bits for DSB test mode */ #define TPDM_DSB_CR_TEST_MODE GENMASK(10, 9)

+/* Enable bit for DSB subunit pattern timestamp */ +#define TPDM_DSB_TIER_PATT_TSENAB BIT(0) /* Enable bit for DSB subunit trigger timestamp */ #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) +/* Bit for DSB subunit pattern type */ +#define TPDM_DSB_TIER_PATT_TYPE BIT(2)

/* DSB programming modes */ /* DSB mode bits mask */ @@ -122,14 +128,26 @@ tpdm_simple_dataset_rw(xpmr##nr, \ DSB_TRIG_PATT_MASK, nr, TPDM_DSB_MAX_PATT)

+#define DSB_PATT_ATTR(nr) \ + tpdm_simple_dataset_rw(tpr##nr, \ + DSB_PATT, nr, TPDM_DSB_MAX_PATT) + +#define DSB_PATT_MASK_ATTR(nr) \ + tpdm_simple_dataset_rw(tpmr##nr, \ + DSB_PATT_MASK, nr, TPDM_DSB_MAX_PATT) + /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode * @edge_ctrl_idx Index number of the edge control * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask + * @patt_val: Save value for pattern + * @patt_mask: Save value for pattern mask * @trig_patt: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @patt_ts: Enable/Disable pattern timestamp + * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. * @trig_type: Enable/Disable trigger type. */ @@ -138,8 +156,12 @@ struct dsb_dataset { u32 edge_ctrl_idx; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; + u32 patt_val[TPDM_DSB_MAX_PATT]; + u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + bool patt_ts; + bool patt_type; bool trig_ts; bool trig_type; }; @@ -171,6 +193,8 @@ enum dataset_mem { DSB_EDGE_CTRL_MASK, DSB_TRIG_PATT, DSB_TRIG_PATT_MASK, + DSB_PATT, + DSB_PATT_MASK, };

/**

Add the nodes for DSB subunit MSR(mux select register) support. The TPDM MSR (mux select register) interface is an optional interface and associated bank of registers per TPDM subunit. The intent of mux select registers is to control muxing structures driving the TPDM’s’ various subunit interfaces.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 8 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 79 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ 3 files changed, 99 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 46a5535..9b7e172 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -162,3 +162,11 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB pattern type to value. 1 : Set the DSB pattern type to toggle. + +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: + (RW) Set/Get the MSR(mux select register) for the DSB subunit + TPDM. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 9b0e060..367c5e2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -51,6 +51,9 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, case DSB_PATT_MASK: return sysfs_emit(buf, "0x%x\n", drvdata->dsb->patt_mask[tpdm_attr->idx]); + case DSB_MSR: + return sysfs_emit(buf, "0x%x\n", + drvdata->dsb->msr[tpdm_attr->idx]); default: return -EINVAL; } @@ -84,6 +87,9 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, case DSB_PATT_MASK: drvdata->dsb->patt_mask[tpdm_attr->idx] = val; break; + case DSB_MSR: + drvdata->dsb->msr[tpdm_attr->idx] = val; + break; default: spin_unlock(&drvdata->spinlock); return -EINVAL; @@ -110,6 +116,22 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, return 0; }

+static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata && tpdm_has_dsb_dataset(drvdata)) { + of_property_read_u32(drvdata->dev->of_node, + "qcom,dsb_msr_num", &drvdata->dsb->msr_num); + if (drvdata->dsb->msr_num != 0) + return attr->mode; + } + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) { @@ -162,6 +184,18 @@ static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val)

}

+static void set_dsb_msr(struct tpdm_drvdata *drvdata) +{ + int i; + + if (drvdata->dsb->msr_num == 0) + return; + + for (i = 0; i < drvdata->dsb->msr_num; i++) + writel_relaxed(drvdata->dsb->msr[i], + drvdata->base + TPDM_DSB_MSR(i)); +} + static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; @@ -186,6 +220,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);

+ set_dsb_msr(drvdata); + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); /* Set the mode of DSB dataset */ set_dsb_mode(drvdata, &val); @@ -707,6 +743,42 @@ static struct attribute *tpdm_dsb_patt_attrs[] = { NULL, };

+static struct attribute *tpdm_dsb_msr_attrs[] = { + DSB_MSR_ATTR(0), + DSB_MSR_ATTR(1), + DSB_MSR_ATTR(2), + DSB_MSR_ATTR(3), + DSB_MSR_ATTR(4), + DSB_MSR_ATTR(5), + DSB_MSR_ATTR(6), + DSB_MSR_ATTR(7), + DSB_MSR_ATTR(8), + DSB_MSR_ATTR(9), + DSB_MSR_ATTR(10), + DSB_MSR_ATTR(11), + DSB_MSR_ATTR(12), + DSB_MSR_ATTR(13), + DSB_MSR_ATTR(14), + DSB_MSR_ATTR(15), + DSB_MSR_ATTR(16), + DSB_MSR_ATTR(17), + DSB_MSR_ATTR(18), + DSB_MSR_ATTR(19), + DSB_MSR_ATTR(20), + DSB_MSR_ATTR(21), + DSB_MSR_ATTR(22), + DSB_MSR_ATTR(23), + DSB_MSR_ATTR(24), + DSB_MSR_ATTR(25), + DSB_MSR_ATTR(26), + DSB_MSR_ATTR(27), + DSB_MSR_ATTR(28), + DSB_MSR_ATTR(29), + DSB_MSR_ATTR(30), + DSB_MSR_ATTR(31), + NULL, +}; + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_patt_ts.attr, @@ -739,12 +811,19 @@ static struct attribute_group tpdm_dsb_patt_grp = { .name = "dsb_patt", };

+static struct attribute_group tpdm_dsb_msr_grp = { + .attrs = tpdm_dsb_msr_attrs, + .is_visible = tpdm_dsb_msr_is_visible, + .name = "dsb_msr", +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attrs_grp, &tpdm_dsb_edge_grp, &tpdm_dsb_trig_patt_grp, &tpdm_dsb_patt_grp, + &tpdm_dsb_msr_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 9173e80..270e946 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -18,6 +18,7 @@ #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) +#define TPDM_DSB_MSR(n) (0x980 + (n * 4))

/* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -90,6 +91,8 @@ #define TPDM_DSB_MAX_EDCMR 8 /* MAX number of DSB pattern */ #define TPDM_DSB_MAX_PATT 8 +/* MAX number of DSB MSR */ +#define TPDM_DSB_MAX_MSR 32

#define tpdm_simple_dataset_ro(name, mem, idx, max) \ (&((struct tpdm_dataset_attribute[]) { \ @@ -136,16 +139,22 @@ tpdm_simple_dataset_rw(tpmr##nr, \ DSB_PATT_MASK, nr, TPDM_DSB_MAX_PATT)

+#define DSB_MSR_ATTR(nr) \ + tpdm_simple_dataset_rw(msr##nr, \ + DSB_MSR, nr, TPDM_DSB_MAX_MSR) + /** * struct dsb_dataset - specifics associated to dsb dataset * @mode: DSB programming mode * @edge_ctrl_idx Index number of the edge control + * @msr_num Number of MSR supported by DSB TPDM * @edge_ctrl: Save value for edge control * @edge_ctrl_mask: Save value for edge control mask * @patt_val: Save value for pattern * @patt_mask: Save value for pattern mask * @trig_patt: Save value for trigger pattern * @trig_patt_mask: Save value for trigger pattern mask + * @msr Save value for MSR * @patt_ts: Enable/Disable pattern timestamp * @patt_type: Set pattern type * @trig_ts: Enable/Disable trigger timestamp. @@ -154,12 +163,14 @@ struct dsb_dataset { u32 mode; u32 edge_ctrl_idx; + u32 msr_num; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; u32 patt_val[TPDM_DSB_MAX_PATT]; u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; + u32 msr[TPDM_DSB_MAX_MSR]; bool patt_ts; bool patt_type; bool trig_ts; @@ -195,6 +206,7 @@ enum dataset_mem { DSB_TRIG_PATT_MASK, DSB_PATT, DSB_PATT_MASK, + DSB_MSR, };

/**

On 22/08/2023 06:26, Tao Zhang wrote:

TPDM device need a node to reset the configurations and status of it. This change provides a node to reset the configurations and disable the TPDM if it has been enabled.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 10 ++++++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 22 ++++++++++++++++++++++ 2 files changed, 32 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 4a58e64..2936226 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -11,3 +11,13 @@ Description: Accepts only one of the 2 values - 1 or 2. 1 : Generate 64 bits data 2 : Generate 32 bits data

+What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (Write) Reset the dataset of the tpdm.
  

• Accepts only one value -  1.
  

• 1 : Reset the dataset of the tpdm
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 951ad4d..d6e7c8c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -162,6 +162,27 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata) return 0; } +static ssize_t reset_dataset_store(struct device *dev,

• 			  struct device_attribute *attr,
  

• 			  const char *buf,
  

• 			  size_t size)
  

+{

• int ret = 0;
• unsigned long val;
• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ret = kstrtoul(buf, 0, &val);
• if (ret || val != 1)

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• tpdm_reset_datasets(drvdata);
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(reset_dataset);

• /*
  • value 1: 64 bits test data
  • value 2: 32 bits test data

@@ -202,6 +223,7 @@ static ssize_t integration_test_store(struct device *dev, static DEVICE_ATTR_WO(integration_test); static struct attribute *tpdm_attrs[] = {

• &dev_attr_reset_dataset.attr,

Should this be only visible when DSB data set is present ?

Suzuki

&dev_attr_integration_test.attr, NULL, };

On 22/08/2023 06:26, Tao Zhang wrote:

The nodes are needed to set or show the trigger timestamp and trigger type. This change is to add these nodes to achieve these function.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 22 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 95 ++++++++++++++++++++++ 2 files changed, 117 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 2936226..9e26e30 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,25 @@ Description: Accepts only one value - 1. 1 : Reset the dataset of the tpdm

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type +Date: March 2023 +KernelVersion 6.5

6.7

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the trigger type of the DSB for tpdm.
  

• Accepts only one of the 2 values -  0 or 1.
  

• 0 : Set the DSB trigger type to false
  

• 1 : Set the DSB trigger type to true
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts +Date: March 2023 +KernelVersion 6.5

Same here

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the trigger timestamp of the DSB for tpdm.
  

• Accepts only one of the 2 values -  0 or 1.
  

• 0 : Set the DSB trigger type to false
  

• 1 : Set the DSB trigger type to true
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d6e7c8c..8e11c9b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -25,6 +25,18 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) return (drvdata->datasets & TPDM_PIDR0_DS_DSB); } +static umode_t tpdm_dsb_is_visible(struct kobject *kobj,

• 			   struct attribute *attr, int n)
  

minor nit: please align.

static umode_t tpdm_dsb_is_visible(struct kobject *kobj, struct attribute *attr, int n)

I don't know if you have a different setting for tabs in your editor. Please refer to the coding style document.

+{

• struct device *dev = kobj_to_dev(kobj);
• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (drvdata && tpdm_has_dsb_dataset(drvdata))

• return attr->mode;
  

• return 0;

+}

• static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) {

@@ -232,8 +244,91 @@ static struct attribute_group tpdm_attr_grp = { .attrs = tpdm_attrs, }; +static ssize_t dsb_trig_type_show(struct device *dev,

•   struct device_attribute *attr, char *buf)
  

same here.

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	 (unsigned int)drvdata->dsb->trig_type);
  

+}

+/*

• • Trigger type (boolean):
• • false - Disable trigger type.
• • true - Enable trigger type.
• */

+static ssize_t dsb_trig_type_store(struct device *dev,

• 			  struct device_attribute *attr,
  

• 			  const char *buf,
  

• 			  size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• if (val)

• drvdata->dsb->trig_type = true;
  

• else

• drvdata->dsb->trig_type = false;
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(dsb_trig_type);

+static ssize_t dsb_trig_ts_show(struct device *dev,

• 			struct device_attribute *attr,
  

• 			char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	 (unsigned int)drvdata->dsb->trig_ts);
  

+}

+/*

• • Trigger timestamp (boolean):
• • false - Disable trigger timestamp.
• • true - Enable trigger timestamp.
• */

+static ssize_t dsb_trig_ts_store(struct device *dev,

• 		   struct device_attribute *attr,
  

• 		   const char *buf,
  

• 		   size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• if (val)

• drvdata->dsb->trig_ts = true;
  

• else

• drvdata->dsb->trig_ts = false;
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(dsb_trig_ts);

+static struct attribute *tpdm_dsb_attrs[] = {

• &dev_attr_dsb_trig_ts.attr,
• &dev_attr_dsb_trig_type.attr,
• NULL,

+};

+static struct attribute_group tpdm_dsb_attr_grp = {

• .attrs = tpdm_dsb_attrs,
• .is_visible = tpdm_dsb_is_visible,

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp,
• &tpdm_dsb_attr_grp, NULL, };

Rest looks fine to me

Suzuki

On 22/08/2023 06:26, Tao Zhang wrote:

Add the nodes to set value for DSB edge control and DSB edge control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control.

Add the nodes to configure DSB edge control and DSB edge control mask. Each DSB subunit TPDM maximum of 256 edge detections can be configured. The index and value sysfs files need to be paired and written to order. The index sysfs file is to set the index number of the edge detection which needs to be configured. And the value sysfs file is to set the control or mask for the edge detection. DSB edge detection control should be set as the following values. 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And DSB edge mask should be set as 0 or 1. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask.

Add the nodes to read a set of the edge control value and mask of the DSB in TPDM.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 51 ++++++ drivers/hwtracing/coresight/coresight-tpdm.c | 177 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 63 ++++++++ 3 files changed, 288 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e17d1b4..097fdc4 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -57,3 +57,54 @@ Description: Bit[3] : Set to 0 for low performance mode. Set to 1 for high performance mode. Bit[4:8] : Select byte lane for high performance mode.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx +Date: March 2023 +KernelVersion 6.5

s/6.5/6.7

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the index number of the edge detection for the DSB
  

• subunit TPDM. Since there are at most 256 edge detections, this
  

• value ranges from 0 to 255.
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val +Date: March 2023 +KernelVersion 6.5

same as above

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• Write a data to control the edge detection corresponding to
  

• the index number. Before writing data to this sysfs file,
  

• "ctrl_idx" should be written first to configure the index
  

• number of the edge detection which needs to be controlled.
  

• Accepts only one of the following values.
  

• 0 - Rising edge detection
  

• 1 - Falling edge detection
  

• 2 - Rising and falling edge detection (toggle detection)
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• Write a data to mask the edge detection corresponding to the index
  

• number. Before writing data to this sysfs file, "ctrl_idx" should
  

• be written first to configure the index number of the edge detection
  

• which needs to be masked.
  

• Accepts only one of the 2 values -  0 or 1.
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• Read a set of the edge control value of the DSB in TPDM.
  

Read edge control register n for edcr<n>.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• Read a set of the edge control mask of the DSB in TPDM.
  

\ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 2424eb7..ba61e6a 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -21,6 +21,29 @@ DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); +/* Read dataset array member with the index number */ +static ssize_t tpdm_simple_dataset_show(struct device *dev,

• 	   struct device_attribute *attr, char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct tpdm_dataset_attribute *tpdm_attr =

• container_of(attr, struct tpdm_dataset_attribute, attr);
  

• if (tpdm_attr->idx >= tpdm_attr->max)

minor nit: See my comment on max below. We could skip max.

• return -EINVAL;
  

• switch (tpdm_attr->mem) {
• case DSB_EDGE_CTRL:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCR) break;

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->dsb->edge_ctrl[tpdm_attr->idx]);
  

• case DSB_EDGE_CTRL_MASK:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCMR) break;

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]);
  

}

return -EINVAL;

• default:

• return -EINVAL;
  

• }

+}

• static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) { return (drvdata->datasets & TPDM_PIDR0_DS_DSB);

@@ -71,7 +94,14 @@ static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val) static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) {

• u32 val;

• u32 val, i;
• for (i = 0; i < TPDM_DSB_MAX_EDCR; i++)

• writel_relaxed(drvdata->dsb->edge_ctrl[i],
  

• 	   drvdata->base + TPDM_DSB_EDCR(i));
  

• for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++)

• writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
  

• 	   drvdata->base + TPDM_DSB_EDCMR(i));
  

val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ @@ -296,6 +326,109 @@ static ssize_t dsb_mode_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_mode); +static ssize_t ctrl_idx_show(struct device *dev,

• 		struct device_attribute *attr,
  

• 		char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	(unsigned int)drvdata->dsb->edge_ctrl_idx);
  

+}

+/*

• • The EDCR registers can include up to 16 32-bit registers, and each
• • one can be configured to control up to 16 edge detections(2 bits
• • control one edge detection). So a total 256 edge detections can be
• • configured. This function provides a way to set the index number of
• • the edge detection which needs to be configured.
• */

+static ssize_t ctrl_idx_store(struct device *dev,

• 		struct device_attribute *attr,
  

• 		const char *buf,
  

• 		size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_DSB_MAX_LINES))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->dsb->edge_ctrl_idx = val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(ctrl_idx);

+/*

• • This function is used to control the edge detection according
• • to the index number that has been set.
• • "edge_ctrl" should be one of the following values.
• • 0 - Rising edge detection
• • 1 - Falling edge detection
• • 2 - Rising and falling edge detection (toggle detection)
• */

+static ssize_t ctrl_val_store(struct device *dev,

• 		struct device_attribute *attr,
  

• 		const char *buf,
  

• 		size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val, edge_ctrl;
• int reg;
• if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• /*

• * There are 2 bit per DSB Edge Control line.
  

• * Thus we have 16 lines in a 32bit word.
  

• */
  

• reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
• val = drvdata->dsb->edge_ctrl[reg];
• val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx);
• val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx);
• drvdata->dsb->edge_ctrl[reg] = val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(ctrl_val);

+static ssize_t ctrl_mask_store(struct device *dev,

• 		  struct device_attribute *attr,
  

• 		  const char *buf,
  

• 		  size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• u32 set;
• int reg;
• if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• /*

• * There is 1 bit per DSB Edge Control Mark line.
  

• * Thus we have 32 lines in a 32bit word.
  

• */
  

• reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
• set = drvdata->dsb->edge_ctrl_mask[reg];
• if (val)

• set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
  

• else

• set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
  

• drvdata->dsb->edge_ctrl_mask[reg] = set;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(ctrl_mask);

• static ssize_t dsb_trig_type_show(struct device *dev, struct device_attribute *attr, char *buf) {

@@ -367,6 +500,37 @@ static ssize_t dsb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_trig_ts); +static struct attribute *tpdm_dsb_edge_attrs[] = {

• &dev_attr_ctrl_idx.attr,
• &dev_attr_ctrl_val.attr,
• &dev_attr_ctrl_mask.attr,
• DSB_EDGE_CTRL_ATTR(0),
• DSB_EDGE_CTRL_ATTR(1),
• DSB_EDGE_CTRL_ATTR(2),
• DSB_EDGE_CTRL_ATTR(3),
• DSB_EDGE_CTRL_ATTR(4),
• DSB_EDGE_CTRL_ATTR(5),
• DSB_EDGE_CTRL_ATTR(6),
• DSB_EDGE_CTRL_ATTR(7),
• DSB_EDGE_CTRL_ATTR(8),
• DSB_EDGE_CTRL_ATTR(9),
• DSB_EDGE_CTRL_ATTR(10),
• DSB_EDGE_CTRL_ATTR(11),
• DSB_EDGE_CTRL_ATTR(12),
• DSB_EDGE_CTRL_ATTR(13),
• DSB_EDGE_CTRL_ATTR(14),
• DSB_EDGE_CTRL_ATTR(15),
• DSB_EDGE_CTRL_MASK_ATTR(0),
• DSB_EDGE_CTRL_MASK_ATTR(1),
• DSB_EDGE_CTRL_MASK_ATTR(2),
• DSB_EDGE_CTRL_MASK_ATTR(3),
• DSB_EDGE_CTRL_MASK_ATTR(4),
• DSB_EDGE_CTRL_MASK_ATTR(5),
• DSB_EDGE_CTRL_MASK_ATTR(6),
• DSB_EDGE_CTRL_MASK_ATTR(7),
• NULL,

+};

• static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr,

@@ -374,14 +538,21 @@ static struct attribute *tpdm_dsb_attrs[] = { NULL, }; -static struct attribute_group tpdm_dsb_attr_grp = { +static struct attribute_group tpdm_dsb_attrs_grp = { .attrs = tpdm_dsb_attrs, .is_visible = tpdm_dsb_is_visible, }; +static struct attribute_group tpdm_dsb_edge_grp = {

• .attrs = tpdm_dsb_edge_attrs,
• .is_visible = tpdm_dsb_is_visible,
• .name = "dsb_edge",

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp,

• &tpdm_dsb_attr_grp,

• &tpdm_dsb_attrs_grp,
• &tpdm_dsb_edge_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index f57c9fe..9736e00 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) +#define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -37,6 +39,16 @@ /* High performance mode */ #define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4)) +#define EDCRS_PER_WORD 16 +#define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD) +#define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2) +#define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r)) +#define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r)

+#define EDCMRS_PER_WORD 32 +#define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD) +#define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD)

• /* TPDM integration test registers */ #define TPDM_ITATBCNTRL (0xEF0) #define TPDM_ITCNTRL (0xF00)

@@ -63,14 +75,44 @@ #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) +#define TPDM_DSB_MAX_LINES 256 +/* MAX number of EDCR registers */ +#define TPDM_DSB_MAX_EDCR 16 +/* MAX number of EDCMR registers */ +#define TPDM_DSB_MAX_EDCMR 8

+#define tpdm_simple_dataset_ro(name, mem, idx, max) \

Do we need max ? The mem itself is enough to help you choose the max ? See my comment above.

• (&((struct tpdm_dataset_attribute[]) { \

•   {								\
  

• __ATTR(name, 0444, tpdm_simple_dataset_show, NULL),	\
  

• mem,							\
  

• idx,							\
  

• max,							\
  

•   }								\
  

• })[0].attr.attr)

+#define DSB_EDGE_CTRL_ATTR(nr) \

• tpdm_simple_dataset_ro(edcr##nr,		\
  

• DSB_EDGE_CTRL, nr, TPDM_DSB_MAX_EDCR)
  

+#define DSB_EDGE_CTRL_MASK_ATTR(nr) \

• tpdm_simple_dataset_ro(edcmr##nr,		\
  

• DSB_EDGE_CTRL_MASK, nr, TPDM_DSB_MAX_EDCMR)
  

• /**
  • struct dsb_dataset - specifics associated to dsb dataset
  • @mode: DSB programming mode
• • @edge_ctrl_idx Index number of the edge control
• • @edge_ctrl: Save value for edge control
• • @edge_ctrl_mask: Save value for edge control mask
  • @trig_ts: Enable/Disable trigger timestamp.
  • @trig_type: Enable/Disable trigger type.
  */ struct dsb_dataset { u32 mode;
• u32 edge_ctrl_idx;
• u32 edge_ctrl[TPDM_DSB_MAX_EDCR] > + u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; bool trig_ts; bool trig_type; };

@@ -96,4 +138,25 @@ struct tpdm_drvdata { struct dsb_dataset *dsb; }; +/* Enumerate members of various datasets */ +enum dataset_mem {

• DSB_EDGE_CTRL,
• DSB_EDGE_CTRL_MASK,

+};

+/**

• • struct tpdm_dataset_attribute - Record the member variables and
• • index number of datasets that need to be operated by sysfs file
• • @attr: The device attribute
• • @mem: The member in the dataset data structure
• • @idx: The index number of the array data
• • @max: The maximal number of the array data

As mentioned above, you could remove this.

Suzuki

• */

+struct tpdm_dataset_attribute {

• struct device_attribute attr;
• enum dataset_mem mem;
• u32 idx;
• u32 max;

+};

• #endif /* _CORESIGHT_CORESIGHT_TPDM_H */

On 9/1/2023 10:07 PM, Suzuki K Poulose wrote:

On 22/08/2023 06:26, Tao Zhang wrote:

...

Add the nodes to set value for DSB edge control and DSB edge control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control.

Add the nodes to configure DSB edge control and DSB edge control mask. Each DSB subunit TPDM maximum of 256 edge detections can be configured. The index and value sysfs files need to be paired and written to order. The index sysfs file is to set the index number of the edge detection which needs to be configured. And the value sysfs file is to set the control or mask for the edge detection. DSB edge detection control should be set as the following values. 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And DSB edge mask should be set as 0 or 1. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask.

Add the nodes to read a set of the edge control value and mask of the DSB in TPDM.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm   |  51 ++++++   drivers/hwtracing/coresight/coresight-tpdm.c       | 177 ++++++++++++++++++++-   drivers/hwtracing/coresight/coresight-tpdm.h       |  63 ++++++++   3 files changed, 288 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e17d1b4..097fdc4 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -57,3 +57,54 @@ Description:           Bit[3] : Set to 0 for low performance mode.                    Set to 1 for high performance mode.           Bit[4:8] : Select byte lane for high performance mode.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx +Date:        March 2023 +KernelVersion    6.5

s/6.5/6.7

Sure, I will update this in the next patch series.

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the index number of the edge detection for the DSB +        subunit TPDM. Since there are at most 256 edge detections, this +        value ranges from 0 to 255.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val +Date:        March 2023 +KernelVersion    6.5

same as above

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Write a data to control the edge detection corresponding to +        the index number. Before writing data to this sysfs file, +        "ctrl_idx" should be written first to configure the index +        number of the edge detection which needs to be controlled.

+        Accepts only one of the following values. +        0 - Rising edge detection +        1 - Falling edge detection +        2 - Rising and falling edge detection (toggle detection)

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Write a data to mask the edge detection corresponding to the index +        number. Before writing data to this sysfs file, "ctrl_idx" should +        be written first to configure the index number of the edge detection +        which needs to be masked.

+        Accepts only one of the 2 values -  0 or 1.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Read a set of the edge control value of the DSB in TPDM.

Read edge control register n for edcr<n>.

In fact, we don't read the register directly through this sysfs file, but read the value

we set to be written to the registers. Do I still need to modify it here?

...

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Read a set of the edge control mask of the DSB in TPDM. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 2424eb7..ba61e6a 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -21,6 +21,29 @@     DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");   +/* Read dataset array member with the index number */ +static ssize_t tpdm_simple_dataset_show(struct device *dev, +               struct device_attribute *attr, char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    struct tpdm_dataset_attribute *tpdm_attr = +        container_of(attr, struct tpdm_dataset_attribute, attr);

+    if (tpdm_attr->idx >= tpdm_attr->max)

minor nit: See my comment on max below. We could skip max.

I will update this in the next patch series.

...

+        return -EINVAL;

+    switch (tpdm_attr->mem) { +    case DSB_EDGE_CTRL:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCR)             break;

...

+        return sysfs_emit(buf, "0x%x\n",

• drvdata->dsb->edge_ctrl[tpdm_attr->idx]);

+    case DSB_EDGE_CTRL_MASK:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCMR)             break;

...

+        return sysfs_emit(buf, "0x%x\n",

• drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]);

}

return -EINVAL;

Why do we need to return this error code here?

...

+    default: +        return -EINVAL; +    } +}

static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)   {       return (drvdata->datasets & TPDM_PIDR0_DS_DSB); @@ -71,7 +94,14 @@ static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val)     static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)   { -    u32 val; +    u32 val, i;

+    for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) +        writel_relaxed(drvdata->dsb->edge_ctrl[i], +               drvdata->base + TPDM_DSB_EDCR(i)); +    for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) +        writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], +               drvdata->base + TPDM_DSB_EDCMR(i));         val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);       /* Set trigger timestamp */ @@ -296,6 +326,109 @@ static ssize_t dsb_mode_store(struct device *dev,   }   static DEVICE_ATTR_RW(dsb_mode);   +static ssize_t ctrl_idx_show(struct device *dev, +                struct device_attribute *attr, +                char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +            (unsigned int)drvdata->dsb->edge_ctrl_idx); +}

+/*

• • The EDCR registers can include up to 16 32-bit registers, and each
• • one can be configured to control up to 16 edge detections(2 bits
• • control one edge detection). So a total 256 edge detections can be
• • configured. This function provides a way to set the index number of
• • the edge detection which needs to be configured.
• */

+static ssize_t ctrl_idx_store(struct device *dev, +                struct device_attribute *attr, +                const char *buf, +                size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_DSB_MAX_LINES)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    drvdata->dsb->edge_ctrl_idx = val; +    spin_unlock(&drvdata->spinlock);

+    return size; +} +static DEVICE_ATTR_RW(ctrl_idx);

+/*

• • This function is used to control the edge detection according
• • to the index number that has been set.
• • "edge_ctrl" should be one of the following values.
• • 0 - Rising edge detection
• • 1 - Falling edge detection
• • 2 - Rising and falling edge detection (toggle detection)
• */

+static ssize_t ctrl_val_store(struct device *dev, +                struct device_attribute *attr, +                const char *buf, +                size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val, edge_ctrl; +    int reg;

+    if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    /* +     * There are 2 bit per DSB Edge Control line. +     * Thus we have 16 lines in a 32bit word. +     */ +    reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); +    val = drvdata->dsb->edge_ctrl[reg]; +    val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx); +    val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx); +    drvdata->dsb->edge_ctrl[reg] = val; +    spin_unlock(&drvdata->spinlock);

+    return size; +} +static DEVICE_ATTR_WO(ctrl_val);

+static ssize_t ctrl_mask_store(struct device *dev, +                  struct device_attribute *attr, +                  const char *buf, +                  size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val; +    u32 set; +    int reg;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    /* +     * There is 1 bit per DSB Edge Control Mark line. +     * Thus we have 32 lines in a 32bit word. +     */ +    reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx); +    set = drvdata->dsb->edge_ctrl_mask[reg]; +    if (val) +        set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); +    else +        set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx)); +    drvdata->dsb->edge_ctrl_mask[reg] = set; +    spin_unlock(&drvdata->spinlock);

+    return size; +} +static DEVICE_ATTR_WO(ctrl_mask);

static ssize_t dsb_trig_type_show(struct device *dev,             struct device_attribute *attr, char *buf)   { @@ -367,6 +500,37 @@ static ssize_t dsb_trig_ts_store(struct device *dev,   }   static DEVICE_ATTR_RW(dsb_trig_ts);   +static struct attribute *tpdm_dsb_edge_attrs[] = { +    &dev_attr_ctrl_idx.attr, +    &dev_attr_ctrl_val.attr, +    &dev_attr_ctrl_mask.attr, +    DSB_EDGE_CTRL_ATTR(0), +    DSB_EDGE_CTRL_ATTR(1), +    DSB_EDGE_CTRL_ATTR(2), +    DSB_EDGE_CTRL_ATTR(3), +    DSB_EDGE_CTRL_ATTR(4), +    DSB_EDGE_CTRL_ATTR(5), +    DSB_EDGE_CTRL_ATTR(6), +    DSB_EDGE_CTRL_ATTR(7), +    DSB_EDGE_CTRL_ATTR(8), +    DSB_EDGE_CTRL_ATTR(9), +    DSB_EDGE_CTRL_ATTR(10), +    DSB_EDGE_CTRL_ATTR(11), +    DSB_EDGE_CTRL_ATTR(12), +    DSB_EDGE_CTRL_ATTR(13), +    DSB_EDGE_CTRL_ATTR(14), +    DSB_EDGE_CTRL_ATTR(15), +    DSB_EDGE_CTRL_MASK_ATTR(0), +    DSB_EDGE_CTRL_MASK_ATTR(1), +    DSB_EDGE_CTRL_MASK_ATTR(2), +    DSB_EDGE_CTRL_MASK_ATTR(3), +    DSB_EDGE_CTRL_MASK_ATTR(4), +    DSB_EDGE_CTRL_MASK_ATTR(5), +    DSB_EDGE_CTRL_MASK_ATTR(6), +    DSB_EDGE_CTRL_MASK_ATTR(7), +    NULL, +};

static struct attribute *tpdm_dsb_attrs[] = {       &dev_attr_dsb_mode.attr,       &dev_attr_dsb_trig_ts.attr, @@ -374,14 +538,21 @@ static struct attribute *tpdm_dsb_attrs[] = {       NULL,   };   -static struct attribute_group tpdm_dsb_attr_grp = { +static struct attribute_group tpdm_dsb_attrs_grp = {       .attrs = tpdm_dsb_attrs,       .is_visible = tpdm_dsb_is_visible,   };   +static struct attribute_group tpdm_dsb_edge_grp = { +    .attrs = tpdm_dsb_edge_attrs, +    .is_visible = tpdm_dsb_is_visible, +    .name = "dsb_edge", +};

static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_attr_grp, -    &tpdm_dsb_attr_grp, +    &tpdm_dsb_attrs_grp, +    &tpdm_dsb_edge_grp,       NULL,   };   diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index f57c9fe..9736e00 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@   /* DSB Subunit Registers */   #define TPDM_DSB_CR        (0x780)   #define TPDM_DSB_TIER        (0x784) +#define TPDM_DSB_EDCR(n)    (0x808 + (n * 4)) +#define TPDM_DSB_EDCMR(n)    (0x848 + (n * 4))     /* Enable bit for DSB subunit */   #define TPDM_DSB_CR_ENA        BIT(0) @@ -37,6 +39,16 @@   /* High performance mode */   #define TPDM_DSB_MODE_HPBYTESEL(val)    (val & GENMASK(8, 4))   +#define EDCRS_PER_WORD                16 +#define EDCR_TO_WORD_IDX(r)            ((r) / EDCRS_PER_WORD) +#define EDCR_TO_WORD_SHIFT(r)        ((r % EDCRS_PER_WORD) * 2) +#define EDCR_TO_WORD_VAL(val, r)    (val << EDCR_TO_WORD_SHIFT(r)) +#define EDCR_TO_WORD_MASK(r)        EDCR_TO_WORD_VAL(0x3, r)

+#define EDCMRS_PER_WORD                32 +#define EDCMR_TO_WORD_IDX(r)        ((r) / EDCMRS_PER_WORD) +#define EDCMR_TO_WORD_SHIFT(r)        ((r) % EDCMRS_PER_WORD)

/* TPDM integration test registers */   #define TPDM_ITATBCNTRL        (0xEF0)   #define TPDM_ITCNTRL        (0xF00) @@ -63,14 +75,44 @@   #define TPDM_PIDR0_DS_IMPDEF    BIT(0)   #define TPDM_PIDR0_DS_DSB    BIT(1)   +#define TPDM_DSB_MAX_LINES    256 +/* MAX number of EDCR registers */ +#define TPDM_DSB_MAX_EDCR    16 +/* MAX number of EDCMR registers */ +#define TPDM_DSB_MAX_EDCMR    8

+#define tpdm_simple_dataset_ro(name, mem, idx, max) \

Do we need max ? The mem itself is enough to help you choose the max ? See my comment above.

I will update this in the next patch series.

...

+    (&((struct tpdm_dataset_attribute[]) {            \ +       {                                \ +        __ATTR(name, 0444, tpdm_simple_dataset_show, NULL), \ +        mem,                            \ +        idx,                            \ +        max,                            \ +       }                                \ +    })[0].attr.attr)

+#define DSB_EDGE_CTRL_ATTR(nr)                    \ +        tpdm_simple_dataset_ro(edcr##nr,        \ +        DSB_EDGE_CTRL, nr, TPDM_DSB_MAX_EDCR)

+#define DSB_EDGE_CTRL_MASK_ATTR(nr)                \ +        tpdm_simple_dataset_ro(edcmr##nr,        \ +        DSB_EDGE_CTRL_MASK, nr, TPDM_DSB_MAX_EDCMR)

/**    * struct dsb_dataset - specifics associated to dsb dataset    * @mode:             DSB programming mode

• • @edge_ctrl_idx     Index number of the edge control
• • @edge_ctrl:        Save value for edge control
• • @edge_ctrl_mask:   Save value for edge control mask

* @trig_ts:          Enable/Disable trigger timestamp.    * @trig_type:        Enable/Disable trigger type.    */   struct dsb_dataset {       u32                mode; +    u32                edge_ctrl_idx; +    u32                edge_ctrl[TPDM_DSB_MAX_EDCR] > + u32                edge_ctrl_mask[TPDM_DSB_MAX_EDCMR];       bool            trig_ts;       bool            trig_type;   }; @@ -96,4 +138,25 @@ struct tpdm_drvdata {       struct dsb_dataset    *dsb;   };   +/* Enumerate members of various datasets */ +enum dataset_mem { +    DSB_EDGE_CTRL, +    DSB_EDGE_CTRL_MASK, +};

+/**

• • struct tpdm_dataset_attribute - Record the member variables and
• • index number of datasets that need to be operated by sysfs file
• • @attr:       The device attribute
• • @mem:        The member in the dataset data structure
• • @idx:        The index number of the array data
• • @max:        The maximal number of the array data

As mentioned above, you could remove this.

Sure, I will update this in the next patch series.

Best,

Tao

Suzuki

...

• */

+struct tpdm_dataset_attribute { +    struct device_attribute attr; +    enum dataset_mem mem; +    u32 idx; +    u32 max; +};

#endif  /* _CORESIGHT_CORESIGHT_TPDM_H */

On 22/08/2023 06:26, Tao Zhang wrote:

Add nodes to configure trigger pattern and trigger pattern mask. Each DSB subunit TPDM has maximum of n(n<7) XPR registers to configure trigger pattern match output. Eight 32 bit registers providing DSB interface trigger output pattern match comparison. And each DSB subunit TPDM has maximum of m(m<7) XPMR registers to configure trigger pattern mask match output. Eight 32 bit registers providing DSB interface trigger output pattern match mask.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 18 +++++- drivers/hwtracing/coresight/coresight-tpdm.c | 71 +++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 29 +++++++++ 3 files changed, 116 insertions(+), 2 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 097fdc4..f5cd302 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -107,4 +107,20 @@ Date: March 2023 KernelVersion 6.5 Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com Description:

• Read a set of the edge control mask of the DSB in TPDM.
  

\ No newline at end of file

• Read a set of the edge control mask of the DSB in TPDM.
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7] +Date: March 2023 +KernelVersion 6.5

Same as previous patches

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the value of the trigger pattern for the DSB
  

• subunit TPDM.
  

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7] +Date: March 2023 +KernelVersion 6.5

here too

+Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the mask of the trigger pattern for the DSB
  

• subunit TPDM.
  

\ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index ba61e6a..6521019 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -39,9 +39,46 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, case DSB_EDGE_CTRL_MASK: return sysfs_emit(buf, "0x%x\n", drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]);

• case DSB_TRIG_PATT:

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->dsb->trig_patt[tpdm_attr->idx]);
  

• case DSB_TRIG_PATT_MASK:

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->dsb->trig_patt_mask[tpdm_attr->idx]);
  

• default:

• return -EINVAL;
  

• }

+}

+/* Write dataset array member with the index number */ +static ssize_t tpdm_simple_dataset_store(struct device *dev,

• 			  struct device_attribute *attr,
  

• 			  const char *buf,
  

• 			  size_t size)
  

+{

• unsigned long val;

ssize_t ret = size;

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct tpdm_dataset_attribute *tpdm_attr =

• container_of(attr, struct tpdm_dataset_attribute, attr);
  

• if (kstrtoul(buf, 0, &val) || (tpdm_attr->idx >= tpdm_attr->max))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• switch (tpdm_attr->mem) {
• case DSB_TRIG_PATT:

• drvdata->dsb->trig_patt[tpdm_attr->idx] = val;
  

• break;
  

• case DSB_TRIG_PATT_MASK:

• drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val;
  

• break;
  

  default:

• spin_unlock(&drvdata->spinlock);
  

ret = -EINVAL;

Please avoid releasing the lock in two different places where possible. Instead use a variable like above.

return -EINVAL;

}

• spin_unlock(&drvdata->spinlock);
• return size;

return ret;

} static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) @@ -102,7 +139,12 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], drvdata->base + TPDM_DSB_EDCMR(i));

• for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {

• writel_relaxed(drvdata->dsb->trig_patt[i],
  

• 	    drvdata->base + TPDM_DSB_XPR(i));
  

• writel_relaxed(drvdata->dsb->trig_patt_mask[i],
  

• 	    drvdata->base + TPDM_DSB_XPMR(i));
  

• } val = readl_relaxed(drvdata->base + TPDM_DSB_TIER); /* Set trigger timestamp */ if (drvdata->dsb->trig_ts)

@@ -531,6 +573,26 @@ static struct attribute *tpdm_dsb_edge_attrs[] = { NULL, }; +static struct attribute *tpdm_dsb_trig_patt_attrs[] = {

• DSB_TRIG_PATT_ATTR(0),
• DSB_TRIG_PATT_ATTR(1),
• DSB_TRIG_PATT_ATTR(2),
• DSB_TRIG_PATT_ATTR(3),
• DSB_TRIG_PATT_ATTR(4),
• DSB_TRIG_PATT_ATTR(5),
• DSB_TRIG_PATT_ATTR(6),
• DSB_TRIG_PATT_ATTR(7),
• DSB_TRIG_PATT_MASK_ATTR(0),
• DSB_TRIG_PATT_MASK_ATTR(1),
• DSB_TRIG_PATT_MASK_ATTR(2),
• DSB_TRIG_PATT_MASK_ATTR(3),
• DSB_TRIG_PATT_MASK_ATTR(4),
• DSB_TRIG_PATT_MASK_ATTR(5),
• DSB_TRIG_PATT_MASK_ATTR(6),
• DSB_TRIG_PATT_MASK_ATTR(7),
• NULL,

+};

• static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr,

@@ -549,10 +611,17 @@ static struct attribute_group tpdm_dsb_edge_grp = { .name = "dsb_edge", }; +static struct attribute_group tpdm_dsb_trig_patt_grp = {

• .attrs = tpdm_dsb_trig_patt_attrs,
• .is_visible = tpdm_dsb_is_visible,
• .name = "dsb_trig_patt",

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attrs_grp, &tpdm_dsb_edge_grp,
• &tpdm_dsb_trig_patt_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 9736e00..9e1b0a4 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,8 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) +#define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) +#define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) @@ -80,6 +82,8 @@ #define TPDM_DSB_MAX_EDCR 16 /* MAX number of EDCMR registers */ #define TPDM_DSB_MAX_EDCMR 8 +/* MAX number of DSB pattern */ +#define TPDM_DSB_MAX_PATT 8 #define tpdm_simple_dataset_ro(name, mem, idx, max) \ (&((struct tpdm_dataset_attribute[]) { \ @@ -91,6 +95,17 @@ } \ })[0].attr.attr) +#define tpdm_simple_dataset_rw(name, mem, idx, max) \

• (&((struct tpdm_dataset_attribute[]) { \

•   {								\
  

• __ATTR(name, 0644, tpdm_simple_dataset_show,		\
  

• tpdm_simple_dataset_store),		\
  

• mem,							\ > +		idx,							\
  

• max								\
  

Same as previous, you could get rid of max

•   }								\
  

• })[0].attr.attr)
• #define DSB_EDGE_CTRL_ATTR(nr) \ tpdm_simple_dataset_ro(edcr##nr, \ DSB_EDGE_CTRL, nr, TPDM_DSB_MAX_EDCR)

@@ -99,12 +114,22 @@ tpdm_simple_dataset_ro(edcmr##nr, \ DSB_EDGE_CTRL_MASK, nr, TPDM_DSB_MAX_EDCMR) +#define DSB_TRIG_PATT_ATTR(nr) \

• tpdm_simple_dataset_rw(xpr##nr,			\
  

• DSB_TRIG_PATT, nr, TPDM_DSB_MAX_PATT)
  

+#define DSB_TRIG_PATT_MASK_ATTR(nr) \

• tpdm_simple_dataset_rw(xpmr##nr,		\
  

• DSB_TRIG_PATT_MASK, nr, TPDM_DSB_MAX_PATT)
  

• /**
  • struct dsb_dataset - specifics associated to dsb dataset
  • @mode: DSB programming mode
  • @edge_ctrl_idx Index number of the edge control
  • @edge_ctrl: Save value for edge control
  • @edge_ctrl_mask: Save value for edge control mask
• • @trig_patt: Save value for trigger pattern
• • @trig_patt_mask: Save value for trigger pattern mask
  • @trig_ts: Enable/Disable trigger timestamp.
  • @trig_type: Enable/Disable trigger type.
  */

@@ -113,6 +138,8 @@ struct dsb_dataset { u32 edge_ctrl_idx; u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR];

• u32 trig_patt[TPDM_DSB_MAX_PATT];
• u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; bool trig_ts; bool trig_type; };

@@ -142,6 +169,8 @@ struct tpdm_drvdata { enum dataset_mem { DSB_EDGE_CTRL, DSB_EDGE_CTRL_MASK,

• DSB_TRIG_PATT,
• DSB_TRIG_PATT_MASK, };

Suzuki

On 22/08/2023 06:26, Tao Zhang wrote:

Add the nodes for DSB subunit MSR(mux select register) support. The TPDM MSR (mux select register) interface is an optional interface and associated bank of registers per TPDM subunit. The intent of mux select registers is to control muxing structures driving the TPDM’s’ various subunit interfaces.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 8 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 79 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++ 3 files changed, 99 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 46a5535..9b7e172 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -162,3 +162,11 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : Set the DSB pattern type to value. 1 : Set the DSB pattern type to toggle.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31] +Date: March 2023 +KernelVersion 6.5 +Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:

• (RW) Set/Get the MSR(mux select register) for the DSB subunit
  

• TPDM.
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 9b0e060..367c5e2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -51,6 +51,9 @@ static ssize_t tpdm_simple_dataset_show(struct device *dev, case DSB_PATT_MASK: return sysfs_emit(buf, "0x%x\n", drvdata->dsb->patt_mask[tpdm_attr->idx]);

• case DSB_MSR:

• return sysfs_emit(buf, "0x%x\n",
  

• 		drvdata->dsb->msr[tpdm_attr->idx]);
  

  default: return -EINVAL; }

@@ -84,6 +87,9 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, case DSB_PATT_MASK: drvdata->dsb->patt_mask[tpdm_attr->idx] = val; break;

• case DSB_MSR:

• drvdata->dsb->msr[tpdm_attr->idx] = val;
  

• break;
  

  default: spin_unlock(&drvdata->spinlock); return -EINVAL;

@@ -110,6 +116,22 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj,

• 			   struct attribute *attr, int n)
  

+{

• struct device *dev = kobj_to_dev(kobj);
• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (drvdata && tpdm_has_dsb_dataset(drvdata)) {

• of_property_read_u32(drvdata->dev->of_node,
  

• 	   "qcom,dsb_msr_num", &drvdata->dsb->msr_num);
  

Why don't we read this during probe and use that here ?

• if (drvdata->dsb->msr_num != 0)
  

Also, could we not check the index of the attribute and make sure it is available on this TPDM ?

attr->idx < drvdata->dsb->msr_num ??

• 	return attr->mode;
  

• }
• return 0;

+}

• static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) {

@@ -162,6 +184,18 @@ static void set_dsb_tier(struct tpdm_drvdata *drvdata, u32 *val) } +static void set_dsb_msr(struct tpdm_drvdata *drvdata) +{

• int i;
• if (drvdata->dsb->msr_num == 0)

• return;
  

You don;t need this special case, the loop handles it already

• for (i = 0; i < drvdata->dsb->msr_num; i++)

• writel_relaxed(drvdata->dsb->msr[i],
  

• 	   drvdata->base + TPDM_DSB_MSR(i));
  

+}

• static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i;

@@ -186,6 +220,8 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) set_dsb_tier(drvdata, &val); writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);

• set_dsb_msr(drvdata);
• val = readl_relaxed(drvdata->base + TPDM_DSB_CR); /* Set the mode of DSB dataset */ set_dsb_mode(drvdata, &val);

@@ -707,6 +743,42 @@ static struct attribute *tpdm_dsb_patt_attrs[] = { NULL, }; +static struct attribute *tpdm_dsb_msr_attrs[] = {

• DSB_MSR_ATTR(0),
• DSB_MSR_ATTR(1),
• DSB_MSR_ATTR(2),
• DSB_MSR_ATTR(3),
• DSB_MSR_ATTR(4),
• DSB_MSR_ATTR(5),
• DSB_MSR_ATTR(6),
• DSB_MSR_ATTR(7),
• DSB_MSR_ATTR(8),
• DSB_MSR_ATTR(9),
• DSB_MSR_ATTR(10),
• DSB_MSR_ATTR(11),
• DSB_MSR_ATTR(12),
• DSB_MSR_ATTR(13),
• DSB_MSR_ATTR(14),
• DSB_MSR_ATTR(15),
• DSB_MSR_ATTR(16),
• DSB_MSR_ATTR(17),
• DSB_MSR_ATTR(18),
• DSB_MSR_ATTR(19),
• DSB_MSR_ATTR(20),
• DSB_MSR_ATTR(21),
• DSB_MSR_ATTR(22),
• DSB_MSR_ATTR(23),
• DSB_MSR_ATTR(24),
• DSB_MSR_ATTR(25),
• DSB_MSR_ATTR(26),
• DSB_MSR_ATTR(27),
• DSB_MSR_ATTR(28),
• DSB_MSR_ATTR(29),
• DSB_MSR_ATTR(30),
• DSB_MSR_ATTR(31),
• NULL,

+};

• static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_patt_ts.attr,

@@ -739,12 +811,19 @@ static struct attribute_group tpdm_dsb_patt_grp = { .name = "dsb_patt", }; +static struct attribute_group tpdm_dsb_msr_grp = {

• .attrs = tpdm_dsb_msr_attrs,
• .is_visible = tpdm_dsb_msr_is_visible,
• .name = "dsb_msr",

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attrs_grp, &tpdm_dsb_edge_grp, &tpdm_dsb_trig_patt_grp, &tpdm_dsb_patt_grp,
• &tpdm_dsb_msr_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 9173e80..270e946 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -18,6 +18,7 @@ #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) +#define TPDM_DSB_MSR(n) (0x980 + (n * 4)) /* Enable bit for DSB subunit */ #define TPDM_DSB_CR_ENA BIT(0) @@ -90,6 +91,8 @@ #define TPDM_DSB_MAX_EDCMR 8 /* MAX number of DSB pattern */ #define TPDM_DSB_MAX_PATT 8 +/* MAX number of DSB MSR */ +#define TPDM_DSB_MAX_MSR 32 #define tpdm_simple_dataset_ro(name, mem, idx, max) \ (&((struct tpdm_dataset_attribute[]) { \ @@ -136,16 +139,22 @@ tpdm_simple_dataset_rw(tpmr##nr, \ DSB_PATT_MASK, nr, TPDM_DSB_MAX_PATT) +#define DSB_MSR_ATTR(nr) \

• tpdm_simple_dataset_rw(msr##nr,			\
  

• DSB_MSR, nr, TPDM_DSB_MAX_MSR)
  

• /**
  • struct dsb_dataset - specifics associated to dsb dataset
  • @mode: DSB programming mode
  • @edge_ctrl_idx Index number of the edge control
• • @msr_num Number of MSR supported by DSB TPDM
  • @edge_ctrl: Save value for edge control
  • @edge_ctrl_mask: Save value for edge control mask
  • @patt_val: Save value for pattern
  • @patt_mask: Save value for pattern mask
  • @trig_patt: Save value for trigger pattern
  • @trig_patt_mask: Save value for trigger pattern mask
• • @msr Save value for MSR
  • @patt_ts: Enable/Disable pattern timestamp
  • @patt_type: Set pattern type
  • @trig_ts: Enable/Disable trigger timestamp.

@@ -154,12 +163,14 @@ struct dsb_dataset { u32 mode; u32 edge_ctrl_idx;

• u32 msr_num;

Why should this be part of the dataset ? If I remember correctly, this data structure is zeroed on reset via sysfs ? Shouldn't that be part of the drvdata-> instead ? So that you read it once during probe and don't mess with it.

Suzuki

u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; u32 patt_val[TPDM_DSB_MAX_PATT]; u32 patt_mask[TPDM_DSB_MAX_PATT]; u32 trig_patt[TPDM_DSB_MAX_PATT]; u32 trig_patt_mask[TPDM_DSB_MAX_PATT];

• u32 msr[TPDM_DSB_MAX_MSR]; bool patt_ts; bool patt_type; bool trig_ts;

@@ -195,6 +206,7 @@ enum dataset_mem { DSB_TRIG_PATT_MASK, DSB_PATT, DSB_PATT_MASK,

• DSB_MSR, };

/**

On 9/5/2023 5:36 PM, Suzuki K Poulose wrote:

On 01/09/2023 17:01, Tao Zhang wrote:

...

On 9/1/2023 10:07 PM, Suzuki K Poulose wrote:

...

On 22/08/2023 06:26, Tao Zhang wrote:

...

Add the nodes to set value for DSB edge control and DSB edge control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. DSB edge detection control 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask. Eight 32 bit registers providing DSB interface edge detection mask control.

Add the nodes to configure DSB edge control and DSB edge control mask. Each DSB subunit TPDM maximum of 256 edge detections can be configured. The index and value sysfs files need to be paired and written to order. The index sysfs file is to set the index number of the edge detection which needs to be configured. And the value sysfs file is to set the control or mask for the edge detection. DSB edge detection control should be set as the following values. 00: Rising edge detection 01: Falling edge detection 10: Rising and falling edge detection (toggle detection) And DSB edge mask should be set as 0 or 1. Each DSB subunit TPDM has maximum of n(n<16) EDCR resgisters to configure edge control. And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to configure mask.

Add the nodes to read a set of the edge control value and mask of the DSB in TPDM.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm   |  51 ++++++   drivers/hwtracing/coresight/coresight-tpdm.c       | 177 ++++++++++++++++++++-   drivers/hwtracing/coresight/coresight-tpdm.h       |  63 ++++++++   3 files changed, 288 insertions(+), 3 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e17d1b4..097fdc4 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -57,3 +57,54 @@ Description:           Bit[3] : Set to 0 for low performance mode.                    Set to 1 for high performance mode.           Bit[4:8] : Select byte lane for high performance mode.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx +Date:        March 2023 +KernelVersion    6.5

s/6.5/6.7

Sure, I will update this in the next patch series.

...

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the index number of the edge detection for the DSB +        subunit TPDM. Since there are at most 256 edge detections, this +        value ranges from 0 to 255.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val +Date:        March 2023 +KernelVersion    6.5

same as above

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Write a data to control the edge detection corresponding to +        the index number. Before writing data to this sysfs file, +        "ctrl_idx" should be written first to configure the index +        number of the edge detection which needs to be controlled.

+        Accepts only one of the following values. +        0 - Rising edge detection +        1 - Falling edge detection +        2 - Rising and falling edge detection (toggle detection)

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Write a data to mask the edge detection corresponding to the index +        number. Before writing data to this sysfs file, "ctrl_idx" should +        be written first to configure the index number of the edge detection +        which needs to be masked.

+        Accepts only one of the 2 values -  0 or 1.

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15] +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Read a set of the edge control value of the DSB in TPDM.

Read edge control register n for edcr<n>.

In fact, we don't read the register directly through this sysfs file, but read the value

we set to be written to the registers. Do I still need to modify it here?

thats fine.

...

...

...

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7] +Date:        March 2023 +KernelVersion    6.5 +Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        Read a set of the edge control mask of the DSB in TPDM. \ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 2424eb7..ba61e6a 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -21,6 +21,29 @@     DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");   +/* Read dataset array member with the index number */ +static ssize_t tpdm_simple_dataset_show(struct device *dev, +               struct device_attribute *attr, char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    struct tpdm_dataset_attribute *tpdm_attr = +        container_of(attr, struct tpdm_dataset_attribute, attr);

+    if (tpdm_attr->idx >= tpdm_attr->max)

minor nit: See my comment on max below. We could skip max.

I will update this in the next patch series.

...

...

+        return -EINVAL;

+    switch (tpdm_attr->mem) { +    case DSB_EDGE_CTRL:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCR)             break;

...

+        return sysfs_emit(buf, "0x%x\n",

• drvdata->dsb->edge_ctrl[tpdm_attr->idx]);

+    case DSB_EDGE_CTRL_MASK:

if (tmp_attr->idx > TPDM_DSB_MAX_EDCMR)             break;

...

+        return sysfs_emit(buf, "0x%x\n",

• drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]);

}

return -EINVAL;

Why do we need to return this error code here?

...

The whole block would look like :

switch (tpdm->attr->mem) {     case DSB_EDGE_CTRL:         if (tmp_attr->idx > TPDM_DSB_MAX_EDCR)             break;         return sysfs_...     case DSB_EDGE_CTRL_MASK:         if (tmp_attr->idx > TPDM_DSB_MAX_EDCMR)             break;         return sysfs_...     }

return -EINVAL;

Sure, I will update this in the next patch series.

Best,

Tao

Suzuki

On 01/09/2023 15:41, Tao Zhang wrote:

On 9/1/2023 6:43 PM, Suzuki K Poulose wrote:

...

On 22/08/2023 06:26, Tao Zhang wrote:

...

The nodes are needed to set or show the trigger timestamp and trigger type. This change is to add these nodes to achieve these function.

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../ABI/testing/sysfs-bus-coresight-devices-tpdm   | 22 +++++   drivers/hwtracing/coresight/coresight-tpdm.c       | 95 ++++++++++++++++++++++   2 files changed, 117 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 2936226..9e26e30 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -21,3 +21,25 @@ Description:             Accepts only one value -  1.           1 : Reset the dataset of the tpdm

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type +Date:        March 2023 +KernelVersion    6.5

6.7

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the trigger type of the DSB for tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Set the DSB trigger type to false +        1 : Set the DSB trigger type to true

+What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts +Date:        March 2023 +KernelVersion    6.5

Same here

...

+Contact:    Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) quic_taozha@quicinc.com +Description: +        (RW) Set/Get the trigger timestamp of the DSB for tpdm.

+        Accepts only one of the 2 values -  0 or 1. +        0 : Set the DSB trigger type to false +        1 : Set the DSB trigger type to true diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d6e7c8c..8e11c9b 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -25,6 +25,18 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)       return (drvdata->datasets & TPDM_PIDR0_DS_DSB);   }   +static umode_t tpdm_dsb_is_visible(struct kobject *kobj, +                       struct attribute *attr, int n)

minor nit: please align.

static umode_t tpdm_dsb_is_visible(struct kobject *kobj,                    struct attribute *attr, int n)

I don't know if you have a different setting for tabs in your editor. Please refer to the coding style document.

Tab size is set to 4 in my editor.

Please read :

Documentation/process/coding-style.rst, section 1.

Suzuki

There are 5 tabs and 3 spaces at the beginning of this line.

I don't know if this is the same as what you see in this patch.

I see from the editor that the code meets the requirements of the coding style document.

If the gap in alignment is not resolved, such alignment problems may still occur.

Best,

Tao

...

...

+{ +    struct device *dev = kobj_to_dev(kobj); +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    if (drvdata && tpdm_has_dsb_dataset(drvdata)) +        return attr->mode;

+    return 0; +}

static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)   {       if (tpdm_has_dsb_dataset(drvdata)) { @@ -232,8 +244,91 @@ static struct attribute_group tpdm_attr_grp = {       .attrs = tpdm_attrs,   };   +static ssize_t dsb_trig_type_show(struct device *dev, +          struct device_attribute *attr, char *buf)

same here.

...

+{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +             (unsigned int)drvdata->dsb->trig_type); +}

+/*

• • Trigger type (boolean):
• • false - Disable trigger type.
• • true  - Enable trigger type.
• */

+static ssize_t dsb_trig_type_store(struct device *dev, +                      struct device_attribute *attr, +                      const char *buf, +                      size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->dsb->trig_type = true; +    else +        drvdata->dsb->trig_type = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(dsb_trig_type);

+static ssize_t dsb_trig_ts_show(struct device *dev, +                    struct device_attribute *attr, +                    char *buf) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);

+    return sysfs_emit(buf, "%u\n", +             (unsigned int)drvdata->dsb->trig_ts); +}

+/*

• • Trigger timestamp (boolean):
• • false - Disable trigger timestamp.
• • true  - Enable trigger timestamp.
• */

+static ssize_t dsb_trig_ts_store(struct device *dev, +                   struct device_attribute *attr, +                   const char *buf, +                   size_t size) +{ +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); +    unsigned long val;

+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL)) +        return -EINVAL;

+    spin_lock(&drvdata->spinlock); +    if (val) +        drvdata->dsb->trig_ts = true; +    else +        drvdata->dsb->trig_ts = false; +    spin_unlock(&drvdata->spinlock); +    return size; +} +static DEVICE_ATTR_RW(dsb_trig_ts);

+static struct attribute *tpdm_dsb_attrs[] = { +    &dev_attr_dsb_trig_ts.attr, +    &dev_attr_dsb_trig_type.attr, +    NULL, +};

+static struct attribute_group tpdm_dsb_attr_grp = { +    .attrs = tpdm_dsb_attrs, +    .is_visible = tpdm_dsb_is_visible, +};

static const struct attribute_group *tpdm_attr_grps[] = {       &tpdm_attr_grp, +    &tpdm_dsb_attr_grp,       NULL,   };

Rest looks fine to me

Suzuki