On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

The device mode is defined as local type. This type cannot promise SMP-safe access.

Change to atomic type and impose relax ordering, which ensures the SMP-safe synchronisation and the ordering between the mode setting and relevant operations.

Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()") Signed-off-by: Leo Yan leo.yan@arm.com

---

include/linux/coresight.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6de59ce8ef8ca45c29e2f09c1b979eb7686b685f..3e5e5acd0c7fcde7d312d440da4355faaf682c7b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -251,15 +251,11 @@ struct coresight_trace_id_map {

•         by @coresight_ops.
  

• @access: Device i/o access abstraction for this device.
• @dev: The device entity associated to this component.

• • @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is

• •         actually an 'enum cs_mode', but is stored in an atomic type.
    

• •         This is always accessed through local_read() and local_set(),
    

• •         but wherever it's done from within the Coresight device's lock,
    

• •         a non-atomic read would also work. This is the main point of
    

• •         synchronisation between code happening inside the sysfs mode's
    

• •         coresight_mutex and outside when running in Perf mode. A compare
    

• •         and exchange swap is done to atomically claim one mode or the
    

• •         other.
    

• • @mode: The device mode, i.e sysFS, Perf or disabled. This is actually

• •         an 'enum cs_mode' but stored in an atomic type. Access is always
    

• •         through atomic APIs, ensuring SMP-safe synchronisation between
    

• •         racing from sysFS and Perf mode. A compare-and-exchange
    

• •         operation is done to atomically claim one mode or the other.
    

  • @refcnt: keep track of what is in use. Only access this outside of the

  •         device's spinlock when the coresight_mutex held and mode ==
    

  •         CS_MODE_SYSFS. Otherwise it must be accessed from inside the
    

@@ -288,7 +284,7 @@ struct coresight_device { const struct coresight_ops *ops; struct csdev_access access; struct device dev;

•   local_t mode;
  

•   atomic_t mode;
    int refcnt;
    bool orphan;
    /* sink specific fields */
  

@@ -621,13 +617,14 @@ static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) static inline bool coresight_take_mode(struct coresight_device *csdev, enum cs_mode new_mode) {

•   return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) ==
  

•          CS_MODE_DISABLED;
  

•   int curr = CS_MODE_DISABLED;
  

•   return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode);
  

}

static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) {

•   return local_read(&csdev->mode);
  

•   return atomic_read_acquire(&csdev->mode);
  

}

static inline void coresight_set_mode(struct coresight_device *csdev, @@ -643,7 +640,7 @@ static inline void coresight_set_mode(struct coresight_device *csdev, WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && current_mode != new_mode, "Device already in use\n");

•   local_set(&csdev->mode, new_mode);
  

•   atomic_set_release(&csdev->mode, new_mode);
  

}

struct coresight_device *coresight_register(struct coresight_desc *desc);

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

On 02/10/2025 1:51 pm, Suzuki K Poulose wrote:

On 15/09/2025 11:33, Leo Yan wrote:

...

The device mode is defined as local type. This type cannot promise SMP-safe access.

Change to atomic type and impose relax ordering, which ensures the SMP-safe synchronisation and the ordering between the mode setting and relevant operations.

Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()")

Do we really have an issue here ? I thought we modify the mode under spinlock. Also the fixes commit looks odd. The mode was added to the coresight device only recently. Prior to that, it was part of drvdata and was serialized by the respective spinlocks. So I don't see how this was an issue.

Suzuki

Mode changes for sources are/were always done outside of any locking using the compare and swap, even before it was moved to coresight device. The reason was probably to do a quick early fail in the case of contention between sysfs and Perf.

I think mode changes for other device types may already be within in their spinlocks.

Unrelated to this change, I think the complexity isn't unnecessary and taking the spinlock could be the very first operation for any action. That would do away with the atomics. We don't need to optimise for any contention cases, because it never happens outside of artificial stress tests.

...

Signed-off-by: Leo Yan leo.yan@arm.com

include/linux/coresight.h | 25 +++++++++++--------------   1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6de59ce8ef8ca45c29e2f09c1b979eb7686b685f..3e5e5acd0c7fcde7d312d440da4355faaf682c7b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -251,15 +251,11 @@ struct coresight_trace_id_map {    *        by @coresight_ops.    * @access:    Device i/o access abstraction for this device.    * @dev:    The device entity associated to this component.

• • @mode:    This tracer's mode, i.e sysFS, Perf or disabled. This is
• *        actually an 'enum cs_mode', but is stored in an atomic type.
• *        This is always accessed through local_read() and local_set(),
• *        but wherever it's done from within the Coresight device's

lock,

• *        a non-atomic read would also work. This is the main point of
• *        synchronisation between code happening inside the sysfs mode's
• *        coresight_mutex and outside when running in Perf mode. A

compare

• *        and exchange swap is done to atomically claim one mode or the
• *        other.

• • @mode:    The device mode, i.e sysFS, Perf or disabled. This is

actually

• *        an 'enum cs_mode' but stored in an atomic type. Access is

always

• *        through atomic APIs, ensuring SMP-safe synchronisation between
• *        racing from sysFS and Perf mode. A compare-and-exchange
• *        operation is done to atomically claim one mode or the other.

* @refcnt:    keep track of what is in use. Only access this outside of the    *        device's spinlock when the coresight_mutex held and mode ==    *        CS_MODE_SYSFS. Otherwise it must be accessed from inside the @@ -288,7 +284,7 @@ struct coresight_device {       const struct coresight_ops *ops;       struct csdev_access access;       struct device dev; -    local_t    mode; +    atomic_t mode;       int refcnt;       bool orphan;       /* sink specific fields */ @@ -621,13 +617,14 @@ static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)   static inline bool coresight_take_mode(struct coresight_device *csdev,                          enum cs_mode new_mode)   { -    return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == -           CS_MODE_DISABLED; +    int curr = CS_MODE_DISABLED;

+    return atomic_try_cmpxchg_acquire(&csdev->mode, &curr, new_mode);   }   static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev)   { -    return local_read(&csdev->mode); +    return atomic_read_acquire(&csdev->mode);   }   static inline void coresight_set_mode(struct coresight_device *csdev, @@ -643,7 +640,7 @@ static inline void coresight_set_mode(struct coresight_device *csdev,       WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED &&            current_mode != new_mode, "Device already in use\n"); -    local_set(&csdev->mode, new_mode); +    atomic_set_release(&csdev->mode, new_mode);   }   struct coresight_device *coresight_register(struct coresight_desc *desc);

On 15/09/2025 11:33, Leo Yan wrote:

When enabling a tracer via SysFS interface, the device mode may be set by any CPU - not necessarily the target CPU. This can lead to race condition in SMP, and may result in incorrect mode values being read.

Consider the following example, where CPU0 attempts to enable the tracer on CPU1 (the target CPU):

CPU0 CPU1 etm4_enable() ` coresight_take_mode(SYSFS) ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() / / CPU idle: / etm4_cpu_save() / ` coresight_get_mode() Failed to enable h/w / ^^^ ` coresight_set_mode(DISABLED) <-' Read the intermediate SYSFS mode

In this case, CPU0 initiates the operation by taking the SYSFS mode to avoid conflicts with the Perf mode. It then sends an IPI to CPU1 to configure the tracer registers. If any error occurs during this process, CPU0 rolls back by setting the mode to DISABLED.

However, if CPU1 enters an idle state during this time, it might read the intermediate SYSFS mode. As a result, the CPU PM flow could wrongly save and restore tracer context that is actually disabled.

To resolve the issue, this commit moves the device mode setting logic on the target CPU. This ensures that the device mode is only modified by the target CPU, eliminating race condition between mode writes and reads across CPUs.

An additional change introduces the etm4_disable_hw_smp_call() function for SMP calls, which disables the tracer and explicitly set the mode to DISABLED during SysFS operations.

The flow is updated with this change:

CPU0 CPU1 etm4_enable() ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() ` coresight_take_mode(SYSFS) Failed, set back to DISABLED ` coresight_set_mode(DISABLED)

                                       CPU idle:
                                       etm4_cpu_save()
                                        ` coresight_get_mode()
                                           ^^^
                                           Read out the DISABLED mode

Fixes: c38a9ec2b2c1 ("coresight: etm4x: moving etm_drvdata::enable to atomic field") Reviewed-by: Yeoreum Yun yeoreum.yun@arm.com Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 48 +++++++++++++++------- 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 020f070bf17dc0557dfb3ae4f282b0a0c1778bd8..02ad41da7356547a67c53ff0a9146aec844f89da 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -592,10 +592,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) static void etm4_enable_hw_smp_call(void *info)

While at this, please could you rename this function to make it explicit that this is only for sysfs mode ?

e.g., etm4_enable_hw_sysfs_smp_call()

{ struct etm4_enable_arg *arg = info;

• struct coresight_device *csdev;

if (WARN_ON(!arg)) return;

• csdev = arg->drvdata->csdev;
• if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {

• /* Someone is already using the tracer */
  

• arg->rc = -EBUSY;
  

• return;
  

• }
• arg->rc = etm4_enable_hw(arg->drvdata);
• /* The tracer didn't start */
• if (arg->rc)

• coresight_set_mode(csdev, CS_MODE_DISABLED);
  

  }

/* @@ -811,6 +824,9 @@ static int etm4_enable_perf(struct coresight_device *csdev, int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

• if (!coresight_take_mode(csdev, CS_MODE_PERF))

• return -EBUSY;
  

Should be done after the CPU check below ? Otherwise you are undoing the fix on sysfs side.

if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { ret = -EINVAL; goto out; @@ -830,6 +846,9 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_enable_hw(drvdata); out:

• /* The tracer didn't start */
• if (ret)

• coresight_set_mode(csdev, CS_MODE_DISABLED);
  

  return ret; }

@@ -882,11 +901,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, { int ret;

• if (!coresight_take_mode(csdev, mode)) {

• /* Someone is already using the tracer */
  

• return -EBUSY;
  

• }
• switch (mode) { case CS_MODE_SYSFS: ret = etm4_enable_sysfs(csdev, path);

@@ -898,10 +912,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, ret = -EINVAL; }

• /* The tracer didn't start */
• if (ret)

• coresight_set_mode(csdev, CS_MODE_DISABLED);
  

• return ret; }

@@ -953,10 +963,9 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) isb(); } -static void etm4_disable_hw(void *info) +static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control;

• struct etmv4_drvdata *drvdata = info; struct etmv4_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access;

@@ -993,6 +1002,15 @@ static void etm4_disable_hw(void *info) "cpu: %d disable smp call done\n", drvdata->cpu); } +static void etm4_disable_hw_smp_call(void *info)

sysfs mode again.

Rest looks fine

Suzuki

+{

• struct etmv4_drvdata *drvdata = info;
• etm4_disable_hw(drvdata);
• coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);

+}

• static int etm4_disable_perf(struct coresight_device *csdev, struct perf_event *event) {

@@ -1022,6 +1040,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9));

• coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
• /*
  • perf will release trace ids when _free_aux() is
  • called at the end of the session.

@@ -1047,7 +1067,8 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) * Executing etm4_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */

• smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);

• smp_call_function_single(drvdata->cpu, etm4_disable_hw_smp_call,

• 		 drvdata, 1);
  

raw_spin_unlock(&drvdata->spinlock); @@ -1087,9 +1108,6 @@ static void etm4_disable(struct coresight_device *csdev, etm4_disable_perf(csdev, event); break; }

• if (mode)

• coresight_set_mode(csdev, CS_MODE_DISABLED);
  

  }

static int etm4_resume_perf(struct coresight_device *csdev)

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

When enabling a tracer via SysFS interface, the device mode may be set by any CPU - not necessarily the target CPU. This can lead to race condition in SMP, and may result in incorrect mode values being read.

Consider the following example, where CPU0 attempts to enable the tracer on CPU1 (the target CPU):

CPU0 CPU1 etm4_enable() ` coresight_take_mode(SYSFS) ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() / / CPU idle: / etm4_cpu_save() / ` coresight_get_mode() Failed to enable h/w / ^^^ ` coresight_set_mode(DISABLED) <-' Read the intermediate SYSFS mode

In this case, CPU0 initiates the operation by taking the SYSFS mode to avoid conflicts with the Perf mode. It then sends an IPI to CPU1 to configure the tracer registers. If any error occurs during this process, CPU0 rolls back by setting the mode to DISABLED.

However, if CPU1 enters an idle state during this time, it might read the intermediate SYSFS mode. As a result, the CPU PM flow could wrongly save and restore tracer context that is actually disabled.

To resolve the issue, this commit moves the device mode setting logic on the target CPU. This ensures that the device mode is only modified by the target CPU, eliminating race condition between mode writes and reads across CPUs.

An additional change introduces the etm4_disable_hw_smp_call() function for SMP calls, which disables the tracer and explicitly set the mode to DISABLED during SysFS operations.

The flow is updated with this change:

CPU0 CPU1 etm4_enable() ` etm4_enable_sysfs() ` smp_call_function_single() ----> etm4_enable_hw_smp_call() ` coresight_take_mode(SYSFS) Failed, set back to DISABLED ` coresight_set_mode(DISABLED)

                                      CPU idle:
                                      etm4_cpu_save()
                                       ` coresight_get_mode()
                                          ^^^
                                          Read out the DISABLED mode

Fixes: c38a9ec2b2c1 ("coresight: etm4x: moving etm_drvdata::enable to atomic field") Reviewed-by: Yeoreum Yun yeoreum.yun@arm.com Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 48 +++++++++++++++------- 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 020f070bf17dc0557dfb3ae4f282b0a0c1778bd8..02ad41da7356547a67c53ff0a9146aec844f89da 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -592,10 +592,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) static void etm4_enable_hw_smp_call(void *info) { struct etm4_enable_arg *arg = info;

•   struct coresight_device *csdev;
  
    if (WARN_ON(!arg))
            return;
  

•   csdev = arg->drvdata->csdev;
  

•   if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
  

•           /* Someone is already using the tracer */
  

•           arg->rc = -EBUSY;
  

•           return;
  

•   }
  

•   arg->rc = etm4_enable_hw(arg->drvdata);
  

•   /* The tracer didn't start */
  

•   if (arg->rc)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

}

/* @@ -811,6 +824,9 @@ static int etm4_enable_perf(struct coresight_device *csdev, int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   if (!coresight_take_mode(csdev, CS_MODE_PERF))
  

•           return -EBUSY;
  

•   if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
            ret = -EINVAL;
            goto out;
  

@@ -830,6 +846,9 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_enable_hw(drvdata);

out:

•   /* The tracer didn't start */
  

•   if (ret)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
    return ret;
  

}

@@ -882,11 +901,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, { int ret;

•   if (!coresight_take_mode(csdev, mode)) {
  

•           /* Someone is already using the tracer */
  

•           return -EBUSY;
  

•   }
  

•   switch (mode) {
    case CS_MODE_SYSFS:
            ret = etm4_enable_sysfs(csdev, path);
  

@@ -898,10 +912,6 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, ret = -EINVAL; }

•   /* The tracer didn't start */
  

•   if (ret)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

•   return ret;
  

}

@@ -953,10 +963,9 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) isb(); }

-static void etm4_disable_hw(void *info) +static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control;

•   struct etmv4_drvdata *drvdata = info;
    struct etmv4_config *config = &drvdata->config;
    struct coresight_device *csdev = drvdata->csdev;
    struct csdev_access *csa = &csdev->access;
  

@@ -993,6 +1002,15 @@ static void etm4_disable_hw(void *info) "cpu: %d disable smp call done\n", drvdata->cpu); }

+static void etm4_disable_hw_smp_call(void *info) +{

•   struct etmv4_drvdata *drvdata = info;
  

•   etm4_disable_hw(drvdata);
  

•   coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
  

+}

static int etm4_disable_perf(struct coresight_device *csdev, struct perf_event *event) { @@ -1022,6 +1040,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9));

•   coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
  

•   /*
     * perf will release trace ids when _free_aux() is
     * called at the end of the session.
  

@@ -1047,7 +1067,8 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) * Executing etm4_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */

•   smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
  

•   smp_call_function_single(drvdata->cpu, etm4_disable_hw_smp_call,
  

•                            drvdata, 1);
  
    raw_spin_unlock(&drvdata->spinlock);
  
  

@@ -1087,9 +1108,6 @@ static void etm4_disable(struct coresight_device *csdev, etm4_disable_perf(csdev, event); break; }

•   if (mode)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

}

static int etm4_resume_perf(struct coresight_device *csdev)

-- 2.34.1

Reviewed-by: mike Leach mike.leach@linaro.org

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

The ETMv3 driver shares the same issue as ETMv4 regarding race conditions when accessing the device mode.

This commit applies the same fix: ensuring that the device mode is modified only by the target CPU to eliminate race conditions across CPUs.

Fixes: 22fd532eaa0c ("coresight: etm3x: adding operation mode for etm_enable()") Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm3x-core.c | 54 +++++++++++++++------- 1 file changed, 37 insertions(+), 17 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 45630a1cd32fbd05ec8b2a6979f0174cacce365e..f759a47eaed9e804e30530a232370c9504912ac6 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -442,10 +442,23 @@ struct etm_enable_arg { static void etm_enable_hw_smp_call(void *info) { struct etm_enable_arg *arg = info;

•   struct coresight_device *csdev;
  
    if (WARN_ON(!arg))
            return;
  

•   csdev = arg->drvdata->csdev;
  

•   if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
  

•           /* Someone is already using the tracer */
  

•           arg->rc = -EBUSY;
  

•           return;
  

•   }
  

•   arg->rc = etm_enable_hw(arg->drvdata);
  

•   /* The tracer didn't start */
  

•   if (arg->rc)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

}

static int etm_cpu_id(struct coresight_device *csdev) @@ -464,17 +477,26 @@ static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event, struct coresight_path *path) {

•   int ret = 0;
    struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  
    if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
            return -EINVAL;
  
  

•   if (!coresight_take_mode(csdev, CS_MODE_PERF))
  

•           return -EBUSY;
  

•   /* Configure the tracer based on the session's specifics */
    etm_parse_event_config(drvdata, event);
    drvdata->traceid = path->trace_id;
  
    /* And enable it */
  

•   return etm_enable_hw(drvdata);
  

•   ret = etm_enable_hw(drvdata);
  

•   /* The tracer didn't start */
  

•   if (ret)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

•   return ret;
  

}

static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path) @@ -517,12 +539,6 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, enum cs_mode mode, struct coresight_path *path) { int ret;

•   struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  

•   if (!coresight_take_mode(csdev, mode)) {
  

•           /* Someone is already using the tracer */
  

•           return -EBUSY;
  

•   }
  
    switch (mode) {
    case CS_MODE_SYSFS:
  

@@ -535,17 +551,12 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event, ret = -EINVAL; }

•   /* The tracer didn't start */
  

•   if (ret)
  

•           coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
  

•   return ret;
  

}

-static void etm_disable_hw(void *info) +static void etm_disable_hw(struct etm_drvdata *drvdata) { int i;

•   struct etm_drvdata *drvdata = info;
    struct etm_config *config = &drvdata->config;
    struct coresight_device *csdev = drvdata->csdev;
  
  

@@ -567,6 +578,15 @@ static void etm_disable_hw(void *info) "cpu: %d disable smp call done\n", drvdata->cpu); }

+static void etm_disable_hw_smp_call(void *info) +{

•   struct etm_drvdata *drvdata = info;
  

•   etm_disable_hw(drvdata);
  

•   coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
  

+}

static void etm_disable_perf(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -588,6 +608,8 @@ static void etm_disable_perf(struct coresight_device *csdev)

    CS_LOCK(drvdata->csa.base);

•   coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
  

•   /*
     * perf will release trace ids when _free_aux()
     * is called at the end of the session
  

@@ -612,7 +634,8 @@ static void etm_disable_sysfs(struct coresight_device *csdev) * Executing etm_disable_hw on the cpu whose ETM is being disabled * ensures that register writes occur when cpu is powered. */

•   smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
  

•   smp_call_function_single(drvdata->cpu, etm_disable_hw_smp_call,
  

•                            drvdata, 1);
  
    spin_unlock(&drvdata->spinlock);
    cpus_read_unlock();
  

@@ -652,9 +675,6 @@ static void etm_disable(struct coresight_device *csdev, WARN_ON_ONCE(mode); return; }

•   if (mode)
  

•           coresight_set_mode(csdev, CS_MODE_DISABLED);
  

}

static const struct coresight_ops_source etm_source_ops = {

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

Since commit 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR"), the code has incorrectly been polling the PMSTABLE bit instead of the IDLE bit.

This commit corrects the typo.

Fixes: 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR") Reviewed-by: Yeoreum Yun yeoreum.yun@arm.com Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 02ad41da7356547a67c53ff0a9146aec844f89da..382ec1a1cdd035e76d451d0112afd3f029ecbdb6 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1926,7 +1926,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcpdcr = etm4x_read32(csa, TRCPDCR);

    /* wait for TRCSTATR.IDLE to go up */

•   if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
  

•   if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) {
            dev_err(etm_dev,
                    "timeout while waiting for Idle Trace Status\n");
            etm4_os_unlock(drvdata);
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

As recommended in section 4.3.7 "Synchronization of register updates" of ARM IHI0064H.b, a self-hosted trace analyzer should always executes an ISB instruction after programming the trace unit registers.

An ISB works as a context synchronization event; a DSB is not required. Removes the redundant barrier in the enabling flow.

The ISB was placed at the end of the enable and disable functions. However, this does not guarantee a context synchronization event in the calling code, which may speculatively execute across function boundaries.

ISB instructions are moved into callers to ensure that a context synchronization is imposed immediately after enabling or disabling trace unit.

Fixes: 40f682ae5086 ("coresight: etm4x: Extract the trace unit controlling") Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 38 +++++++++++++++------- 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 382ec1a1cdd035e76d451d0112afd3f029ecbdb6..31d4838b47ae4a3a96c6a06774707214943268fc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -460,13 +460,6 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) return -ETIME; }

•   /*
  

•    * As recommended by section 4.3.7 ("Synchronization when using the
  

•    * memory-mapped interface") of ARM IHI 0064D
  

•    */
  

•   dsb(sy);
  

•   isb();
  

•   return 0;
  

}

@@ -581,6 +574,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)

    if (!drvdata->paused)
            rc = etm4_enable_trace_unit(drvdata);

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

done: etm4_cs_lock(drvdata, csa);

@@ -956,11 +956,6 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for PM stable Trace Status\n");

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b.
  

•    */
  

•   isb();
  

}

static void etm4_disable_hw(struct etmv4_drvdata *drvdata) @@ -983,6 +978,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)

    etm4_disable_trace_unit(drvdata);

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

•   /* read the status of the single shot comparators */
    for (i = 0; i < drvdata->nr_ss_cmp; i++) {
            config->ss_status[i] =
  

@@ -1120,6 +1122,12 @@ static int etm4_resume_perf(struct coresight_device *csdev)

    etm4_cs_unlock(drvdata, csa);
    etm4_enable_trace_unit(drvdata);

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
    etm4_cs_lock(drvdata, csa);
  
    drvdata->paused = false;
  

@@ -1136,6 +1144,12 @@ static void etm4_pause_perf(struct coresight_device *csdev)

    etm4_cs_unlock(drvdata, csa);
    etm4_disable_trace_unit(drvdata);

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
    etm4_cs_lock(drvdata, csa);
  
    drvdata->paused = true;
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

According to the software usage PKLXF in Arm ARM (ARM DDI 0487 L.a), a Context synchronization event is required before enabling the trace unit. An ISB is added to meet this requirement.

Improved the barrier comments to provide more accurate information by specifying which section of the document the requirement comes from and clarifying its intended purpose.

Fixes: 1ab3bb9df5e3 ("coresight: etm4x: Add necessary synchronization for sysreg access") Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 37 +++++++++++++++++++--- 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 31d4838b47ae4a3a96c6a06774707214943268fc..999bceef4cd771e46aec891f4c814a95e0921c2f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -446,13 +446,37 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);

    etm4x_allow_trace(drvdata);

•   /*
  

•    * According to software usage PKLXF in Arm ARM (ARM DDI 0487 L.a),
  

•    * execute a Context synchronization event to guarantee the trace unit
  

•    * will observe the new values of the System registers.
  

•    */
  

•   if (!csa->io_mem)
  

•           isb();
  

•   /* Enable the trace unit */
    etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
  
  

•   /* Synchronize the register updates for sysreg access */
  

•   /*
  

•    * As recommended by section 4.3.7 ("Synchronization when using system
  

•    * instructions to progrom the trace unit") of ARM IHI 0064H.b, the
  

•    * self-hosted trace analyzer must perform a Context synchronization
  

•    * event between writing to the TRCPRGCTLR and reading the TRCSTATR.
  

•    */
    if (!csa->io_mem)
            isb();
  
  

•   /*
  

•    * For the memory-mapped interface, the registers are mapped as Device
  

•    * type (Device-nGnRE). As described in section 4.3.7 ("Synchronization
  

•    * of register updates") of ARM IHI0064H.b, read back the value of any
  

•    * register in the trace unit to ensure writes have completed.
  

•    *
  

•    * Therefore, polling on TRCSTATR ensures that the writing TRCPRGCTLR
  

•    * is complete.
  

•    */
  

•   /* wait for TRCSTATR.IDLE to go back down to '0' */
    if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0)) {
            dev_err(etm_dev,
  

@@ -933,11 +957,16 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata) */ etm4x_prohibit_trace(drvdata); /*

•    * Make sure everything completes before disabling, as recommended
  

•    * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
  

•    * SSTATUS") of ARM IHI 0064D
  

•    * Prevent being speculative at the point of disabling the trace unit,
  

•    * as recommended by section 7.3.77 ("TRCVICTLR, ViewInst Main Control
  

•    * Register, SSTATUS") of ARM IHI 0064D
     */
    dsb(sy);
  

•   /*
  

•    * According to software usage VKHHY in Arm ARM (ARM DDI 0487 L.a),
  

•    * execute a Context synchronization event to guarantee no new
  

•    * program-flow trace is generated.
  

•    */
    isb();
    /* Trace synchronization barrier, is a nop if not supported */
    tsb_csync();
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

If a CPU supports FEAT_TRF, as described in the section K5.5 "Context switching", Arm ARM (ARM DDI 0487 L.a), it defines a flow to prohibit program-flow trace, execute a TSB CSYNC instruction for flushing, followed by clearing TRCPRGCTLR.EN bit.

To restore the state, the reverse sequence is required.

This differs from the procedure described in the section 3.4.1 "The procedure when powering down the PE" of ARM IHI0064H.b, which involves the OS Lock to prevent external debugger accesses and implicitly disables trace.

To be compatible with different ETM versions, explicitly control trace unit using etm4_disable_trace_unit() and etm4_enable_trace_unit() during CPU idle to comply with FEAT_TRF.

As a result, the save states for TRFCR_ELx and trcprgctlr are redundant, remove them.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 28 ++++++++++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 3 --- 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 999bceef4cd771e46aec891f4c814a95e0921c2f..2d2ef58393db10d058b3e29c5b270dd2d62e1a49 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1884,9 +1884,18 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) goto out; }

•   if (!drvdata->paused)
  

•           etm4_disable_trace_unit(drvdata);
  

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

•   state = drvdata->save_state;
  
  

•   state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
    if (drvdata->nr_pe)
            state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
    state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
  

@@ -1996,9 +2005,6 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int ret = 0;

•   /* Save the TRFCR irrespective of whether the ETM is ON */
  

•   if (drvdata->trfcr)
  

•           drvdata->save_trfcr = read_trfcr();
    /*
     * Save and restore the ETM Trace registers only if
     * the ETM is active.
  

@@ -2020,7 +2026,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);

•   etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
    if (drvdata->nr_pe)
            etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
    etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
  

@@ -2105,13 +2110,22 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)

    /* Unlock the OS lock to re-enable trace and external debug access */
    etm4_os_unlock(drvdata);

•   if (!drvdata->paused)
  

•           etm4_enable_trace_unit(drvdata);
  

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

•   etm4_cs_lock(drvdata, csa);
  

}

static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) {

•   if (drvdata->trfcr)
  

•           write_trfcr(drvdata->save_trfcr);
    if (drvdata->state_needs_restore)
            __etm4_cpu_restore(drvdata);
  

} diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 13ec9ecef46f5b60a38c464e8ebde3ef72e7d50b..b8796b4271025f6aba79fe3cd6e4d17d0b56952d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -866,7 +866,6 @@ struct etmv4_config {

• struct etm4_save_state - state to be preserved when ETM is without power

*/ struct etmv4_save_state {

•   u32     trcprgctlr;
    u32     trcprocselr;
    u32     trcconfigr;
    u32     trcauxctlr;
  

@@ -980,7 +979,6 @@ struct etmv4_save_state {

•         at runtime, due to the additional setting of TRFCR_CX when
  

•         in EL2. Otherwise, 0.
  

• @config: structure holding configuration parameters.

• • @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
  • @save_state: State to be preserved across power loss
  • @state_needs_restore: True when there is context to restore after PM exit
  • @skip_power_up: Indicates if an implementation can skip powering up

@@ -1037,7 +1035,6 @@ struct etmv4_drvdata { bool lpoverride; u64 trfcr; struct etmv4_config config;

•   u64                             save_trfcr;
    struct etmv4_save_state         *save_state;
    bool                            state_needs_restore;
    bool                            skip_power_up;
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

When the restore flow is invoked, it means no error occurred during the save phase. Otherwise, if any errors happened while saving the context, the function would return an error and abort the suspend sequence.

Therefore, the state_needs_restore flag is unnecessary. The save and restore functions are changed to check two conditions:

1. The global flag pm_save_enable is SELF_HOSTED mode;
2. The device is in active mode (non DISABLED).

Reviewed-by: Yeoreum Yun yeoreum.yun@arm.com Signed-off-by: Leo Yan leo.yan@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 ++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 2 -- 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2d2ef58393db10d058b3e29c5b270dd2d62e1a49..fbcd0fcd1992cd600d2eb8c95ae9a5adf0c287da 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1986,8 +1986,6 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) goto out; }

•   drvdata->state_needs_restore = true;
  

•   /*
     * Power can be removed from the trace unit now. We do this to
     * potentially save power on systems that respect the TRCPDCR_PU
  

@@ -2005,11 +2003,14 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int ret = 0;

•   if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED)
  

•           return 0;
  

•   /*
     * Save and restore the ETM Trace registers only if
     * the ETM is active.
     */
  

•   if (coresight_get_mode(drvdata->csdev) && drvdata->save_state)
  

•   if (coresight_get_mode(drvdata->csdev))
            ret = __etm4_cpu_save(drvdata);
    return ret;
  

} @@ -2099,8 +2100,6 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) if (!drvdata->skip_power_up) etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);

•   drvdata->state_needs_restore = false;
  

•   /*
     * As recommended by section 4.3.7 ("Synchronization when using the
     * memory-mapped interface") of ARM IHI 0064D
  

@@ -2126,7 +2125,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)

static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) {

•   if (drvdata->state_needs_restore)
  

•   if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED)
  

•           return;
  

•   if (coresight_get_mode(drvdata->csdev))
            __etm4_cpu_restore(drvdata);
  

}

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b8796b4271025f6aba79fe3cd6e4d17d0b56952d..012c52fd19338133129752d35523dc102df24604 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -980,7 +980,6 @@ struct etmv4_save_state {

•         in EL2. Otherwise, 0.
  

• @config: structure holding configuration parameters.
• @save_state: State to be preserved across power loss

• • @state_needs_restore: True when there is context to restore after PM exit
  • @skip_power_up: Indicates if an implementation can skip powering up

  •            the trace unit.
    

  • @paused: Indicates if the trace unit is paused.

@@ -1036,7 +1035,6 @@ struct etmv4_drvdata { u64 trfcr; struct etmv4_config config; struct etmv4_save_state *save_state;

•   bool                            state_needs_restore;
    bool                            skip_power_up;
    bool                            paused;
    DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

On Mon, 15 Sept 2025 at 11:33, Leo Yan leo.yan@arm.com wrote:

Add a new argument restart_ss to etm4_enable_hw(). When passed as true, it resets the TRCSSCSRn.STATUS bit to 0 to re-enable single-shot control.

No functional change. This is a preparation for a subsequent change.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-etm4x-core.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index fbcd0fcd1992cd600d2eb8c95ae9a5adf0c287da..f61c9924ad0496be2e41c84172c2bbe348df7b60 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -487,7 +487,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata) return 0; }

-static int etm4_enable_hw(struct etmv4_drvdata *drvdata) +static int etm4_enable_hw(struct etmv4_drvdata *drvdata, bool restart_ss) { int i, rc; struct etmv4_config *config = &drvdata->config; @@ -562,9 +562,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));

    for (i = 0; i < drvdata->nr_ss_cmp; i++) {

•           /* always clear status bit on restart if using single-shot */
  

•           if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
  

•                   config->ss_status[i] &= ~TRCSSCSRn_STATUS;
  

•           if (restart_ss) {
  

•                   /* always clear status bit on restart if using single-shot */
  

•                   if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
  

•                           config->ss_status[i] &= ~TRCSSCSRn_STATUS;
  

•           }
            etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
            etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
            if (etm4x_sspcicrn_present(drvdata, i))
  

@@ -628,7 +630,7 @@ static void etm4_enable_hw_smp_call(void *info) return; }

•   arg->rc = etm4_enable_hw(arg->drvdata);
  

•   arg->rc = etm4_enable_hw(arg->drvdata, true);
  
    /* The tracer didn't start */
    if (arg->rc)
  

@@ -867,7 +869,7 @@ static int etm4_enable_perf(struct coresight_device *csdev, drvdata->paused = !!READ_ONCE(event->hw.aux_paused);

    /* And enable it */

•   ret = etm4_enable_hw(drvdata);
  

•   ret = etm4_enable_hw(drvdata, true);
  
  

out: /* The tracer didn't start */ @@ -1833,7 +1835,7 @@ static int etm4_starting_cpu(unsigned int cpu) etm4_os_unlock(etmdrvdata[cpu]);

    if (coresight_get_mode(etmdrvdata[cpu]->csdev))

•           etm4_enable_hw(etmdrvdata[cpu]);
  

•           etm4_enable_hw(etmdrvdata[cpu], true);
    raw_spin_unlock(&etmdrvdata[cpu]->spinlock);
    return 0;
  

}

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

Hi Leo,

Overall I like the idea, but there are some minor issues that need addressing.

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

The etm4_enable_trace_unit() function is almost identical to the restore flow, with a few differences listed below:

1. TRCQCTLR register

   The TRCQCTLR register is saved and restored during CPU idle, but it is never touched in the normal flow. Given the Q element is not enabled (TRCCONFIGR.QE bits), it is acceptable to omit saving and restoring this register during idle.

2. TRCSSCSRn.STATUS bit

   The restore flow does not explicitly clear the TRCSSCSRn.STATUS bit but instead directly loads the saved value. In contrast, the normal flow clears this bit to 0 when re-enabling single-shot control.

   Therefore, the restore function passes the restart_ss argument as false to etm4_enable_hw() to avoid re-enabling single-shot mode.

3. Claim Tag Handling

   The claim tag is acquired and released in normal flow, on the other hand, the claim protocol is not applied in CPU idle flow - it simply restores the saved value.

   The claim bits serve two purpose:

   • Exclusive access between the kernel driver and an external debugger. During CPU idle, the kernel driver locks the OS Lock, ensuring that the external debugger cannot access the trace unit. Therefore, it is safe to release the claim tag during idle.

   • Notification to supervisory software to save/restore context for external debuggers. The kernel driver does not touch the external debugger's claim bit (ETMCLAIM[0]).

   Based on this, it is safe to acquire and release claim tag in the idle sequence.

Not sure I agree - in the original save restore the claim tag state was retained - so if an external claim was asserted it would not be lost. here if we do not retain the claim tag value, then an external state can be lost.

The debugger cannot access the device during idle/oslok, but it can detect that the device is powered down/oslocked and this potential is a change of behaviour from the external debug perspective, where a race to claim the resource now exists over powerdown were one did not before.

4. OS Lock Behavior

   The OS Lock should be locked during CPU idle states. This differs from the normal flow, which unlock it. This special handling remains in the CPU save path.

This commit reuses the normal enable and disable logic in the CPU idle path. The only addition is locking the OS Lock upon entering idle to ensure exclusive access.

The save context in the driver data is no longer needed and has been removed.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-etm4x-core.c | 215 +-------------------- drivers/hwtracing/coresight/coresight-etm4x.h | 57 ------ 2 files changed, 5 insertions(+), 267 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index f61c9924ad0496be2e41c84172c2bbe348df7b60..4a75c76bb44fc284034e25f8eb8e7a04e9d35885 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1854,8 +1854,7 @@ static int etm4_dying_cpu(unsigned int cpu)

static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) {

•   int i, ret = 0;
  

•   struct etmv4_save_state *state;
  

•   int ret = 0;
    struct coresight_device *csdev = drvdata->csdev;
    struct csdev_access *csa;
    struct device *etm_dev;
  

@@ -1885,100 +1884,11 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) ret = -EBUSY; goto out; }

•   etm4_cs_lock(drvdata, csa);
  
  

•   if (!drvdata->paused)
  

•           etm4_disable_trace_unit(drvdata);
  

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

•   state = drvdata->save_state;
  

•   if (drvdata->nr_pe)
  

•           state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
  

•   state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
  

•   state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
  

•   state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
  

•   state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
  

•   if (drvdata->stallctl)
  

•           state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
  

•   state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
  

•   state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
  

•   state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
  

•   state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
  

•   state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
  

•   if (drvdata->q_filt)
  

•           state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
  

•   state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
  

•   state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
  

•   state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
  

•   if (drvdata->nr_pe_cmp)
  

•           state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
  

•   for (i = 0; i < drvdata->nrseqstate - 1; i++)
  

•           state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
  

•   if (drvdata->nrseqstate) {
  

•           state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
  

•           state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
  

The TRCSEQSTR changes in use, but is not read back be the standard enable/disable flow. This does not matter in a normal enable/disable case, but in a save/restore we need to retain the current state. Probably should be added to the normal disable flow to read back this as we do with counters etc.

•   }
  

•   if (drvdata->numextinsel)
  

•           state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
  

•   for (i = 0; i < drvdata->nr_cntr; i++) {
  

•           state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
  

•           state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
  

•           state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
  

•   }
  

•   /* Resource selector pair 0 is reserved */
  

•   for (i = 2; i < drvdata->nr_resource * 2; i++)
  

•           state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
  

•   for (i = 0; i < drvdata->nr_ss_cmp; i++) {
  

•           state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
  

•           state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
  

•           if (etm4x_sspcicrn_present(drvdata, i))
  

•                   state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
  

•   }
  

•   for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
  

•           state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
  

•           state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
  

•   }
  

•   /*
  

•    * Data trace stream is architecturally prohibited for A profile cores
  

•    * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
  

•    * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
  

•    * unit") of ARM IHI 0064D.
  

•    */
  

•   for (i = 0; i < drvdata->numcidc; i++)
  

•           state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
  

•   for (i = 0; i < drvdata->numvmidc; i++)
  

•           state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
  

•   state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
  

•   if (drvdata->numcidc > 4)
  

•           state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
  

•   state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
  

•   if (drvdata->numvmidc > 4)
  

•           state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
  

•   state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
  

•   if (!drvdata->skip_power_up)
  

•           state->trcpdcr = etm4x_read32(csa, TRCPDCR);
  

•   etm4_disable_hw(drvdata);
  
  

•   etm4_cs_unlock(drvdata, csa);
    /* wait for TRCSTATR.IDLE to go up */
    if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) {
            dev_err(etm_dev,
  

@@ -1988,14 +1898,6 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) goto out; }

•   /*
  

•    * Power can be removed from the trace unit now. We do this to
  

•    * potentially save power on systems that respect the TRCPDCR_PU
  

•    * despite requesting software to save/restore state.
  

•    */
  

•   if (!drvdata->skip_power_up)
  

•           etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
  

•                                 TRCPDCR);
  

out: etm4_cs_lock(drvdata, csa); return ret; @@ -2019,110 +1921,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)

static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) {

•   int i;
  

•   struct etmv4_save_state *state = drvdata->save_state;
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   if (WARN_ON(!drvdata->csdev))
            return;
  
  

•   etm4_cs_unlock(drvdata, csa);
  

•   etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
  

•   if (drvdata->nr_pe)
  

•           etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
  

•   etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
  

•   etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
  

•   etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
  

•   etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
  

•   if (drvdata->stallctl)
  

•           etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
  

•   etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
  

•   etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
  

•   etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
  

•   etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
  

•   etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
  

•   if (drvdata->q_filt)
  

•           etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
  

•   etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
  

•   etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
  

•   etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
  

•   if (drvdata->nr_pe_cmp)
  

•           etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
  

•   for (i = 0; i < drvdata->nrseqstate - 1; i++)
  

•           etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
  

•   if (drvdata->nrseqstate) {
  

•           etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
  

•           etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
  

•   }
  

•   if (drvdata->numextinsel)
  

•           etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
  

•   for (i = 0; i < drvdata->nr_cntr; i++) {
  

•           etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
  

•           etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
  

•           etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
  

•   }
  

•   /* Resource selector pair 0 is reserved */
  

•   for (i = 2; i < drvdata->nr_resource * 2; i++)
  

•           etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
  

•   for (i = 0; i < drvdata->nr_ss_cmp; i++) {
  

•           etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
  

•           etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
  

•           if (etm4x_sspcicrn_present(drvdata, i))
  

•                   etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
  

•   }
  

•   for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
  

•           etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
  

•           etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
  

•   }
  

•   for (i = 0; i < drvdata->numcidc; i++)
  

•           etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
  

•   for (i = 0; i < drvdata->numvmidc; i++)
  

•           etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
  

•   etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
  

•   if (drvdata->numcidc > 4)
  

•           etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
  

•   etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
  

•   if (drvdata->numvmidc > 4)
  

•           etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
  

•   etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
  

•   if (!drvdata->skip_power_up)
  

•           etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
  

•   /*
  

•    * As recommended by section 4.3.7 ("Synchronization when using the
  

•    * memory-mapped interface") of ARM IHI 0064D
  

•    */
  

•   dsb(sy);
  

•   isb();
  

•   /* Unlock the OS lock to re-enable trace and external debug access */
  

•   etm4_os_unlock(drvdata);
  

•   if (!drvdata->paused)
  

•           etm4_enable_trace_unit(drvdata);
  

•   /*
  

•    * As recommended by section 4.3.7 (Synchronization of register updates)
  

•    * of ARM IHI 0064H.b, the self-hosted trace analyzer always executes an
  

•    * ISB instruction after programming the trace unit registers.
  

•    */
  

•   isb();
  

•   etm4_cs_lock(drvdata, csa);
  

•   etm4_enable_hw(drvdata, false);
  

}

static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) @@ -2309,13 +2111,6 @@ static int etm4_probe(struct device *dev) pm_save_enable = coresight_loses_context_with_cpu(dev) ? PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;

•   if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
  

•           drvdata->save_state = devm_kmalloc(dev,
  

•                           sizeof(struct etmv4_save_state), GFP_KERNEL);
  

•           if (!drvdata->save_state)
  

•                   return -ENOMEM;
  

•   }
  

•   raw_spin_lock_init(&drvdata->spinlock);
  
    drvdata->cpu = coresight_get_cpu(dev);
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 012c52fd19338133129752d35523dc102df24604..9dfdcfc2b16748bedc278ba2ceaa7e39b29cc351 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -862,61 +862,6 @@ struct etmv4_config { u8 s_ex_level; };

-/**

• • struct etm4_save_state - state to be preserved when ETM is without power
• */

-struct etmv4_save_state {

•   u32     trcprocselr;
  

•   u32     trcconfigr;
  

•   u32     trcauxctlr;
  

•   u32     trceventctl0r;
  

•   u32     trceventctl1r;
  

•   u32     trcstallctlr;
  

•   u32     trctsctlr;
  

•   u32     trcsyncpr;
  

•   u32     trcccctlr;
  

•   u32     trcbbctlr;
  

•   u32     trctraceidr;
  

•   u32     trcqctlr;
  

•   u32     trcvictlr;
  

•   u32     trcviiectlr;
  

•   u32     trcvissctlr;
  

•   u32     trcvipcssctlr;
  

•   u32     trcseqevr[ETM_MAX_SEQ_STATES];
  

•   u32     trcseqrstevr;
  

•   u32     trcseqstr;
  

•   u32     trcextinselr;
  

•   u32     trccntrldvr[ETMv4_MAX_CNTR];
  

•   u32     trccntctlr[ETMv4_MAX_CNTR];
  

•   u32     trccntvr[ETMv4_MAX_CNTR];
  

•   u32     trcrsctlr[ETM_MAX_RES_SEL];
  

•   u32     trcssccr[ETM_MAX_SS_CMP];
  

•   u32     trcsscsr[ETM_MAX_SS_CMP];
  

•   u32     trcsspcicr[ETM_MAX_SS_CMP];
  

•   u64     trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
  

•   u64     trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
  

•   u64     trccidcvr[ETMv4_MAX_CTXID_CMP];
  

•   u64     trcvmidcvr[ETM_MAX_VMID_CMP];
  

•   u32     trccidcctlr0;
  

•   u32     trccidcctlr1;
  

•   u32     trcvmidcctlr0;
  

•   u32     trcvmidcctlr1;
  

•   u32     trcclaimset;
  

•   u32     cntr_val[ETMv4_MAX_CNTR];
  

•   u32     seq_state;
  

•   u32     vinst_ctrl;
  

•   u32     ss_status[ETM_MAX_SS_CMP];
  

•   u32     trcpdcr;
  

-};

/**

• struct etm4_drvdata - specifics associated to an ETM component
• @pclk: APB clock if present, otherwise NULL

@@ -979,7 +924,6 @@ struct etmv4_save_state {

•         at runtime, due to the additional setting of TRFCR_CX when
  

•         in EL2. Otherwise, 0.
  

• @config: structure holding configuration parameters.

• • @save_state: State to be preserved across power loss
  • @skip_power_up: Indicates if an implementation can skip powering up

  •            the trace unit.
    

  • @paused: Indicates if the trace unit is paused.

@@ -1034,7 +978,6 @@ struct etmv4_drvdata { bool lpoverride; u64 trfcr; struct etmv4_config config;

•   struct etmv4_save_state         *save_state;
    bool                            skip_power_up;
    bool                            paused;
    DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
  
  

-- 2.34.1

Regards

Mike

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

Introduce coresight_set_percpu_source() for setting CPU source device. The sources are maintained in a per CPU structure 'csdev_source'.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index db325dff884d21cc8d93f32bfe3be5c0491ffc8d..25a530cde8938b366bbb144fdcc107271ebae276 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -34,6 +34,7 @@ */ DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); +static DEFINE_PER_CPU(struct coresight_device *, csdev_source);

/**

• struct coresight_node - elements of a path, from source to sink

@@ -79,6 +80,11 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);

+static void coresight_set_percpu_source(int cpu, struct coresight_device *csdev) +{

•   per_cpu(csdev_source, cpu) = csdev;
  

+}

static struct coresight_device *coresight_get_source(struct coresight_path *path) { struct coresight_device *csdev; @@ -1393,6 +1399,10 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) goto out_unlock; } }

•   if (coresight_is_percpu_source(csdev))
  

•           coresight_set_percpu_source(csdev->cpu, csdev);
  

•   /* Device is now registered */
    registered = true;
  
  

@@ -1424,6 +1434,8 @@ EXPORT_SYMBOL_GPL(coresight_register);

void coresight_unregister(struct coresight_device *csdev) {

•   if (coresight_is_percpu_source(csdev))
  

•           coresight_set_percpu_source(csdev->cpu, NULL);
    etm_perf_del_symlink_sink(csdev);
    /* Remove references of that device in the topology */
    if (cti_assoc_ops && cti_assoc_ops->remove)
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org

Hi Leo,

This could be made more generic from the start - as multiple devices will eventually come under PM control.

Improve naming by explicitly mentioning _pm_ in function names.

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

The current implementation only saves and restores the context for ETM sources while ignoring the context of links. However, if funnels or replicators on a linked path resides in a CPU or cluster power domain, the hardware context for the link will be lost after resuming from low power states.

To support context management for links during CPU low power modes, a better way is to implement CPU PM callbacks in the Arm CoreSight core layer. As the core layer has sufficient information for linked paths, from tracers to links, which can be used for power management.

As a first step, this patch registers CPU PM notifier in the core layer. If a source driver provides callbacks for saving and restoring context, these callbacks will be invoked in CPU suspend and resume.

Further changes will extend for controlling path.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-core.c | 62 ++++++++++++++++++++++++++++ include/linux/coresight.h | 4 ++ 2 files changed, 66 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 25a530cde8938b366bbb144fdcc107271ebae276..f944a610c85e9e3fce43497543ccc48ab7c2c0d9 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -6,6 +6,7 @@ #include <linux/acpi.h> #include <linux/bitfield.h> #include <linux/build_bug.h> +#include <linux/cpu_pm.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/types.h> @@ -422,6 +423,21 @@ int coresight_resume_source(struct coresight_device *csdev) } EXPORT_SYMBOL_GPL(coresight_resume_source);

+static int coresight_save_source(struct coresight_device *csdev)

See comments below & make this a generic coresight_pm_save() fn.

+{

•   if (csdev && source_ops(csdev)->save)
  

and this could become

if(csdev && coresight_ops(csdev)->pm_save_disable)

•           return source_ops(csdev)->save(csdev);
  

•   /* Return success if callback is not supported */
  

•   return 0;
  

+}

+static void coresight_restore_source(struct coresight_device *csdev)

As above

+{

•   if (csdev && source_ops(csdev)->restore)
  

•           source_ops(csdev)->restore(csdev);
  

+}

/*

• coresight_disable_path_from : Disable components in the given path beyond
• @nd in the list. If @nd is NULL, all the components, except the SOURCE are

@@ -1575,6 +1591,45 @@ char *coresight_alloc_device_name(struct coresight_dev_list *dict, } EXPORT_SYMBOL_GPL(coresight_alloc_device_name);

+static int coresight_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,

•                              void *v)
  

+{

•   unsigned int cpu = smp_processor_id();
  

•   struct coresight_device *source = per_cpu(csdev_source, cpu);
  

•   if (!source)
  

•           return NOTIFY_OK;
  

•   switch (cmd) {
  

•   case CPU_PM_ENTER:
  

•           if (coresight_save_source(source))
  

•                   return NOTIFY_BAD;
  

•           break;
  

•   case CPU_PM_EXIT:
  

•   case CPU_PM_ENTER_FAILED:
  

•           coresight_restore_source(source);
  

•           break;
  

•   default:
  

•           return NOTIFY_DONE;
  

•   }
  

•   return NOTIFY_OK;
  

+}

+static struct notifier_block coresight_cpu_pm_nb = {

•   .notifier_call = coresight_cpu_pm_notify,
  

+};

+static int __init coresight_pm_setup(void) +{

•   return cpu_pm_register_notifier(&coresight_cpu_pm_nb);
  

+}

+static void coresight_pm_cleanup(void) +{

•   cpu_pm_unregister_notifier(&coresight_cpu_pm_nb);
  

+}

const struct bus_type coresight_bustype = { .name = "coresight", }; @@ -1629,9 +1684,15 @@ static int __init coresight_init(void)

    /* initialise the coresight syscfg API */
    ret = cscfg_init();

•   if (ret)
  

•           goto exit_notifier;
  

•   ret = coresight_pm_setup();
    if (!ret)
            return 0;
  
  

•   cscfg_exit();
  

+exit_notifier: atomic_notifier_chain_unregister(&panic_notifier_list, &coresight_notifier); exit_perf: @@ -1643,6 +1704,7 @@ static int __init coresight_init(void)

static void __exit coresight_exit(void) {

•   coresight_pm_cleanup();
    cscfg_exit();
    atomic_notifier_chain_unregister(&panic_notifier_list,
                                         &coresight_notifier);
  

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 222597ec7a089e10ad763df206917e90f34bb5c2..d0764a9c7692181d2619c277acb83701c6b0115e 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -400,6 +400,8 @@ struct coresight_ops_link {

• @disable: disables tracing for a source.
• @resume_perf: resumes tracing for a source in perf session.
• @pause_perf: pauses tracing for a source in perf session.

• • @save: save context for a source.
• • @restore: restore context for a source.
  */

struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); @@ -409,6 +411,8 @@ struct coresight_ops_source { struct perf_event *event); int (*resume_perf)(struct coresight_device *csdev); void (*pause_perf)(struct coresight_device *csdev);

•   int (*save)(struct coresight_device *csdev);
  

•   void (*restore)(struct coresight_device *csdev);
  

These functions should have more explicit names - better describe what they do and prevent a future developer thinking they are a benign states save/restore set (as they used to be!)

e.g.:

pm_save_disable / pm_restore_enable.

Further, since the only parameter is the csdev being acted on, the functions could be part of the generic coresight_ops structure (as per trace_id) rather than repeat the addition for each coresight type variant. Should simplify the handling code too.

Regards

Mike

};

/**

-- 2.34.1

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

Since the CoreSight core layer has registered CPU PM notifiers, this patch hooks CPU save and restore callbacks to be invoked from the core layer.

The CPU PM notifier in the ETMv4 driver is no longer needed, remove it along with its registration and unregistration code.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-etm4x-core.c | 73 ++++++---------------- 1 file changed, 18 insertions(+), 55 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7e66d094269de4a1344f5d962bc320b2603b7627..ec7e8d09ce58d62dac826fba9edafc967504a1a5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1186,19 +1186,6 @@ static void etm4_pause_perf(struct coresight_device *csdev) drvdata->paused = true; }

-static const struct coresight_ops_source etm4_source_ops = {

•   .cpu_id         = etm4_cpu_id,
  

•   .enable         = etm4_enable,
  

•   .disable        = etm4_disable,
  

•   .resume_perf    = etm4_resume_perf,
  

•   .pause_perf     = etm4_pause_perf,
  

-};

-static const struct coresight_ops etm4_cs_ops = {

•   .trace_id       = coresight_etm_get_trace_id,
  

•   .source_ops     = &etm4_source_ops,
  

-};

static bool cpu_supports_sysreg_trace(void) { u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); @@ -1903,8 +1890,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) return ret; }

-static int etm4_cpu_save(struct etmv4_drvdata *drvdata) +static int etm4_cpu_save(struct coresight_device *csdev) {

•   struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
    int ret = 0;
  
    if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED)
  

@@ -1927,8 +1915,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) etm4_enable_hw(drvdata, false); }

-static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) +static void etm4_cpu_restore(struct coresight_device *csdev) {

•   struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  

•   if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED)
            return;
  
  

@@ -1936,38 +1926,19 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) __etm4_cpu_restore(drvdata); }

-static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,

•                         void *v)
  

-{

•   struct etmv4_drvdata *drvdata;
  

•   unsigned int cpu = smp_processor_id();
  

•   if (!etmdrvdata[cpu])
  

•           return NOTIFY_OK;
  

•   drvdata = etmdrvdata[cpu];
  

•   if (WARN_ON_ONCE(drvdata->cpu != cpu))
  

•           return NOTIFY_BAD;
  

•   switch (cmd) {
  

•   case CPU_PM_ENTER:
  

•           if (etm4_cpu_save(drvdata))
  

•                   return NOTIFY_BAD;
  

•           break;
  

•   case CPU_PM_EXIT:
  

•   case CPU_PM_ENTER_FAILED:
  

•           etm4_cpu_restore(drvdata);
  

•           break;
  

•   default:
  

•           return NOTIFY_DONE;
  

•   }
  

•   return NOTIFY_OK;
  

-} +static const struct coresight_ops_source etm4_source_ops = {

•   .cpu_id         = etm4_cpu_id,
  

•   .enable         = etm4_enable,
  

•   .disable        = etm4_disable,
  

•   .resume_perf    = etm4_resume_perf,
  

•   .pause_perf     = etm4_pause_perf,
  

•   .save           = etm4_cpu_save,
  

•   .restore        = etm4_cpu_restore,
  

+};

-static struct notifier_block etm4_cpu_pm_nb = {

•   .notifier_call = etm4_cpu_pm_notify,
  

+static const struct coresight_ops etm4_cs_ops = {

•   .trace_id       = coresight_etm_get_trace_id,
  

•   .source_ops     = &etm4_source_ops,
  

};

/* Setup PM. Deals with error conditions and counts */ @@ -1975,16 +1946,12 @@ static int __init etm4_pm_setup(void) { int ret;

•   ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
  

•   if (ret)
  

•           return ret;
  

•   ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
                                    "arm/coresight4:starting",
                                    etm4_starting_cpu, etm4_dying_cpu);
  
    if (ret)
  

•           goto unregister_notifier;
  

•           return ret;
  
    ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
                                    "arm/coresight4:online",
  

@@ -1998,15 +1965,11 @@ static int __init etm4_pm_setup(void)

    /* failed dyn state - remove others */
    cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);

-unregister_notifier:

•   cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
    return ret;
  

}

static void etm4_pm_clear(void) {

•   cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
    cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
    if (hp_online) {
            cpuhp_remove_state_nocalls(hp_online);
  
  

-- 2.34.1

c.f. my previous comments regarding save/restore nameing and location

otherwise looks fine.

Mike

Hi Leo

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

Add a callback in the source device that returns a boolean indicating whether context save and restore operations are required. The save and restore flow is skipped if the callback returns false.

The ETMv4 driver implements its own version's callback.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-core.c | 16 +++++++++++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 30 +++++++++++++++++----- include/linux/coresight.h | 2 ++ 3 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f944a610c85e9e3fce43497543ccc48ab7c2c0d9..94803cacf1a374ae8a3b9513d7d029d5c77d5925 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -423,6 +423,20 @@ int coresight_resume_source(struct coresight_device *csdev) } EXPORT_SYMBOL_GPL(coresight_resume_source);

+static bool coresight_need_save_restore_source(struct coresight_device *csdev) +{

•   if (!csdev)
  

•           return false;
  

•   if (source_ops(csdev)->need_context_save_restore)
  

check the actual save and restore ops here too?

•           return source_ops(csdev)->need_context_save_restore(csdev);
  

•   if (coresight_get_mode(csdev))
  

•           return true;
  

Not needed - should decide only on the previous need_context_save_restore() test. Components such as STM, ETR, ETB all use the mode status, but may not support / need save and restore.

•   return false;
  

+}

static int coresight_save_source(struct coresight_device *csdev) { if (csdev && source_ops(csdev)->save) @@ -1597,7 +1611,7 @@ static int coresight_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, unsigned int cpu = smp_processor_id(); struct coresight_device *source = per_cpu(csdev_source, cpu);

•   if (!source)
  

•   if (!coresight_need_save_restore_source(source))
            return NOTIFY_OK;
  
    switch (cmd) {
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index ec7e8d09ce58d62dac826fba9edafc967504a1a5..66aefdb002f075446572df9c4eed9093da19a066 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1839,6 +1839,21 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; }

+static bool etm4_need_context_save_restore(struct coresight_device *csdev) +{

•   if (pm_save_enable != PARAM_PM_SAVE_SELF_HOSTED)
  

•           return false;
  

•   /*
  

•    * Save and restore the ETM Trace registers only if
  

•    * the ETM is active.
  

•    */
  

•   if (coresight_get_mode(csdev))
  

•           return true;
  

•   return false;
  

+}

static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int ret = 0; @@ -1927,13 +1942,14 @@ static void etm4_cpu_restore(struct coresight_device *csdev) }

static const struct coresight_ops_source etm4_source_ops = {

•   .cpu_id         = etm4_cpu_id,
  

•   .enable         = etm4_enable,
  

•   .disable        = etm4_disable,
  

•   .resume_perf    = etm4_resume_perf,
  

•   .pause_perf     = etm4_pause_perf,
  

•   .save           = etm4_cpu_save,
  

•   .restore        = etm4_cpu_restore,
  

•   .cpu_id                    = etm4_cpu_id,
  

•   .enable                    = etm4_enable,
  

•   .disable                   = etm4_disable,
  

•   .resume_perf               = etm4_resume_perf,
  

•   .pause_perf                = etm4_pause_perf,
  

•   .save                      = etm4_cpu_save,
  

•   .restore                   = etm4_cpu_restore,
  

Above are just white space change noise as far as I can see.

•   .need_context_save_restore = etm4_need_context_save_restore,
  

};

static const struct coresight_ops etm4_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index d0764a9c7692181d2619c277acb83701c6b0115e..39781ba24ee2ad9f3065770409aafb0e5af57fa8 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -400,6 +400,7 @@ struct coresight_ops_link {

• @disable: disables tracing for a source.
• @resume_perf: resumes tracing for a source in perf session.
• @pause_perf: pauses tracing for a source in perf session.

• • @need_context_save_restore: if need to save and restore context.
  • @save: save context for a source.
  • @restore: restore context for a source.
  */

@@ -411,6 +412,7 @@ struct coresight_ops_source { struct perf_event *event); int (*resume_perf)(struct coresight_device *csdev); void (*pause_perf)(struct coresight_device *csdev);

•   bool (*need_context_save_restore)(struct coresight_device *csdev);
    int (*save)(struct coresight_device *csdev);
    void (*restore)(struct coresight_device *csdev);
  

};

-- 2.34.1

Regards

Mike

Hi Leo

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

Introduce per-CPU path pointers, save activated paths into the structure. This will be used by later changes for controlling the path during CPU idle.

The path pointer is assigned before setting the source device mode to active, and it is cleared after the device is changed to an inactive mode. So safe access to path pointers is guaranteed when the device is in an active mode.

The path enabling has been refactored: a new _coresight_enable_path() function is introduced to enable components in the path. The existing coresight_enable_path() function now calls this new helper and updates the per-CPU pointers accordingly.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 94803cacf1a374ae8a3b9513d7d029d5c77d5925..904123279ee70531787feea98e5f9fc502470f88 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -37,6 +37,27 @@ DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); static DEFINE_PER_CPU(struct coresight_device *, csdev_source);

+/*

• • Activated path pointer for a per-CPU source device. When enabling a path,
• • the path pointer is first assigned, followed by a synchronous SMP call on
• • the target CPU to transition the device mode from DISABLED to an enabled
• • state. Conversely, during the disable flow, an SMP call on the target CPU
• • transitions the device mode to DISABLED, after which the path pointer is
• • cleared.
• • per_cpu(csdev_cpu_path, csdev->cpu) = path
• • coresight_take_mode(csdev, CS_MODE_SYSFS or CS_MODE_PERF)
• • // Safe to access per_cpu(csdev_cpu_path, cpu);
• • coresight_set_mode(csdev, CS_MODE_DISABLED)
• • per_cpu(csdev_cpu_path, csdev->cpu) = NULL
• • As a result, the device mode is used to determine whether it is safe
• • to access the path pointer.
• */

+static DEFINE_PER_CPU(struct coresight_path *, csdev_cpu_path);

This replicates the per-cpu tracer_path variable in coresight-sysfs.c - seems there should be a way to combine them. This is also set / unset on enable / disable

/**

• struct coresight_node - elements of a path, from source to sink
• @csdev: Address of an element.

@@ -510,6 +531,12 @@ static void coresight_disable_path_from(struct coresight_path *path,

void coresight_disable_path(struct coresight_path *path) {

•   struct coresight_device *source;
  

•   source = coresight_get_source(path);
  

•   if (coresight_is_percpu_source(source))
  

•           per_cpu(csdev_cpu_path, source->cpu) = NULL;
  

•   coresight_disable_path_from(path, NULL);
  

} EXPORT_SYMBOL_GPL(coresight_disable_path); @@ -533,8 +560,8 @@ static int coresight_enable_helpers(struct coresight_device *csdev, return 0; }

-int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,

•                     void *sink_data)
  

+static int _coresight_enable_path(struct coresight_path *path,

•                             enum cs_mode mode, void *sink_data)
  

{ int ret = 0; u32 type; @@ -601,6 +628,23 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, goto out; }

+int coresight_enable_path(struct coresight_path *path, enum cs_mode mode,

•                     void *sink_data)
  

+{

•   int ret;
  

•   struct coresight_device *source;
  

•   ret = _coresight_enable_path(path, mode, sink_data);
  

•   if (ret)
  

•           return ret;
  

•   source = coresight_get_source(path);
  

•   if (coresight_is_percpu_source(source))
  

•           per_cpu(csdev_cpu_path, source->cpu) = path;
  

why is this in a refactored function for enable() but not disable(). Seems that the original coresight_enable_path() creates a 'source' variable, so just the two lines

if (coresight_is_percpu_source(source)) per_cpu(csdev_cpu_path, source->cpu) = path;

added to the original function acheives the same thing with less churn

Regards

Mike

•   return 0;
  

+}

struct coresight_device *coresight_get_sink(struct coresight_path *path) { struct coresight_device *csdev;

-- 2.34.1

On Fri, Oct 03, 2025 at 12:42:39PM +0100, Mike Leach wrote:

[...]

...

@@ -502,6 +503,10 @@ static void coresight_disable_path_from(struct coresight_path *path, CORESIGHT_DEV_TYPE_SINK : CORESIGHT_DEV_TYPE_LINK;

•           /* To reduce latency, CPU idle does not touch the sink */
  

•           if (in_idle && type == CORESIGHT_DEV_TYPE_SINK)
  

•                   continue;
  

Why not - if this is the last/only active path then you absolutely want to disable the sink to flush trace through the system. If it is not, then the disable sink will simply reduce the refcount by one.

CPU idle is latency sensitive, and the CPU can enter and exit low power states frequently.

And ETR uses a bounce buffer. If we disable the sink in the idle path, that not only disables the sink but also copies data from the bounce buffer to the perf AUX ring buffer, which can introduce significant latency. Given the latency is not constrained, this is why we don't disable sink for CPUidle.

To be clear, we will disable sink for CPU hotplug case, in this case, CPU hotplug itself usually has no high requirement for latency, and we will expect CPU hotplug does not happen frequently, thus it makes sense to disable sink (and copying trace data).

Thanks, Leo

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

The hotplug lock is acquired and released in the etm4_disable_sysfs() function, which is a low-level function located in the ETM4 driver. This prevents us from a new solution for hotplug.

Firstly, hotplug callbacks cannot invoke etm4_disable_sysfs() to disable the source; otherwise, a deadlock issue occurs. The reason is that, in the hotplug flow, the kernel acquires the hotplug lock before calling callbacks. Subsequently, if coresight_disable_source() is invoked and it calls etm4_disable_sysfs(), the hotplug lock will be acquired twice, leading to a double lock issue.

Secondly, when hotplugging a CPU on or off, if we want to manipulate all components on a path attached to the CPU, we need to maintain atomicity for the entire path. Otherwise, a race condition may occur with users setting the same path via the Sysfs knobs, ultimately causing mess states in CoreSight components.

This patch moves the hotplug locking from etm4_disable_sysfs() into enable_source_store(). As a result, when users control the Sysfs knobs, the whole flow is protected by hotplug locking, ensuring it is mutual exclusive with hotplug callbacks.

Note, the paired function etm4_enable_sysfs() does not use hotplug locking, which is why this patch does not modify it.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 --------- drivers/hwtracing/coresight/coresight-sysfs.c | 7 +++++++ 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4218cefca63d7b2f3b102e74d7f007ebc7b08861..920c817de8c33751760a1ed7ab1df8437620bb4e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1088,13 +1088,6 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   /*
  

•    * Taking hotplug lock here protects from clocks getting disabled
  

•    * with tracing being left on (crash scenario) if user disable occurs
  

•    * after cpu online mask indicates the cpu is offline but before the
  

•    * DYING hotplug callback is serviced by the ETM driver.
  

•    */
  

•   cpus_read_lock();
    raw_spin_lock(&drvdata->spinlock);
  
    /*
  

@@ -1108,8 +1101,6 @@ static void etm4_disable_sysfs(struct coresight_device *csdev)

    cscfg_csdev_disable_active_config(csdev);

•   cpus_read_unlock();
  

•   /*
     * we only release trace IDs when resetting sysfs.
     * This permits sysfs users to read the trace ID after the trace
  

diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c index cb02f1bfaf068ec3f50f997bcb94f7d5215ccea8..a4c5a334703f0bb35db5eeda87ae5a9756f6a453 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -363,6 +363,13 @@ static ssize_t enable_source_store(struct device *dev, if (ret) return ret;

•   /*
  

•    * CoreSight hotplug callbacks in core layer control a activated path
  

•    * from its source to sink. Taking hotplug lock here protects a race
  

•    * condition with hotplug callbacks.
  

•    */
  

•   guard(cpus_read_lock)();
  

•   if (val) {
            ret = coresight_enable_sysfs(csdev);
            if (ret)
  
  

-- 2.34.1

Reviewed-by: Mike Leach mike.leach@linaro.org