On 8/19/23 02:41, Randy Dunlap wrote:
Hi--
On 8/18/23 04:20, Anshuman Khandual wrote:
This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN field in ETM gets an wrong value.
If software uses the value returned by the TRCIDR3.CCITMIN register field, then it will limit the range which could be used for programming the ETM. In reality, the ETM could be programmed with a much smaller value than what is indicated by the TRCIDR3.CCITMIN field and still function correctly.
If software reads the TRCIDR3.CCITMIN register field, corresponding to the instruction trace counting minimum threshold, observe the value 0x100 or a minimum cycle count threshold of 256. The correct value should be 0x4 or a minimum cycle count threshold of 4.
This work arounds the problem via storing 4 in drvdata->ccitmin on affected systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count threshold granularity.
These errata information has been updated in arch/arm64/silicon-errata.rst, but without their corresponding configs because these have been implemented directly in the driver.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: Mike Leach mike.leach@linaro.org Cc: James Clark james.clark@arm.com Cc: Jonathan Corbet corbet@lwn.net Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
Documentation/arch/arm64/silicon-errata.rst | 10 ++++++ .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++++++ 2 files changed, 46 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7e307022303a..591fab73ee79 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1131,6 +1131,39 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) drvdata->trfcr = trfcr; } +/*
- The following errata on applicable cpu ranges, affect the CCITMIN filed
- in TCRIDR3 register. Software read for the field returns 0x100 limiting
- the cycle threshold granularity, where as the right value should have
whereas
- been 0x4, which is well supported in the hardware.
- */
+static struct midr_range etm_wrong_ccitmin_cpus[] = {
- /* Erratum #1490853 - Cortex-A76 */
- MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
- /* Erratum #1490853 - Neoverse-N1 */
- MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
- /* Erratum #1491015 - Cortex-A77 */
- MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
- /* Erratum #1502854 - Cortex-X1 */
- MIDR_REV(MIDR_CORTEX_X1, 0, 0),
- /* Erratum #1619801 - Neoverse-V1 */
- MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
- {},
+};
+static bool etm4_core_reads_wrong_ccitmin(struct etmv4_drvdata *drvdata) +{
- /*
* Erratum affected cpus will read 256 as the minimum* instruction trace cycle counting threshold where aswhereas
Right, 'whereas' is a single word indeed. I will change these as required.
-
Anshuman Khandual