Adds in required sysfs access for:- - CoreSight management registers. - CTI device specific registers. - Channel Cross triggering API.

This provides the basic programming interface for the device.

Signed-off-by: Mike Leach mike.leach@linaro.org --- .../hwtracing/coresight/coresight-cti-sysfs.c | 831 +++++++++++++++++- drivers/hwtracing/coresight/coresight-cti.c | 188 +++- drivers/hwtracing/coresight/coresight-cti.h | 42 + drivers/hwtracing/coresight/coresight-priv.h | 2 + 4 files changed, 1053 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 9b6749621dcb..ff8dad02a779 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,8 @@ static ssize_t enable_show(struct device *dev, struct device_attribute *attr, char *buf) { - int enable_req; - bool enabled, powered, cpuid; + int enable_req, cpuid; + bool enabled, powered; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); ssize_t size = 0;

@@ -46,12 +46,18 @@ static ssize_t enable_show(struct device *dev, cpuid = drvdata->ctidev.cpu; spin_unlock(&drvdata->spinlock);

- if (powered) { - size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d powered;\n", - enabled ? "enabled" : "disabled", cpuid); - } else if (cpuid >= 0) { - size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d unpowered;\n", - enable_req ? "enable req" : "disable req", cpuid); + if (cpuid >= 0) { + if (powered) { + size = scnprintf(buf, PAGE_SIZE, + "cti %s; cpu%d powered;\n", + enabled ? "enabled" : "disabled", + cpuid); + } else { + size = scnprintf(buf, PAGE_SIZE, + "cti %s; cpu%d unpowered;\n", + enable_req ? "enable req" : "disable req", + cpuid); + } } else { size = scnprintf(buf, PAGE_SIZE, "cti %s; no assoc cpu;\n", enabled ? "enabled" : "disabled"); @@ -81,17 +87,826 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable);

+static ssize_t ctmid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return scnprintf(buf, PAGE_SIZE, "0x%x\n", drvdata->ctidev.ctm_id); +} +static DEVICE_ATTR_RO(ctmid); + /* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr, + &dev_attr_ctmid.attr, NULL, };

+/* register based attributes */ +#define coresight_cti_reg(name, offset) \ + coresight_simple_reg32(struct cti_drvdata, name, offset) + +/* + * Show a simple 32 bit value. If pval is NULL then live read, + * otherwise read from supplied pointer only. + */ +static ssize_t cti_reg32_show(struct device *dev, char *buf, + u32 *pval, int reg_offset) +{ + unsigned long val = 0; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + if (pval) { + val = (unsigned long)*pval; + } else if ((reg_offset >= 0) && CTI_PWR_ENA(config)) { + CS_UNLOCK(drvdata->base); + val = readl_relaxed(drvdata->base + reg_offset); + CS_LOCK(drvdata->base); + } + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +/* + * Store a simple 32 bit value. + * If pval not NULL, then copy to here too, + * if reg_offset >= 0 then write through if enabled. + */ +static ssize_t cti_reg32_store(struct device *dev, const char *buf, + size_t size, u32 *pval, + int reg_offset) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + /* local store */ + if (pval) + *pval = (u32)val; + + /* write through of offset and enabled */ + if ((reg_offset >= 0) && CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, reg_offset, val); + spin_unlock(&drvdata->spinlock); + return size; +} + +/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4); + +static struct attribute *coresight_cti_mgmt_attrs[] = { + &dev_attr_devaff0.attr, + &dev_attr_devaff1.attr, + &dev_attr_authstatus.attr, + &dev_attr_devarch.attr, + &dev_attr_devid.attr, + &dev_attr_devtype.attr, + &dev_attr_pidr0.attr, + &dev_attr_pidr1.attr, + &dev_attr_pidr2.attr, + &dev_attr_pidr3.attr, + &dev_attr_pidr4.attr, + NULL, +}; + +/* CTI low level programming registers */ +static ssize_t inout_sel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u32 val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = (u32)drvdata->config.ctiinout_sel; + return scnprintf(buf, PAGE_SIZE, "%#x\n", val); +} + +static ssize_t inout_sel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > (CTIINOUTEN_MAX-1)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->config.ctiinout_sel = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(inout_sel); + +static ssize_t inen_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + int index; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + index = drvdata->config.ctiinout_sel; + val = drvdata->config.ctiinen[index]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "INEN%d %#lx\n", index, val); +} + +static ssize_t inen_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + int index; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + index = config->ctiinout_sel; + config->ctiinen[index] = val; + + /* write through if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIINEN(index), val); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(inen); + +static ssize_t outen_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + int index; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + index = drvdata->config.ctiinout_sel; + val = drvdata->config.ctiouten[index]; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "OUTEN%d %#lx\n", index, val); +} + +static ssize_t outen_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + int index; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + index = config->ctiinout_sel; + config->ctiouten[index] = val; + + /* write through if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIOUTEN(index), val); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(outen); + +static ssize_t gate_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_show(dev, buf, &drvdata->config.ctigate, -1); +} + +static ssize_t gate_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_store(dev, buf, size, + &drvdata->config.ctigate, CTIGATE); +} +static DEVICE_ATTR_RW(gate); + +static ssize_t asicctl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_show(dev, buf, &drvdata->config.asicctl, -1); +} + +static ssize_t asicctl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_store(dev, buf, size, + &drvdata->config.asicctl, ASICCTL); +} +static DEVICE_ATTR_RW(asicctl); + +static ssize_t intack_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + cti_write_intack(dev, val); + return size; +} +static DEVICE_ATTR_WO(intack); + +static ssize_t appset_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_show(dev, buf, &drvdata->config.ctiappset, -1); +} + +static ssize_t appset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return cti_reg32_store(dev, buf, size, + &drvdata->config.ctiappset, CTIAPPSET); +} +static DEVICE_ATTR_RW(appset); + +static ssize_t appclear_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val, mask; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + + /* a 1'b1 in appclr clears down the same bit in appset*/ + mask = ~val; + config->ctiappset &= mask; + + /* write through if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIAPPCLEAR, val); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_WO(appclear); + +static ssize_t apppulse_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val, mask; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + + /* + * a 1'b1 in apppulse sets then clears the bit, + * effectively clears down the same bit in appset + */ + mask = ~val; + config->ctiappset &= mask; + + /* write through if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIAPPPULSE, val); + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_WO(apppulse); + +static ssize_t itchout_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return cti_reg32_show(dev, buf, NULL, ITCHOUT); +} + +static ssize_t itchout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_reg32_store(dev, buf, size, NULL, ITCHOUT); +} +static DEVICE_ATTR_RW(itchout); + +static ssize_t ittrigout_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return cti_reg32_show(dev, buf, NULL, ITTRIGOUT); +} + +static ssize_t ittrigout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_reg32_store(dev, buf, size, NULL, ITTRIGOUT); +} +static DEVICE_ATTR_RW(ittrigout); + +static ssize_t itchinack_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_reg32_store(dev, buf, size, NULL, ITCHINACK); +} +static DEVICE_ATTR_WO(itchinack); + +static ssize_t ittriginack_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_reg32_store(dev, buf, size, NULL, ITTRIGINACK); +} +static DEVICE_ATTR_WO(ittriginack); + +static ssize_t itctrl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return cti_reg32_show(dev, buf, NULL, CORESIGHT_ITCTRL); +} + +static ssize_t itctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_reg32_store(dev, buf, size, NULL, CORESIGHT_ITCTRL); +} +static DEVICE_ATTR_RW(itctrl); + +coresight_cti_reg(triginstatus, CTITRIGINSTATUS); +coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS); +coresight_cti_reg(chinstatus, CTICHINSTATUS); +coresight_cti_reg(choutstatus, CTICHOUTSTATUS); +coresight_cti_reg(ittrigin, ITTRIGIN); +coresight_cti_reg(itchin, ITCHIN); +coresight_cti_reg(itchoutack, ITCHOUTACK); +coresight_cti_reg(ittrigoutack, ITTRIGOUTACK); + +static struct attribute *coresight_cti_regs_attrs[] = { + &dev_attr_inout_sel.attr, + &dev_attr_inen.attr, + &dev_attr_outen.attr, + &dev_attr_gate.attr, + &dev_attr_asicctl.attr, + &dev_attr_intack.attr, + &dev_attr_appset.attr, + &dev_attr_appclear.attr, + &dev_attr_apppulse.attr, + &dev_attr_triginstatus.attr, + &dev_attr_trigoutstatus.attr, + &dev_attr_chinstatus.attr, + &dev_attr_choutstatus.attr, + &dev_attr_itctrl.attr, + &dev_attr_ittrigin.attr, + &dev_attr_itchin.attr, + &dev_attr_ittrigout.attr, + &dev_attr_itchout.attr, + &dev_attr_itchoutack.attr, + &dev_attr_ittrigoutack.attr, + &dev_attr_ittriginack.attr, + &dev_attr_itchinack.attr, + NULL, +}; + +/* CTI channel x-trigger programming */ +static int +cti_trig_op_parse(struct device *dev, enum cti_chan_op op, + enum cti_trig_dir dir, const char *buf, size_t size) +{ + u32 chan_idx; + u32 trig_idx; + int items, err = size; + + /* extract chan idx and trigger idx */ + items = sscanf(buf, "%d %d", &chan_idx, &trig_idx); + if (items) { + err = cti_channel_trig_op(dev, op, dir, chan_idx, trig_idx); + if (!err) + err = size; + } else + err = -EINVAL; + return err; +} + +static ssize_t trigin_attach_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_IN, + buf, size); +} +static DEVICE_ATTR_WO(trigin_attach); + +static ssize_t trigin_detach_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_IN, + buf, size); +} +static DEVICE_ATTR_WO(trigin_detach); + +static ssize_t trigout_attach_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_OUT, + buf, size); +} +static DEVICE_ATTR_WO(trigout_attach); + +static ssize_t trigout_detach_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_OUT, + buf, size); +} +static DEVICE_ATTR_WO(trigout_detach); + + +static ssize_t gate_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int err = 0, channel = 0; + + if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) { + err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE_ALL, 0); + } else { + if (kstrtoint(buf, 0, &channel)) + return -EINVAL; + + err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE, channel); + } + return err ? err : size; +} +static DEVICE_ATTR_WO(gate_enable); + +static ssize_t gate_disable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int err = 0, channel = 0; + + if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) { + err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE_ALL, 0); + } else { + if (kstrtoint(buf, 0, &channel)) + return -EINVAL; + + err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE, channel); + } + return err ? err : size; +} +static DEVICE_ATTR_WO(gate_disable); + +static int +chan_op_parse(struct device *dev, enum cti_chan_set_op op, const char *buf) +{ + int err = 0, channel = 0; + + if (kstrtoint(buf, 0, &channel)) + return -EINVAL; + + err = cti_channel_setop(dev, op, channel); + return err; + +} + +static ssize_t chan_set_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int err = chan_op_parse(dev, CTI_CHAN_SET, buf); + + return err ? err : size; +} +static DEVICE_ATTR_WO(chan_set); + +static ssize_t chan_clear_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int err = chan_op_parse(dev, CTI_CHAN_CLR, buf); + + return err ? err : size; +} +static DEVICE_ATTR_WO(chan_clear); + +static ssize_t chan_pulse_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int err = chan_op_parse(dev, CTI_CHAN_PULSE, buf); + + return err ? err : size; +} +static DEVICE_ATTR_WO(chan_pulse); + +static ssize_t trig_filter_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + spin_lock(&drvdata->spinlock); + val = drvdata->config.trig_filter_enable; + spin_unlock(&drvdata->spinlock); + return scnprintf(buf, PAGE_SIZE, "%ld (%s)\n", val, + val ? "enabled" : "disabled"); +} + +static ssize_t trig_filter_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->config.trig_filter_enable = val ? 1 : 0; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(trig_filter_enable); + +/* clear all xtrigger / channel programming */ +static ssize_t reset_xtrigs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int i; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + + /* clear the CTI trigger / channel programming registers */ + for (i = 0; i < config->nr_trig_max; i++) { + config->ctiinen[i] = 0; + config->ctiouten[i] = 0; + } + + /* clear the other regs */ + config->ctigate = (0x1 << config->nr_ctm_channels) - 1; + config->asicctl = 0; + config->ctiappset = 0; + config->ctiinout_sel = 0; + + /* if enabled then write through */ + if (CTI_PWR_ENA(config)) + cti_write_all_hw_regs(drvdata); + + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_WO(reset_xtrigs); + +static ssize_t show_chan_sel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + u32 val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = (u32)drvdata->config.xtrig_rchan_sel; + return scnprintf(buf, PAGE_SIZE, "%d\n", val); +} + +/* select a channel for the show_chan_xtrig function */ +static ssize_t show_chan_sel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val > (drvdata->config.nr_ctm_channels-1)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->config.xtrig_rchan_sel = val; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(show_chan_sel); + +/* for the selected channel - show the signals attached. */ +static ssize_t show_chan_xtrigs_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *cfg = &drvdata->config; + int used = 0, reg_idx; + int buf_sz = PAGE_SIZE; + u32 chan_mask = 0x1 << cfg->xtrig_rchan_sel; + + used += scnprintf(buf, buf_sz, "IN: "); + for (reg_idx = 0; + reg_idx < drvdata->config.nr_trig_max; + reg_idx++) { + if (chan_mask & cfg->ctiinen[reg_idx]) { + used += scnprintf(buf+used, buf_sz-used, "%d ", + reg_idx); + } + } + + used += scnprintf(buf+used, buf_sz-used, " OUT: "); + for (reg_idx = 0; + reg_idx < drvdata->config.nr_trig_max; + reg_idx++) { + if (chan_mask & cfg->ctiouten[reg_idx]) { + used += scnprintf(buf+used, buf_sz-used, "%d ", + reg_idx); + } + } + used += scnprintf(buf+used, buf_sz-used, "\n"); + return used; +} +static DEVICE_ATTR_RO(show_chan_xtrigs); + +static ssize_t print_chan_list(struct device *dev, + char *buf, bool inuse) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + int used = 0, i; + u32 inuse_bits = 0, chan_mask, chan_bit_mask; + + /* scan regs to get bitmap of channels in use. */ + spin_lock(&drvdata->spinlock); + for (i = 0; i < config->nr_trig_max; i++) { + inuse_bits |= config->ctiinen[i]; + inuse_bits |= config->ctiouten[i]; + } + spin_unlock(&drvdata->spinlock); + + /* inverse bits if printing free channels */ + if (!inuse) + inuse_bits = ~inuse_bits; + + /* list of channels, or 'none' */ + chan_mask = ((u32)(0x1 << config->nr_ctm_channels)) - 1; + if (inuse_bits & chan_mask) { + for (i = 0; i < config->nr_ctm_channels; i++) { + chan_bit_mask = 0x1 << i; + if (chan_bit_mask & inuse_bits) { + used += scnprintf(buf+used, PAGE_SIZE-used, + "%d ", i); + } + } + used += scnprintf(buf+used, PAGE_SIZE-used, "\n"); + } else { + used = scnprintf(buf, PAGE_SIZE, "none\n"); + } + return used; +} + +static ssize_t list_inuse_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return print_chan_list(dev, buf, true); +} +static DEVICE_ATTR_RO(list_inuse); + +static ssize_t list_free_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return print_chan_list(dev, buf, false); +} +static DEVICE_ATTR_RO(list_free); + +static ssize_t list_gate_ena_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *cfg = &drvdata->config; + int b_sz = PAGE_SIZE; + u32 chan_mask; + int chan, used = 0; + + if (cfg->ctigate == 0) { + used += scnprintf(buf, b_sz, "none\n"); + } else { + for (chan = 0; chan < cfg->nr_ctm_channels; chan++) { + chan_mask = 0x1 << chan; + if (chan_mask & cfg->ctigate) { + used += scnprintf(buf+used, b_sz-used, "%d ", + chan); + } + } + used += scnprintf(buf+used, b_sz-used, "\n"); + } + return used; +} +static DEVICE_ATTR_RO(list_gate_ena); + +static struct attribute *coresight_cti_channel_attrs[] = { + &dev_attr_trigin_attach.attr, + &dev_attr_trigin_detach.attr, + &dev_attr_trigout_attach.attr, + &dev_attr_trigout_detach.attr, + &dev_attr_gate_enable.attr, + &dev_attr_gate_disable.attr, + &dev_attr_chan_set.attr, + &dev_attr_chan_clear.attr, + &dev_attr_chan_pulse.attr, + &dev_attr_trig_filter_enable.attr, + &dev_attr_reset_xtrigs.attr, + &dev_attr_show_chan_sel.attr, + &dev_attr_show_chan_xtrigs.attr, + &dev_attr_list_inuse.attr, + &dev_attr_list_free.attr, + &dev_attr_list_gate_ena.attr, + NULL, +}; + +/* attribute and group sysfs tables. */ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, };

+static const struct attribute_group coresight_cti_mgmt_group = { + .attrs = coresight_cti_mgmt_attrs, + .name = "mgmt", +}; + +static const struct attribute_group coresight_cti_regs_group = { + .attrs = coresight_cti_regs_attrs, + .name = "regs", +}; + +static const struct attribute_group coresight_cti_channels_group = { + .attrs = coresight_cti_channel_attrs, + .name = "channels", +}; + const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group, + &coresight_cti_mgmt_group, + &coresight_cti_regs_group, + &coresight_cti_channels_group, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 0a0fb6d48237..06b1f84795a4 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -69,7 +69,7 @@ static int cti_cpu_count; dev_get_drvdata(csdev->dev.parent)

/* write set of regs to hardware - call with spinlock claimed */ -static void cti_write_all_hw_regs(struct cti_drvdata *drvdata) +void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; int i; @@ -173,6 +173,13 @@ static int cti_disable_hw(void *info) return 0; }

+void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) +{ + CS_UNLOCK(drvdata->base); + writel_relaxed(value, drvdata->base+offset); + CS_LOCK(drvdata->base); +} + static void cti_set_default_config(struct cti_config *config) { /* Most regs default to 0 as zalloc'ed except...*/ @@ -285,6 +292,178 @@ int cti_add_default_connection(struct cti_drvdata *drvdata) return ret; }

+/** cti channel api **/ +/* attach/detach channel from trigger - write through if enabled. */ +int cti_channel_trig_op(struct device *dev, + enum cti_chan_op op, + enum cti_trig_dir direction, + u32 channel_idx, + u32 trigger_idx) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + u32 trig_bitmask; + u32 chan_bitmask; + u32 reg_value; + int reg_offset; + + dev_info(dev, "chan_trig_op: op %d, dir %d, chan %d, trig %d\n", + op, direction, channel_idx, trigger_idx); + + /* ensure indexes in range */ + if ((channel_idx >= config->nr_ctm_channels) || + (trigger_idx >= config->nr_trig_max)) + return -EINVAL; + + trig_bitmask = 0x1 << trigger_idx; + + /* ensure registered triggers and not out filtered */ + if (direction == CTI_TRIG_IN) { + if (!(trig_bitmask & config->trig_in_use)) + return -EINVAL; + } else { + if (!(trig_bitmask & config->trig_out_use)) + return -EINVAL; + + if ((config->trig_filter_enable) && + (config->trig_out_filter & trig_bitmask)) + return -EINVAL; + } + + /* update the local register values */ + chan_bitmask = 0x1 << channel_idx; + reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : + CTIOUTEN(trigger_idx)); + + spin_lock(&drvdata->spinlock); + + /* read - modify write - the trigger / channel enable value */ + reg_value = (direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] : + config->ctiouten[trigger_idx]); + reg_value = (op == CTI_CHAN_ATTACH) ? reg_value | chan_bitmask : + reg_value & (~chan_bitmask); + + /* write local copy */ + if (direction == CTI_TRIG_IN) + config->ctiinen[trigger_idx] = reg_value; + else + config->ctiouten[trigger_idx] = reg_value; + + /* write through if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, reg_offset, reg_value); + spin_unlock(&drvdata->spinlock); + return 0; +} + +int cti_channel_gate_op(struct device *dev, + enum cti_chan_gate_op op, + u32 channel_idx) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + u32 chan_bitmask; + u32 reg_value; + int err = 0; + + if (channel_idx >= config->nr_ctm_channels) + return -EINVAL; + + chan_bitmask = 0x1 << channel_idx; + + spin_lock(&drvdata->spinlock); + reg_value = config->ctigate; + switch (op) { + case CTI_GATE_CHAN_ENABLE: + reg_value |= chan_bitmask; + break; + + case CTI_GATE_CHAN_DISABLE: + reg_value &= ~chan_bitmask; + break; + + case CTI_GATE_CHAN_ENABLE_ALL: + reg_value = (0x1 << config->nr_ctm_channels) - 1; + break; + + case CTI_GATE_CHAN_DISABLE_ALL: + reg_value = 0x0; + break; + + default: + err = -EINVAL; + break; + } + if (err == 0) { + config->ctigate = reg_value; + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIGATE, reg_value); + } + spin_unlock(&drvdata->spinlock); + return err; +} + +int cti_channel_setop(struct device *dev, + enum cti_chan_set_op op, + u32 channel_idx) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + u32 chan_bitmask; + u32 reg_value; + u32 reg_offset; + int err = 0; + + if (channel_idx >= config->nr_ctm_channels) + return -EINVAL; + + chan_bitmask = 0x1 << channel_idx; + + spin_lock(&drvdata->spinlock); + reg_value = config->ctiappset; + switch (op) { + case CTI_CHAN_SET: + config->ctiappset |= chan_bitmask; + reg_value = config->ctiappset; + reg_offset = CTIAPPSET; + break; + + case CTI_CHAN_CLR: + config->ctiappset &= ~chan_bitmask; + reg_value = chan_bitmask; + reg_offset = CTIAPPCLEAR; + break; + + case CTI_CHAN_PULSE: + config->ctiappset &= ~chan_bitmask; + reg_value = chan_bitmask; + reg_offset = CTIAPPPULSE; + break; + + default: + err = -EINVAL; + break; + } + + if ((err == 0) && CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, reg_offset, reg_value); + spin_unlock(&drvdata->spinlock); + + return err; +} + +void cti_write_intack(struct device *dev, u32 ackval) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *config = &drvdata->config; + + spin_lock(&drvdata->spinlock); + /* write if enabled */ + if (CTI_PWR_ENA(config)) + cti_write_single_reg(drvdata, CTIINTACK, ackval); + spin_unlock(&drvdata->spinlock); +} + /** cti ect operations **/ int cti_enable(struct coresight_device *csdev, void *__unused) { @@ -432,7 +611,12 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)

/* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(dev, "%s: initialized\n", pdata->name); + if (drvdata->ctidev.cpu >= 0) { + dev_info(dev, "%s: cti-CPU%d initialized\n", pdata->name, + drvdata->ctidev.cpu); + } else { + dev_info(dev, "%s: cti-system initialized\n", pdata->name); + } cti_count++; return 0;

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index c1af6cf9c2fe..a5bf59155f62 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -153,6 +153,7 @@ struct cti_device { * @trig_out_filter: bitfield of out triggers that are blocked if filter * enabled. Typically this would be dbgreq / restart on a core CTI. * @trig_filter_enable: 1 if filtering enabled. + * @xtrig_rchan_sel: channel ID when reading set xtrig info * * cti software programmable regs: * @ctiappset: CTI Software application channel set. @@ -174,6 +175,7 @@ struct cti_config { u32 trig_out_use; u32 trig_out_filter; int trig_filter_enable; + u8 xtrig_rchan_sel; /* cti cross trig programmable regs */ u32 ctiappset; u8 ctiinout_sel; @@ -202,11 +204,51 @@ struct cti_drvdata { struct cti_config config; };

+/* + * Channel operation types. + */ +enum cti_chan_op { + CTI_CHAN_ATTACH, + CTI_CHAN_DETACH, +}; + +enum cti_trig_dir { + CTI_TRIG_IN, + CTI_TRIG_OUT, +}; + +enum cti_chan_gate_op { + CTI_GATE_CHAN_ENABLE, + CTI_GATE_CHAN_DISABLE, + CTI_GATE_CHAN_ENABLE_ALL, + CTI_GATE_CHAN_DISABLE_ALL, +}; + +enum cti_chan_set_op { + CTI_CHAN_SET, + CTI_CHAN_CLR, + CTI_CHAN_PULSE, +}; + /* private cti driver fns & vars */ extern const struct attribute_group *coresight_cti_groups[]; + int cti_add_default_connection(struct cti_drvdata *drvdata); int cti_enable(struct coresight_device *csdev, void *__unused); int cti_disable(struct coresight_device *csdev, void *__unused); +void cti_write_all_hw_regs(struct cti_drvdata *drvdata); +void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); +int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, + enum cti_trig_dir direction, u32 channel_idx, + u32 trigger_idx); +int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op, + u32 channel_idx); +int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, + u32 channel_idx); +void cti_write_intack(struct device *dev, u32 ackval); + +/* cti powered and enabled */ +#define CTI_PWR_ENA(p_cfg) (p_cfg->hw_enabled && p_cfg->hw_powered)

#ifdef CONFIG_OF extern int of_cti_get_hw_data(struct device *dev, diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 8e9e5b6ad866..9b497e2f8725 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -23,10 +23,12 @@ #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 #define CORESIGHT_AUTHSTATUS 0xfb8 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_DEVID 0xfc8 #define CORESIGHT_DEVTYPE 0xfcc

+ /* * Coresight device CLAIM protocol. * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.

Adds support for CTIs that are implementation defined at design time, and not constrained by v8 architecture.

These CTIs have no standard connection setup, all the settings have to be defined in the device tree files. The patch creates a set of connections and trigger signals based on the information provided,

Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/hwtracing/coresight/coresight-cti.h | 1 + .../hwtracing/coresight/of_coresight-cti.c | 191 +++++++++++++++++- 2 files changed, 191 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index df40ca2d9548..7342f998f4c5 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -239,6 +239,7 @@ int cti_add_connection_entry(struct cti_drvdata *drvdata, struct cti_trig_grp *out_info, struct coresight_device *csdev, const char *assoc_dev_name); +void cti_free_conn_info(struct cti_drvdata *drvdata); int cti_enable(struct coresight_device *csdev, void *__unused); int cti_disable(struct coresight_device *csdev, void *__unused); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/of_coresight-cti.c b/drivers/hwtracing/coresight/of_coresight-cti.c index ee9a5906dc37..486fa99813ae 100644 --- a/drivers/hwtracing/coresight/of_coresight-cti.c +++ b/drivers/hwtracing/coresight/of_coresight-cti.c @@ -23,10 +23,19 @@ #define NR_V8PE_OUT_SIGS 3 #define NR_V8ETM_INOUT_SIGS 4

+/* CTI device tree trigger connection node keyword */ +#define CTI_DT_CONNS "trig-conns" + /* CTI device tree connection property keywords */ #define CTI_DT_V8ARCH "arm,cti-v8-arch" #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc" #define CTI_DT_CTM_ID "arm,cti-ctm-id" +#define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs" +#define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs" +#define CTI_DT_TRIGIN_TYPES "arm,trig-in-types" +#define CTI_DT_TRIGOUT_TYPES "arm,trig-out-types" +#define CTI_DT_FILTER_OUT_SIGS "arm,trig-filters" +#define CTI_DT_CONN_NAME "arm,trig-conn-name"

#ifdef CONFIG_OF

@@ -210,6 +219,181 @@ static int of_cti_create_v8_connections(struct cti_drvdata *drvdata, return -ENOMEM; }

+static int of_cti_read_trig_group(struct cti_trig_grp **trig_grp_ptr, + struct device_node *np, + const char *grp_name, + int max_trigs) +{ + int items, err = 0; + u32 value, pidx; + struct cti_trig_grp *grp; + + grp = kzalloc(sizeof(struct cti_trig_grp), GFP_KERNEL); + if (!grp) + return -ENOMEM; + *trig_grp_ptr = grp; + + items = of_property_count_elems_of_size(np, grp_name, 4); + /* if the property doesn't exist or has no values, then return + * an empty connection group + */ + if (items < 0) + return 0; + + if (items > max_trigs) + return -EINVAL; + + /* set the number of signals and usage mask */ + for (pidx = 0; pidx < items; pidx++) { + err = of_property_read_u32_index(np, grp_name, pidx, &value); + if (err) + return err; + grp->nr_sigs++; + grp->used_mask |= (0x1 << value); + } + return 0; +} + +static int of_cti_read_trig_types(struct cti_trig_grp *trig_grp_ptr, + struct device_node *np, + const char *type_name) +{ + int items, used = 0, err = 0, nr_sigs; + u32 value, i; + + /* allocate an array according to number of signals in connection */ + nr_sigs = trig_grp_ptr->nr_sigs; + if (!nr_sigs) + return 0; + trig_grp_ptr->sig_types = kzalloc(sizeof(int) * nr_sigs, GFP_KERNEL); + if (!trig_grp_ptr->sig_types) + return -ENOMEM; + + /* see if any types have been included in the device description */ + items = of_property_count_elems_of_size(np, type_name, 4); + + /* + * Match type id to signal index, + * too few - default to genio, + * too many - ignore excess. + */ + for (i = 0; i < nr_sigs; i++) { + if (used < items) { + err = of_property_read_u32_index(np, type_name, + i, &value); + if (!err) + trig_grp_ptr->sig_types[i] = value; + else + trig_grp_ptr->sig_types[i] = CTITRIG_GEN_IO; + used++; + } + else + trig_grp_ptr->sig_types[i] = CTITRIG_GEN_IO; + } + return 0; +} + +static void of_cti_free_trig_grp(struct cti_trig_grp *grp) +{ + if (grp) { + kfree(grp->sig_types); + kfree(grp); + } +} + +static int of_cti_create_connection(struct device *dev, + struct device_node *np, + struct cti_drvdata *drvdata) +{ + struct cti_trig_grp *in = 0, *out = 0, *filter = 0; + int cpuid = -1, err = 0, trig_max = drvdata->config.nr_trig_max; + struct device_node *cs_np; + struct coresight_device *csdev = NULL; + const char *assoc_name = "unknown"; + char cpu_name_str[16]; + + /* look for the signals properties. */ + err = of_cti_read_trig_group(&in, np, CTI_DT_TRIGIN_SIGS, trig_max); + if (err) + goto of_create_con_err; + + err = of_cti_read_trig_types(in, np, CTI_DT_TRIGIN_TYPES); + if (err) + goto of_create_con_err; + + err = of_cti_read_trig_group(&out, np, CTI_DT_TRIGOUT_SIGS, trig_max); + if (err) + goto of_create_con_err; + + err = of_cti_read_trig_types(out, np, CTI_DT_TRIGOUT_TYPES); + if (err) + goto of_create_con_err; + + err = of_cti_read_trig_group(&filter, np, CTI_DT_FILTER_OUT_SIGS, + trig_max); + if (err) + goto of_create_con_err; + + /* read the connection name if set - may be overridden by later */ + of_property_read_string(np, CTI_DT_CONN_NAME, &assoc_name); + + /* associated cpu ? */ + cpuid = of_cti_get_cpu(np); + if (cpuid >= 0) { + drvdata->ctidev.cpu = cpuid; + scnprintf(cpu_name_str, 16, "cpu%d", cpuid); + assoc_name = cpu_name_str; + } else { + /* associated device ? */ + cs_np = of_parse_phandle(np, CTI_DT_CSDEV_ASSOC, 0); + if (cs_np) { + csdev = of_cti_get_assoc_cs_dev_by_node(cs_np); + if (csdev) /* use device name if csdev found */ + assoc_name = dev_name(&csdev->dev); + else /* otherwise node name for later association */ + assoc_name = cs_np->full_name; + of_node_put(cs_np); + } + } + /* set up a connection */ + err = cti_add_connection_entry(drvdata, in, out, csdev, assoc_name); + if (err) + goto of_create_con_err; + + /* note any filter info */ + drvdata->config.trig_out_filter |= filter->used_mask; + kfree(filter); + return err; + +of_create_con_err: + of_cti_free_trig_grp(in); + of_cti_free_trig_grp(out); + of_cti_free_trig_grp(filter); + return err; +} + +static int of_cti_create_impdef_connections(struct device *dev, + struct device_node *np, + struct cti_drvdata *drvdata) +{ + int rc = 0; + struct device_node *nc = NULL; + + for_each_child_of_node(np, nc) { + if (of_node_cmp(nc->name, CTI_DT_CONNS) != 0) + continue; + rc = of_cti_create_connection(dev, nc, drvdata); + if (rc != 0) + goto of_cti_impdef_create_err; + } + return rc; + +of_cti_impdef_create_err: + /* last create should have freed its mem - unpick previous */ + cti_free_conn_info(drvdata); + return rc; +} + /* get the hardware configuration & connection data. */ int of_cti_get_hw_data(struct device *dev, struct device_node *np, @@ -221,9 +405,14 @@ int of_cti_get_hw_data(struct device *dev, /* get any CTM ID - defaults to 0 */ of_property_read_u32(np, CTI_DT_CTM_ID, &cti_dev->ctm_id);

- /* check for a v8 architectural CTI device */ + /* + * Check for a v8 architectural CTI device, + * otherwise implementation defined. + */ if (of_property_read_bool(np, CTI_DT_V8ARCH)) rc = of_cti_create_v8_connections(drvdata, np); + else + rc = of_cti_create_impdef_connections(dev, np, drvdata);

/* if no connections, just add a single default based on max IN-OUT */ if (!rc && (cti_dev->nr_trig_con == 0))

Dynamically adds sysfs attributes for all connections defined in the CTI.

Each connection has _name, _trgin_type, _trgout_type, _trgin_sig and _trgout_sig, preceded by a connection index (e.g. 0_name is the name of connection 0).

Additionally each device has a nr_cons and trigout_filtered parameter. This allows clients to explore the connection and trigger signal details without needing to refer to device tree or specification of the device.

Standardised type information is provided for certain common functions - e.g. snk_full for a trigger from a sink indicating full. Otherwise type defaults to genio.

Signed-off-by: Mike Leach mike.leach@linaro.org --- .../hwtracing/coresight/coresight-cti-sysfs.c | 338 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.c | 11 + drivers/hwtracing/coresight/coresight-cti.h | 4 + 3 files changed, 353 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index ff8dad02a779..e4b23e291114 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -883,6 +883,343 @@ static struct attribute *coresight_cti_channel_attrs[] = { NULL, };

+/* Create the connections group attrs dynamically */ + +/* group is static - .attrs will be built dynamically */ +static struct attribute_group coresight_cti_conns_group = { + .name = "connections", +}; + +/* + *Each connection has dynamic name, trigin/out sigs/types attrs, + * + each device has static nr conns + filter attr + */ + +static ssize_t trigout_filtered_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *cfg = &drvdata->config; + int b_sz = PAGE_SIZE; + u32 sig_mask; + int sig_idx, used = 0, nr_trig_max = cfg->nr_trig_max; + + if (cfg->trig_out_filter) { + sig_mask = 0x1; + for (sig_idx = 0; sig_idx < nr_trig_max; sig_idx++) { + if (sig_mask & cfg->trig_out_filter) { + used += scnprintf(buf+used, b_sz-used, "%d ", + sig_idx); + } + sig_mask <<= 1; + } + used += scnprintf(buf+used, b_sz-used, "\n"); + } else + used += scnprintf(buf, b_sz, "none\n"); + return used; +} +static DEVICE_ATTR_RO(trigout_filtered); + +static ssize_t nr_cons_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.nr_trig_con); +} +static DEVICE_ATTR_RO(nr_cons); + +/* static attrs - 2 + null terminator */ +#define CTI_SYSFS_CONS_ST_ATTR 3 +/* dynamic attr - per connection */ +#define CTI_SYSFS_CONS_DYN_ATTR 5 + +static ssize_t con_name_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr; + struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; + + return scnprintf(buf, PAGE_SIZE, "%s\n", con->con_dev_name); +} + +static ssize_t trigin_sig_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr; + struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *cfg = &drvdata->config; + + u32 sig_mask; + int sig_idx, used = 0, b_sz = PAGE_SIZE; + + sig_mask = 0x1; + for (sig_idx = 0; sig_idx < cfg->nr_trig_max; sig_idx++) { + if (sig_mask & con->con_in->used_mask) { + used += scnprintf(buf+used, b_sz-used, "%d ", + sig_idx); + } + sig_mask <<= 1; + } + used += scnprintf(buf+used, b_sz-used, "\n"); + return used; +} + +static ssize_t trigout_sig_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr; + struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_config *cfg = &drvdata->config; + + u32 sig_mask; + int sig_idx, used = 0, b_sz = PAGE_SIZE; + + sig_mask = 0x1; + for (sig_idx = 0; sig_idx < cfg->nr_trig_max; sig_idx++) { + if (sig_mask & con->con_out->used_mask) { + used += scnprintf(buf+used, b_sz-used, "%d ", + sig_idx); + } + sig_mask <<= 1; + } + used += scnprintf(buf+used, b_sz-used, "\n"); + return used; +} + +/* convert a sig type id to a name */ +static const char * +cti_sig_type_name(struct cti_trig_con *con, int used_count, bool in) +{ + static const char * const sig_type_names[] = { + "genio", "intreq", "intack", "haltreq", "restartreq", + "pe_edbgreq", "pe_dbgrestart", "pe_ctiirq", "pe_pmuirq", + "pe_dbgtrigger", "etm_extout", "etm_extin", "snk_full", + "snk_acqcomp", "snk_flushcomp", "snk_flushin", "snk_trigin", + "stm_asyncout", "stm_tout_spte", "stm_tout_sw", "stm_tout_hete", + "stm_hwevent", "ela_tstart", "ela_tstop", "ela_dbgreq", + }; + int idx = 0; + struct cti_trig_grp *grp = in ? con->con_in : con->con_out; + + if (grp->sig_types) { + if (used_count < grp->nr_sigs) + idx = grp->sig_types[used_count]; + } + return sig_type_names[idx]; +} + +static ssize_t trigin_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr; + struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; + + int sig_idx, used = 0, b_sz = PAGE_SIZE; + const char *name; + + for (sig_idx = 0; sig_idx < con->con_in->nr_sigs; sig_idx++) { + name = cti_sig_type_name(con, sig_idx, true); + used += scnprintf(buf+used, b_sz-used, "%s ", name); + } + used += scnprintf(buf+used, b_sz-used, "\n"); + return used; +} + +static ssize_t trigout_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr; + struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; + + int sig_idx, used = 0, b_sz = PAGE_SIZE; + const char *name; + + for (sig_idx = 0; sig_idx < con->con_out->nr_sigs; sig_idx++) { + name = cti_sig_type_name(con, sig_idx, false); + used += scnprintf(buf+used, b_sz-used, "%s ", name); + } + used += scnprintf(buf+used, b_sz-used, "\n"); + return used; +} + +typedef ssize_t (*p_show_fn)(struct device *dev, struct device_attribute *attr, + char *buf); + +enum cti_conn_attr_type { + CTI_CON_ATTR_NAME, + CTI_CON_ATTR_TRIGIN_SIG, + CTI_CON_ATTR_TRIGOUT_SIG, + CTI_CON_ATTR_TRIGIN_TYPES, + CTI_CON_ATTR_TRIGOUT_TYPES +}; + +static p_show_fn show_fns[] = { + con_name_show, + trigin_sig_show, + trigout_sig_show, + trigin_type_show, + trigout_type_show, +}; + +static const char * const base_names[] = { + "_name", + "_trgin_sig", + "_trgout_sig", + "_trgin_type", + "_trgout_type", +}; + +struct dev_ext_attribute * +cti_create_con_sysfs_attr(int con_idx, enum cti_conn_attr_type attr_type) +{ + struct dev_ext_attribute *dev_ext_attr = 0; + char *name = 0; + + dev_ext_attr = kzalloc(sizeof(struct dev_ext_attribute), GFP_KERNEL); + if (dev_ext_attr) { + name = kzalloc(sizeof(char) * 16, GFP_KERNEL); + if (name) { + /* fill out the underlying attribute struct */ + sprintf(name, "%d%s", con_idx, base_names[attr_type]); + dev_ext_attr->attr.attr.name = name; + dev_ext_attr->attr.attr.mode = 0444; + + /* now the device_attribute struct */ + dev_ext_attr->attr.show = show_fns[attr_type]; + } else { + kfree(dev_ext_attr); + dev_ext_attr = 0; + } + } + return dev_ext_attr; +} + +int cti_create_con_attr_set(int con_idx, int *next_attr_idx, + struct cti_device *ctidev, + struct cti_trig_con *con) +{ + struct dev_ext_attribute *dev_ext_attr; + int attr_idx = *next_attr_idx; + + dev_ext_attr = cti_create_con_sysfs_attr(con_idx, CTI_CON_ATTR_NAME); + if (!dev_ext_attr) + goto create_con_attr_err; + dev_ext_attr->var = con; + ctidev->con_attrs[attr_idx++] = dev_ext_attr; + + if (con->con_in->nr_sigs > 0) { + dev_ext_attr = + cti_create_con_sysfs_attr(con_idx, + CTI_CON_ATTR_TRIGIN_SIG); + if (!dev_ext_attr) + goto create_con_attr_err; + dev_ext_attr->var = con; + ctidev->con_attrs[attr_idx++] = dev_ext_attr; + + dev_ext_attr = + cti_create_con_sysfs_attr(con_idx, + CTI_CON_ATTR_TRIGIN_TYPES); + if (!dev_ext_attr) + goto create_con_attr_err; + dev_ext_attr->var = con; + ctidev->con_attrs[attr_idx++] = dev_ext_attr; + + } + + if (con->con_in->nr_sigs > 0) { + + dev_ext_attr = + cti_create_con_sysfs_attr(con_idx, + CTI_CON_ATTR_TRIGOUT_SIG); + if (!dev_ext_attr) + goto create_con_attr_err; + dev_ext_attr->var = con; + ctidev->con_attrs[attr_idx++] = dev_ext_attr; + + dev_ext_attr = + cti_create_con_sysfs_attr(con_idx, + CTI_CON_ATTR_TRIGOUT_TYPES); + if (!dev_ext_attr) + goto create_con_attr_err; + dev_ext_attr->var = con; + ctidev->con_attrs[attr_idx++] = dev_ext_attr; + } + *next_attr_idx = attr_idx; + return 0; + +create_con_attr_err: + cti_destroy_cons_sysfs(ctidev); + return -ENOMEM; +} + +int cti_create_cons_sysfs(struct cti_drvdata *drvdata) +{ + struct cti_device *ctidev = &drvdata->ctidev; + int err = 0, n_attrs = 0, con_idx = 0; + int next_attr_idx = CTI_SYSFS_CONS_ST_ATTR - 1; + struct cti_trig_con *tc; + + n_attrs = CTI_SYSFS_CONS_ST_ATTR + + (CTI_SYSFS_CONS_DYN_ATTR * ctidev->nr_trig_con); + ctidev->con_attrs = + kcalloc(n_attrs, sizeof(struct dev_ext_attribute *), + GFP_KERNEL); + if (ctidev->con_attrs != 0) { + ctidev->con_attrs[0] = (struct dev_ext_attribute *) + &dev_attr_trigout_filtered.attr; + ctidev->con_attrs[1] = (struct dev_ext_attribute *) + &dev_attr_nr_cons.attr; + + /* add dynamic set for each connection */ + list_for_each_entry(tc, &ctidev->trig_cons, node) { + err = cti_create_con_attr_set(con_idx++, + &next_attr_idx, + ctidev, + tc); + /* if create con fails it will free all prior cons */ + if (err) + return err; + } + coresight_cti_conns_group.attrs = + (struct attribute **)ctidev->con_attrs; + } else + err = -ENOMEM; + return err; +} + +void cti_destroy_cons_sysfs(struct cti_device *ctidev) +{ + int n_attrs = CTI_SYSFS_CONS_ST_ATTR + + (CTI_SYSFS_CONS_DYN_ATTR * ctidev->nr_trig_con); + int dyn_idx = CTI_SYSFS_CONS_ST_ATTR - 1; + bool eol = false; + struct dev_ext_attribute *dev_ext_attr = 0; + + if (ctidev->con_attrs) { + while (!eol && (dyn_idx < n_attrs)) { + dev_ext_attr = ctidev->con_attrs[dyn_idx]; + if (dev_ext_attr) { + kfree(dev_ext_attr->attr.attr.name); + kfree(dev_ext_attr); + } else + eol = true; + dyn_idx++; + } + kfree(ctidev->con_attrs); + ctidev->con_attrs = 0; + } +} + /* attribute and group sysfs tables. */ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, @@ -908,5 +1245,6 @@ const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_mgmt_group, &coresight_cti_regs_group, &coresight_cti_channels_group, + &coresight_cti_conns_group, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 6d452ca3725c..e0192fd50804 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -671,6 +671,14 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* setup cpu related CTI devices, otherwise assume powered */ drvdata->config.hw_powered = true;

+ /* create dynamic attributes for connections */ + ret = cti_create_cons_sysfs(drvdata); + if (ret) { + pr_err("%s: create dynamic sysfs entries failed\n", + pdata->name); + goto err_out; + } + /* set up coresight component description */ cti_desc.pdata = pdata; cti_desc.type = CORESIGHT_DEV_TYPE_ECT; @@ -746,6 +754,9 @@ void cti_device_release(struct device *dev) if (drvdata->ctidev.cpu >= 0) cti_cpu_drv[drvdata->ctidev.cpu] = 0;

+ /* clear the dynamic sysfs associate with connections */ + cti_destroy_cons_sysfs(&drvdata->ctidev); + /* clear the connection list items */ cti_free_conn_info(drvdata);

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 7342f998f4c5..2a3557bfcd16 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -125,6 +125,7 @@ struct cti_trig_con { * assumed there is a single CTM per SoC, ID 0). * @trig_cons: list of connections to this device. * @cpu: CPU ID if associated with CPU, -1 otherwise. + * @con_attrs: Dymanic sysfs attributes created to display connection info. * */ struct cti_device { @@ -132,6 +133,7 @@ struct cti_device { u32 ctm_id; struct list_head trig_cons; int cpu; + struct dev_ext_attribute **con_attrs; };

/** @@ -252,6 +254,8 @@ int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op, int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, u32 channel_idx); void cti_write_intack(struct device *dev, u32 ackval); +int cti_create_cons_sysfs(struct cti_drvdata *drvdata); +void cti_destroy_cons_sysfs(struct cti_device *ctidev);

/* cti powered and enabled */ #define CTI_PWR_ENA(p_cfg) (p_cfg->hw_enabled && p_cfg->hw_powered)

Adds new .txt file describing the bindings required to define CTI in the device trees.

Signed-off-by: Mike Leach mike.leach@linaro.org --- .../bindings/arm/coresight-ect-cti.txt | 203 ++++++++++++++++++ .../devicetree/bindings/arm/coresight.txt | 7 + 2 files changed, 210 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-ect-cti.txt

diff --git a/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt new file mode 100644 index 000000000000..ba95c0002ccc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt @@ -0,0 +1,203 @@ +*CoreSight Embedded Cross Trigger Components + +The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected +to one or more CoreSight components and/or a CPU, with CTIs interconnected in +a star topology via the CTM (which is not programmable). The ECT components +are not part of the trace generation data path and are thus not part of the +CoreSight graph described above. + +The CTI component properties define the connections between the individual CTI +and the components it is directly connected to, consisting of input and output +hardware trigger signals. CTIs can have a maximum number of input and output +hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The number is +defined at design time, the maximum of each defined in the DEVID register. +Note that some hardware trigger signals can be connected to non-CoreSight +components (e.g. UART etc) depending on hardware implementation. + +CTIs are interconnect in a star topology via the CTM, using a number of +programmable channels usually 4, but again implementation defined and described +in the DEVID register. The star topology is not required to be described in the +bindings as the actual connections are software programmable. + +In general the connections between CTI and components via the trigger signals +are implementation defined, other than when v8 core and ETM is present. The v8 +architecture then defines the required signal connections between core and CTI, +and ETM and CTI, if the ETM if present. + +Certain triggers between CoreSight devices and the CTI have specific types / +usages. These can be defined along with the signal indexes with the constants +defined in <dt-bindings/arm/coresight-cti-dt.h> + +For example a CTI connected to a core will usually have a DBGREQ signal. This +is defined in the binding as type PE_EDBGREQ. These types will appear in an +optional array alongside the signal indexes. Omitting types will default all +signals to GEN_IO. + +The minimum required binding for a CTI consist of the only the required +properties above. + +e.g. + + /* sys cti 0 - connects to STM, ETF0 (core trace) TPIU and ETR */ + cti0: cti@20020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20020000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + }; + + +This will result in the driver using the DEVID register to set the +input and output triggers and channels in use. Any user / client +application will require additional information on the connections +between the CTI and other components for correct operation. + +Where information is immediately available for the component connections then +a series of trigger connection nodes can be defined (trig-conns). + +These connections explicitly define the input and output triggers between the +CTI and a connected component. Connections to an cpu use the standard cpu +property, connections to other CoreSight components use the arm,cs-dev-assoc +property. + +Where the signals are connected to a device that is not coresight device then +no association is registered. + +cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + trig-conns@0 { + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT>; + arm,trig-out-sigs = <4 5 6 7>; + arm,trig-out-types = <ETM_EXTIN ETM_EXTIN ETM_EXTIN ETM_EXTIN>; + arm,cs-dev-assoc = <&etm0>; + }; + + trig-conns@1 { + cpu = <&CPU0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<PE_DBGTRIGGER PE_PMUIRQ>; + arm,trig-out-sigs=<0 1 2 >; + arm,trig-out-types=<PE_EDBGREQ PE_DBGRESTART PE_CTIIRQ>; + arm,trig-filters=<0>; + }; + +}; + +Note that where input and output triggers are defined as above, then the driver +will limit the channel connection sysfs API to using only the defined signals. + +The arm,trig-filters property blocks output signals that could cause system +issues is set - such as the dbgreq signal into a CPU. The filtering is +enabled by default, but can be disabled at runtime. + +Finally, a CTI that is an architecturally defined v8 CTI connected to a cpu +and optional ETM may be declared as: + +cti@859000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; +}; + +The arm,cti-v8-arch property declares this as a v8 CTI, the cpu property must +be present, and a single arm,cs-dev-assoc may be present to define an attached +ETM. No additional trig-conns nodes are permitted. The driver will build a +connection model according to architectural requirements. This will include +a filter on the CPU debreq signal as described above. + +All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by + a CTM. On these systems a CTM index is declared to associate CTI devices that + are interconnected via the CTM. + + e.g. + arm,ctm-ctm-id=<2> + +CTI devices with the same CTM ID are considered connected by the CTM. If this +parameter is absent then all CTIs are considered interconnected by the same +CTM. + +*Summary of CTI required properties: + + * compatible : should be "arm,coresight-cti"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + + * reg: physical base address and length of the register + set(s) of the component. + + * clocks: the clocks associated to this component. + + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. + +*Summary of CTI optional properties: + + * trig-conns : defines a connection node between CTI and a component. + Component may be a CPU, CoreSight device, any other hardware device + or simple external IO lines. + + *arm,trig-in-sigs: List of CTI trigger in signals in use by a + trig-conns node. Only valid as property of trig-conns node. + + *arm,trig-in-types: List of types for the CTI trigger in signals. + Types in this array match to the corresponding signal in the + arm,trig-in-sigs array. If the -types array is smaller, or omitted + completely, then the types will default to GEN_IO. + + *arm,trig-out-sigs: List of CTI trigger out signals in use by a + trig-conns node. Only valid as property of trig-conns node. + + *arm,trig-out-types: List of types for the CTI trigger out signals. + Types in this array match to the corresponding signal in the + arm,trig-out-sigs array. If the -types array is smaller, or omitted + completely, then the types will default to GEN_IO. + + *arm-trig-filters: List of CTI trigger out signals that will be + blocked from becoming active, unless filtering is disabled on the + driver. Only valid as property of trig-conns node. + + *arm,cti-v8-arch: Declares this CTI device as a v8 architecturally + defined device. Use in CTI base node only, no additional trig-conns + nodes permitted if this is declared. + + *cpu : defines a phandle reference to an associated CPU. Use in + trig-conns node, or in CTI base node when arm,cti-v8-arch present. + + *arm,cs-dev-assoc: defines a phandle reference to an associated + CoreSight trace device. When the associated trace device is enabled, + then the respective CTI will be enabled. Use in a trig-conns node, + or in CTI base node when arm,cti-v8-arch present. If the associated + device has not been registered then the node name will be stored as + the connection name for later resolution. If the associated device is + not a CoreSight device or not registered then the node name will + remain the connection name and automatic enabling will not occur. + + *arm,trig-conn-name: defines a connection name that will be displayed, + if not overridden by the name of associated device from + arm,cs-dev-assoc or the CPU. Only valid as property of trig-conns node. + Principle use for CTI that are connected to non-coresight devices, + or external IO. + + *arm,ctm-ctm-id: Defines the interconnecting CTM for this device. + Use in CTI base node. diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index f8aff65ab921..2013757b1f93 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -42,6 +42,10 @@ its hardware characteristcs. - Coresight Address Translation Unit (CATU) "arm,coresight-catu", "arm,primecell";

+ - Coresight Cross Trigger Interface (CTI): + "arm,coresight-cti", "arm,primecell"; + See coresight-ect-cti.txt for full CTI definitions. + * reg: physical base address and length of the register set(s) of the component.

@@ -64,6 +68,9 @@ its hardware characteristcs. * reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg".

+* Required properties for Coresight Cross Trigger Interface (CTI) + See coresight-ect-cti.txt for full CTI definitions. + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators:

Signed-off-by: Mike Leach mike.leach@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 102 +++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0803ca8c02da..86d0b185a207 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -16,6 +16,7 @@ #include <dt-bindings/reset/qcom,gcc-msm8916.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/arm/coresight-cti-dt.h>

/ { interrupt-parent = <&intc>; @@ -1352,7 +1353,7 @@ cpu = <&CPU3>; };

- etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>;

@@ -1370,7 +1371,7 @@ }; };

- etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>;

@@ -1388,7 +1389,7 @@ }; };

- etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>;

@@ -1406,7 +1407,7 @@ }; };

- etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>;

@@ -1424,6 +1425,99 @@ }; };

+ /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + /* v8 cpu the hard way... */ + trig-conns@0 { +/* #address-cells = <1>; + #size-cells = <0>; + reg = <0>;*/ + cpu = <&CPU2>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<PE_DBGTRIGGER PE_PMUIRQ>; + arm,trig-out-sigs=<0 1 2 >; + arm,trig-out-types=<PE_EDBGREQ PE_DBGRESTART PE_CTIIRQ>; + arm,trig-filters=<0>; + }; + trig-conns@1 { + /* reg = <1>; */ + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT>; + arm,trig-out-sigs = <4 5 6 7>; + arm,trig-out-types = <ETM_EXTIN ETM_EXTIN ETM_EXTIN ETM_EXTIN>; + arm,cs-dev-assoc = <&etm2>; + }; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + arm,cti-v8-arch; + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;

Add section in coresight.txt explaining operation and use of CTI devices in CoreSight.

Signed-off-by: Mike Leach mike.leach@linaro.org --- Documentation/trace/coresight.txt | 139 ++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+)

diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight.txt index efbc832146e7..d3e1147b5156 100644 --- a/Documentation/trace/coresight.txt +++ b/Documentation/trace/coresight.txt @@ -425,6 +425,145 @@ root@genericarmv8:~#

Details on how to use the generic STM API can be found here [2].

+CoreSight Embedded Cross Trigger (CTI & CTM). +--------------------------------------------- + +The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes +individual input and output hardware signals from devices and interconnects +them via the Cross Trigger Matrix (CTM) to other devices, in order to propogate +events between devices. + +e.g. + + 0000000 in_trigs ::::::: + 0 C 0----------->: : +======>(other CTI channel IO) + 0 P 0<-----------: : v + 0 U 0 out_trigs : : Channels ***** ::::::: + 0000000 : CTI :<=========>*CTM*<====>: CTI :---+ + ####### in_trigs : : (id 0-3) ***** ::::::: v + # ETM #----------->: : ^ ####### + # #<-----------: : +---# ETR # + ####### out_trigs ::::::: ####### + +The CTI driver enables the programming of the CTI to attach triggers to +channels. When an input trigger becomes active, the attached channel will +become active. Any output trigger also attached to that channel will also +become active. The active channel is propogated to other CTIs via the CTM +affecting output triggers there, unless filtered by the CTI channel gate. + +It is also possible to activate a channel using system software. + +The CTIs are registered by the system to be associated with CPUs and/or other +CoreSight devices on the trace data path. When these devices are enabled then +the attached CTIs will also be enabled. By default/on power up the CTIs have +no programmed trigger/channel attachments, so will not affect the system +until explicitly programmed. + +The hardware trigger connections between CTIs and devices is implementation +defined, unless the CPU/ETM combination is a v8 architecture, in which case +the connections have an architecturally defined standard layout. + +The hardware trigger signals can also be connected to non-CoreSight devices +(e.g. UART), or be propogated off chip as hardware IO lines. + +All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by + a CTM. On these systems a CTM index is declared to associate CTI devices that + are interconnected via the CTM. + +The CTI devices appear on the existing coresight bus alongside the other +CoreSight devices. + +# ls /sys/bus/coresight/devices/858000.cti +channels connections ctmid enable mgmt power regs subsystem uevent + +Key items are: +* enable: enables the CTI. +* ctmid : associated CTM - only relevant if system has multiple CTI+CTM clusters +that are not interconnected. + + +*connections: sub-dir containing the interconnection information for this CTI. +*channels: sub-dir containing the channel API - CTI main programming interface. +*regs: sub-dir giving access to the raw programmable CTI regs. +*mgmt: sub-dir for the standard CoreSight management registers. + +** Connections: This contains a list of read only data describing the devices +connected to this CTI, and the individual trigger signals to and from the +devices: +./b5b000.cti/connections# ls +0_name 0_trgin_type 0_trgout_type 1_trgin_sig 1_trgout_sig nr_cons +0_trgin_sig 0_trgout_sig 1_name 1_trgin_type 1_trgout_type trigout_filtered + +* nr_cons - number of connections +* trigout_filtered - trigger out signals that are prevented from being set if +filtering is enabled. Prevents accidental edbgreq signals stopping a core. + +Each connection has a set of parameters prefixed with the connection index. +Thus 0_name will show the name of connection 0. +* N_name : name of connection +* N_trgin_sig : input trigger signal indexes used in this connection. +* N_trgin_type : functional types for in signals. +* N_trgout_sig : output trigger signals for this connection. +* N_trgout_type : functional types for out signals. + +e.g. +.../85b000.cti/connections# cat 0_name +cpu3 +.../85b000.cti/connections# cat 0_trgin_sig +0 1 +.../85b000.cti/connections# cat 0_trgin_type +pe_dbgtrigger pe_pmuirq + +If a connection has zero signals in either the in or out triggers then those +parameters will be omitted from the connections sub-dir. + + +** Channels API : This provides an easy way to attach triggers to channels, +without needing the multiple register operations that are required if +manipluating the 'regs' sub-dir elements directly. + +# ls /sys/bus/coresight/devices/859000.cti/channels/ +chan_clear gate_disable list_xtrigs trigin_attach trigout_detach +chan_pulse gate_enable reset_xtrigs trigin_detach +chan_set list_chan_inuse trig_filter_enable trigout_attach + +Most access to these elements take the form: +echo <chan> [<trigger>] > /<device_path>/<operation> +where the optional <trigger> is only needed for trigXX_at|detach operations. + +e.g. +echo 0 1 > /sys/bus/coresight/devices/859000.cti/channels/trigin_attach +attach trig_in(1) to channel(0). +echo 0 > /sys/bus/coresight/devices/859000.cti/channels/chan_set +activate channel(0) + +*gate_enable, gate_disable operations set the CTI gate to propogate +(enable) to other devices. These operation can take a channel number or 'all' +to operate on all channels. CTI gate is enabled by default at power up. + +*list_gate_enable: show the current channels enabled through the gate. +*list_inuse: show the current channels attached to any signal +*list_free: show channels with no attached signals +*show_chan_sel: select the channel for the show_chan_xtrigs operation. +*show_chan_xtrigs: show the cross triggers programmed for the selected channel. + +.../85b000.cti/channels# echo 0 1 > trigin_attach +.../85b000.cti/channels# cat list_free +1 2 3 +.../85b000.cti/channels# cat list_inuse +0 +.../85b000.cti/channels# echo 0 > show_chan_sel +.../85b000.cti/channels# cat show_chan_xtrigs +IN: 1 OUT: + +*trig_filter_enable: defaults to enabled, disable to allow potentially +dangerous output signals to be set. + +*reset_xtrigs: clear all channel / trigger programming - reset device hardware +to default state. + [1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-stm [2]. Documentation/trace/stm.rst [3]. https://github.com/Linaro/perf-opencsd

On Wed, May 01, 2019 at 09:49:33AM +0100, Mike Leach wrote:

This introduces a baseline CTI driver and associated configuration files.

Driver will probe for the device on the AMBA bus, and load the CTI driver on CoreSight ID match to CTI IDs in tables.

Initial sysfs support for enable / disable provided.

Default CTI interconnection data is generated based on hardware register signal counts, with no additional connection information

Signed-off-by: Mike Leach mike.leach@linaro.org

drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/Makefile | 4 + .../hwtracing/coresight/coresight-cti-sysfs.c | 97 ++++ drivers/hwtracing/coresight/coresight-cti.c | 522 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.h | 228 ++++++++ drivers/hwtracing/coresight/coresight-priv.h | 7 + drivers/hwtracing/coresight/coresight.c | 8 + .../hwtracing/coresight/of_coresight-cti.c | 81 +++ include/linux/coresight.h | 26 + 9 files changed, 986 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-cti-sysfs.c create mode 100644 drivers/hwtracing/coresight/coresight-cti.c create mode 100644 drivers/hwtracing/coresight/coresight-cti.h create mode 100644 drivers/hwtracing/coresight/of_coresight-cti.c

Compiling this patch gave me the following compilation warning:

/home/mpoirier/work/coresight/kernel-maint/drivers/hwtracing/coresight/coresight-cti-sysfs.c: In function ‘enable_show’: /home/mpoirier/work/coresight/kernel-maint/drivers/hwtracing/coresight/coresight-cti-sysfs.c:52:19: warning: comparison of constant ‘0’ with boolean expression is always true [-Wbool-compare] } else if (cpuid >= 0) {

mpoirier@xps15:~/work/coresight/kernel-maint$ aarch64-linux-gnu-gcc --version aarch64-linux-gnu-gcc (Linaro GCC 7.2-2017.11) 7.2.1 20171011 Copyright (C) 2017 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Checkpatch.pl also found problems with several patches and I had to rebase your work on the latest coresight-next tree.

diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ad34380cac49..9f1cac64f357 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -114,4 +114,17 @@ config CORESIGHT_CPU_DEBUG properly, please refer Documentation/trace/coresight-cpu-debug.txt for detailed description and the example for usage. +config CORESIGHT_CTI

• bool "CoreSight Cross Trigger Interface (CTI) driver"
• depends on ARM || ARM64
• select CORESIGHT_LINKS_AND_SINKS
• help

•  This driver provides support for CoreSight CTI and CTM components.
  

•  These provide hardware triggering events between CoreSight trace
  

•  source and sink components. These can be used  to halt trace or
  

s/"used to halt"/"used to halt"

•  inject events into the trace stream. CTI also provides a software
  

•  control to trigger same halt events. This can provide fast trace
  

s/"to trigger same halt"/"to trigger the same halt"

•  halt compared to disabling sources and sinks normally in driver
  

•  software.
  

endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 41870ded51a3..77402cfc7174 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -19,3 +19,7 @@ obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o +obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o \

• 		of_coresight-cti.o \
  

• 		coresight-cti-sysfs.o
  

It is probably a good idea to base your work on Suzuki's ACPI pathset [1] where he got rid of of_coresight.c to favour a firmware agnostic naming convention. While doing so skip patches 34 to 36 as they relate to sysfs topology and we need to deal with that separately. Better yet, include patches 34 to 36 and propose a sysfs topology representation that works for both "data" and "signal" components.

[1]. https://patchwork.kernel.org/cover/10901109/

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c new file mode 100644 index 000000000000..9b6749621dcb --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019 Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#include <linux/coresight.h> +#include <linux/coresight-pmu.h> +#include <linux/cpu.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/moduleparam.h> +#include <linux/of.h> +#include <linux/perf_event.h> +#include <linux/pm_runtime.h> +#include <linux/pm_wakeup.h> +#include <linux/seq_file.h> +#include <linux/smp.h> +#include <linux/slab.h> +#include <linux/stat.h> +#include <linux/sysfs.h> +#include <linux/types.h> +#include <linux/uaccess.h>

As far as I can tell this file can be compile with the following headers:

coresight.h device.h kernel.h spinlock.h sysfs.h types.h

Everything else can be removed and re-introduced as you need them.

+#include "coresight-cti.h"

+/* basic attributes */ +static ssize_t enable_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

Once applied the second and third line don't line up with the 's' of the first line.

+{

• int enable_req;
• bool enabled, powered, cpuid;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ssize_t size = 0;
• enable_req = atomic_read(&drvdata->config.enable_req_count);
• spin_lock(&drvdata->spinlock);
• powered = drvdata->config.hw_powered;
• enabled = drvdata->config.hw_enabled;
• cpuid = drvdata->ctidev.cpu;
• spin_unlock(&drvdata->spinlock);
• if (powered) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d powered;\n",
  

• 	enabled ? "enabled" : "disabled", cpuid);
  

• } else if (cpuid >= 0) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d unpowered;\n",
  

• 	enable_req ? "enable req" : "disable req", cpuid);
  

• } else {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; no assoc cpu;\n",
  

• 	enabled ? "enabled" : "disabled");
  

• }

This interface seems a little complex to me. I will wait to see how things evolved in the coming patches - maybe I'll understand better then.

• return size;

+}

+static ssize_t enable_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• int ret = 0;
• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• ret = kstrtoul(buf, 16, &val);
• if (ret)

• return ret;
  

• if (val)

• ret = cti_enable(drvdata->csdev, NULL);
  

• else

• ret = cti_disable(drvdata->csdev, NULL);
  

• if (ret)

• return ret;
  

• return size;

+} +static DEVICE_ATTR_RW(enable);

+/* attribute and group sysfs tables. */ +static struct attribute *coresight_cti_attrs[] = {

• &dev_attr_enable.attr,
• NULL,

+};

+static const struct attribute_group coresight_cti_group = {

• .attrs = coresight_cti_attrs,

+};

+const struct attribute_group *coresight_cti_groups[] = {

• &coresight_cti_group,
• NULL,

+}; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c new file mode 100644 index 000000000000..0a0fb6d48237 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2018 Linaro Limited, All rights reserved.

s/2018/2019

• • Author: Mike Leach mike.leach@linaro.org
• */

+#include <linux/amba/bus.h> +#include <linux/clk.h> +#include <linux/coresight.h> +#include <linux/coresight-pmu.h> +#include <linux/cpu.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/moduleparam.h> +#include <linux/of.h> +#include <linux/perf_event.h> +#include <linux/pm_runtime.h> +#include <linux/pm_wakeup.h> +#include <linux/seq_file.h> +#include <linux/smp.h> +#include <linux/slab.h> +#include <linux/stat.h> +#include <linux/sysfs.h> +#include <linux/types.h> +#include <linux/uaccess.h> +#include <asm/local.h> +#include <asm/sections.h>

+#include "coresight-cti.h"

Same comment as above - please get rid of all the headers that aren't currenlty needed.

+/**

• • CTI devices can be associated with a PE, or be connected to CoreSight
• • hardware. We have a list of all CTIs, and a subset array associated
• • with individual PEs for pwr management as they will power up in the
• • PE power domain.
• • At this point we assume that the none CPU CTIs are always powered as
• • we do with sinks etc.

s/none/non

• • We leave the client to figure out if all the CTIs are interconnected with
• • the same CTM, in general this is the case but does not always have to be.
• */

While reading the bindings and the documentation included in this set (many thanks for that), I was wondering if you have seen and tested your work on systems where more than one CTM is present.

+struct ect_node {

• struct cti_drvdata *cti_drv;
• struct list_head next;

+};

+/* net of CTI devices connected via CTM */ +LIST_HEAD(ect_net);

+/* protect the list */ +static DEFINE_MUTEX(ect_mutex);

+/* quick reference for CPU CTIs */ +static struct cti_drvdata *cti_cpu_drv[NR_CPUS];

+/* number of registered CTI devices */ +static int cti_count;

+/* number of cpu associated CTI devices in use */ +static int cti_cpu_count;

+#define csdev_to_cti_drvdata(csdev) \

• dev_get_drvdata(csdev->dev.parent)

+/* write set of regs to hardware - call with spinlock claimed */ +static void cti_write_all_hw_regs(struct cti_drvdata *drvdata) +{

• struct cti_config *config = &drvdata->config;
• int i;
• CS_UNLOCK(drvdata->base);
• /* disable CTI before writing registers */
• writel_relaxed(0, drvdata->base + CTICONTROL);
• /* write the CTI trigger registers */
• for (i = 0; i < config->nr_trig_max; i++) {

• writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
  

• writel_relaxed(config->ctiouten[i],
  

• 	drvdata->base + CTIOUTEN(i));
  

• }
• /* other regs */
• writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
• writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
• writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
• /* re-enable CTI */
• writel_relaxed(1, drvdata->base + CTICONTROL);
• CS_LOCK(drvdata->base);

+}

+static void cti_enable_hw_smp_call(void *info) +{

• struct cti_drvdata *drvdata = info;
• cti_write_all_hw_regs(drvdata);

+}

+/* write regs to hardware and enable */ +static int cti_enable_hw(void *info) +{

• struct cti_drvdata *drvdata = info;
• struct cti_config *config = &drvdata->config;
• int rc = 0;
• pm_runtime_get_sync(drvdata->dev);
• spin_lock(&drvdata->spinlock);
• /* no need to do anything if enabled or unpowered*/
• if (config->hw_enabled || !config->hw_powered)

• goto cti_not_enabled;
  

• /* claim the device */
• rc = coresight_claim_device(drvdata->base);
• if (rc)

• goto cti_not_enabled;
  

• if (drvdata->ctidev.cpu >= 0) {

• dev_info(drvdata->dev, "cti enable smp call for cpu %d\n",
  

• 	 drvdata->ctidev.cpu);
  

• rc = smp_call_function_single(drvdata->ctidev.cpu,
  

• 			 cti_enable_hw_smp_call,
  

• 			 drvdata, 1);
  

• if (rc)
  

• 	goto cti_not_enabled;
  

• } else {

• dev_info(drvdata->dev, "cti enable not cpu call\n");
  

• cti_write_all_hw_regs(drvdata);
  

• }
• config->hw_enabled = true;
• spin_unlock(&drvdata->spinlock);
• return rc;
• /* not enabled in this call */

+cti_not_enabled:

• spin_unlock(&drvdata->spinlock);
• pm_runtime_put(drvdata->dev);
• return rc;

+}

+/* disable hardware */ +static int cti_disable_hw(void *info) +{

• struct cti_drvdata *drvdata = info;
• struct cti_config *config = &drvdata->config;
• spin_lock(&drvdata->spinlock);
• /* no need to do anything if disabled or cpu unpowered*/
• if (!config->hw_enabled || !config->hw_powered) {

• spin_unlock(&drvdata->spinlock);
  

• return 0;
  

• }
• CS_UNLOCK(drvdata->base);
• /* disable CTI */
• writel_relaxed(0, drvdata->base + CTICONTROL);
• config->hw_enabled = false;
• coresight_disclaim_device_unlocked(drvdata->base);
• CS_LOCK(drvdata->base);
• spin_unlock(&drvdata->spinlock);
• pm_runtime_put(drvdata->dev);
• return 0;

+}

+static void cti_set_default_config(struct cti_config *config) +{

• /* Most regs default to 0 as zalloc'ed except...*/
• config->trig_filter_enable = 1;
• config->ctigate = ((u32)0x1 << config->nr_ctm_channels) - 1;

Please use the macro GENMASK().

• atomic_set(&config->enable_req_count, 0);

+}

+/*

• • Add a connection entry to the list of connections for this
• • CTI device.
• */

+static int cti_add_connection_entry(struct cti_drvdata *drvdata,

• 		    struct cti_trig_grp *in_info,
  

• 		    struct cti_trig_grp *out_info,
  

• 		    struct coresight_device *csdev,
  

• 		    const char *assoc_dev_name)
  

+{

• struct cti_trig_con *tc;
• struct cti_device *cti_dev = &drvdata->ctidev;
• tc = kzalloc(sizeof(struct cti_trig_con), GFP_KERNEL);
• if (tc == 0)

• return -ENOMEM;
  

• tc->con_dev = csdev;
• /*

• * Prefer actual associated CS device dev name to supplied value -
  

• * which is likely to be node name / other conn name.
  

• */
  

• if (csdev)

• tc->con_dev_name = kstrdup(dev_name(&csdev->dev), GFP_KERNEL);
  

• else if (assoc_dev_name != NULL)

• tc->con_dev_name = kstrdup(assoc_dev_name, GFP_KERNEL);
  

• tc->con_in = in_info;
• tc->con_out = out_info;
• list_add_tail(&tc->node, &cti_dev->trig_cons);
• cti_dev->nr_trig_con++;
• /* add connection usage bit info to overall info */
• drvdata->config.trig_in_use |= in_info->used_mask;
• drvdata->config.trig_out_use |= out_info->used_mask;
• return 0;

+}

+/*

• • Add a default connection if nothing else is specified.
• • single connection based on max in/out info, no assoc device
• */

+int cti_add_default_connection(struct cti_drvdata *drvdata) +{

• int ret = 0, idx;
• struct cti_trig_grp *in = 0, *out = 0;
• int n_trigs = drvdata->config.nr_trig_max;
• u32 n_trig_mask = (0x1 << n_trigs) - 1;

GENMASK().

• int *in_sig_types = 0, *out_sig_types = 0;
• in = kzalloc(sizeof(struct cti_trig_grp), GFP_KERNEL);
• if (!in) {

• ret = -ENOMEM;
  

• goto conn_add_err;
  

• }
• out = kzalloc(sizeof(struct cti_trig_grp), GFP_KERNEL);
• if (!out) {

• ret = -ENOMEM;
  

• goto conn_add_err;
  

• }
• in_sig_types = kzalloc(sizeof(int) * n_trigs, GFP_KERNEL);
• if (!in_sig_types) {

• ret = -ENOMEM;
  

• goto conn_add_err;
  

• }
• out_sig_types = kzalloc(sizeof(int) * n_trigs, GFP_KERNEL);
• if (!out_sig_types) {

• ret = -ENOMEM;
  

• goto conn_add_err;
  

• }
• /* signal types marked as default CTITRIG_GEN_IO */
• for (idx = 0; idx < n_trigs; idx++) {

• in_sig_types[idx] = CTITRIG_GEN_IO;
  

• out_sig_types[idx] = CTITRIG_GEN_IO;
  

• }
• /*

• * Assume max trigs for in and out,
  

• * all used, default sig types allocated
  

• */
  

• in->nr_sigs = n_trigs;
• in->used_mask = n_trig_mask;
• in->sig_types = in_sig_types;
• out->nr_sigs = n_trigs;
• out->used_mask = n_trig_mask;
• out->sig_types = out_sig_types;
• ret = cti_add_connection_entry(drvdata, in, out, NULL, "default");
• if (ret)

• goto conn_add_err;
  

• return ret;

+conn_add_err:

• kfree(in);
• kfree(out);
• kfree(out_sig_types);
• kfree(in_sig_types);
• return ret;

+}

+/** cti ect operations **/ +int cti_enable(struct coresight_device *csdev, void *__unused) +{

• int rc;
• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• atomic_inc(&drvdata->config.enable_req_count);
• rc = cti_enable_hw(drvdata);
• if (rc)

• atomic_dec(&drvdata->config.enable_req_count);
  

• return rc;

+}

+int cti_disable(struct coresight_device *csdev, void *__unused) +{

• int rc = 0;
• struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev);
• if (!atomic_dec_return(&drvdata->config.enable_req_count)) {

• rc = cti_disable_hw(drvdata);
  

• if (rc)
  

• 	atomic_inc(&drvdata->config.enable_req_count);
  

• }
• return rc;

+}

+const struct coresight_ops_ect cti_ops_ect = {

• .enable = cti_enable,
• .disable = cti_disable,

+};

+const struct coresight_ops cti_ops = {

• .ect_ops = &cti_ops_ect,

+};

+static int cti_probe(struct amba_device *adev, const struct amba_id *id) +{

• int ret = 0;
• u32 devid;
• void __iomem *base;
• struct device *dev = &adev->dev;
• struct cti_drvdata *drvdata = NULL;
• struct coresight_desc cti_desc;
• struct coresight_platform_data *pdata = NULL;
• struct resource *res = &adev->res;
• struct device_node *np = adev->dev.of_node;
• struct ect_node *ect_nd = NULL;
• /* boilerplate code to set up the basics */
• if (np) {

• pdata = of_get_coresight_cti_platform_data(dev, np);
  

• if (IS_ERR(pdata)) {
  

• 	dev_info(dev, "of_get_coresight_ect_platform err\n");
  

• 	return PTR_ERR(pdata);
  

• }
  

• dev->platform_data = pdata;
  

• }
• /* node to keep track of CTI net */
• ect_nd = devm_kzalloc(dev, sizeof(struct ect_node), GFP_KERNEL);
• if (!ect_nd) {

• ret = -ENOMEM;
  

• goto err_out;
  

• }
• /* driver data*/
• drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
• if (!drvdata) {

• ret = -ENOMEM;
  

• dev_info(dev, "%s, mem err\n", __func__);
  

• goto err_out;
  

• }
• /* Validity for the resource is already checked by the AMBA core */
• base = devm_ioremap_resource(dev, res);
• if (IS_ERR(base)) {

• ret = PTR_ERR(base);
  

• dev_info(dev, "%s, remap err\n", __func__);
  

• goto err_out;
  

• }
• drvdata->base = base;
• /* links between dev and drvdata*/
• drvdata->dev = dev;
• dev_set_drvdata(dev, drvdata);
• /* default CTI device info */
• drvdata->ctidev.cpu = pdata->cpu;
• drvdata->ctidev.nr_trig_con = 0;
• drvdata->ctidev.ctm_id = 0;
• INIT_LIST_HEAD(&drvdata->ctidev.trig_cons);
• spin_lock_init(&drvdata->spinlock);
• /* look at the HW DEVID register for some of the HW settings */
• devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
• drvdata->config.nr_trig_max = (int)((devid & 0xFF00) >> 8);

Every time you use hard coded values like this, please introduce a comments that explains what you are doing. For example:

"DEVID.NUM_TRIG [15:8] : Indicates the maximum number of triggers."

That way we don't always have to go back to the TRM to understand the code.

• /*

• * no current hardware should exceed this, but protect the driver
  

• * in case of fault / out of spec hw
  

• */
  

• if (drvdata->config.nr_trig_max > CTIINOUTEN_MAX) {

• dev_warn_once(dev,
  

• 	"Limiting HW MaxTrig value(%d) to driver max(%d)\n",
  

• 	drvdata->config.nr_trig_max, CTIINOUTEN_MAX);
  

• drvdata->config.nr_trig_max = CTIINOUTEN_MAX;
  

• }
• drvdata->config.nr_ctm_channels = (int)((devid & 0xF0000) >> 16);
• /* additional parse the .dts for connections and signals */
• of_cti_get_hw_data(dev, np, drvdata);
• /* initialise default driver values */
• cti_set_default_config(&drvdata->config);
• /* setup cpu related CTI devices, otherwise assume powered */
• drvdata->config.hw_powered = true;
• /* set up coresight component description */
• cti_desc.pdata = pdata;
• cti_desc.type = CORESIGHT_DEV_TYPE_ECT;
• cti_desc.subtype.ect_subtype = CORESIGHT_DEV_SUBTYPE_ECT_CTI;

Out of curiosity, do you expect other ECT device types?

• cti_desc.ops = &cti_ops;
• cti_desc.groups = coresight_cti_groups;
• cti_desc.dev = dev;
• drvdata->csdev = coresight_register(&cti_desc);
• if (IS_ERR(drvdata->csdev)) {

• ret = PTR_ERR(drvdata->csdev);
  

• pr_err("%s: CS register failed\n", pdata->name);
  

None of the other drivers have this - please remove.

• goto err_out;
  

• }
• /* add to list of CTI devices */
• mutex_lock(&ect_mutex);
• ect_nd->cti_drv = drvdata;
• list_add(&ect_nd->next, &ect_net);
• /* if cpu bound add to CPU array */
• if (drvdata->ctidev.cpu >= 0) {

• cti_cpu_drv[drvdata->ctidev.cpu] = drvdata;
  

• cti_cpu_count++;
  

• }
• mutex_unlock(&ect_mutex);
• /* all done - dec pm refcount */
• pm_runtime_put(&adev->dev);
• dev_info(dev, "%s: initialized\n", pdata->name);
• cti_count++;
• return 0;

+err_out:

• kfree(drvdata);
• kfree(ect_nd);

Because devm_kzalloc() was used to allocate the memory, the device core will automagically take care of releasing the memory for you upon error.

• return ret;

+}

+/* free all connection info from the driver */ +void cti_free_conn_info(struct cti_drvdata *drvdata) +{

• struct cti_trig_con *tc, *tc_tmp;
• list_for_each_entry_safe(tc, tc_tmp,

• 		  &drvdata->ctidev.trig_cons, node) {
  

• kfree(tc->con_in->sig_types);
  

• kfree(tc->con_in);
  

• kfree(tc->con_out->sig_types);
  

• kfree(tc->con_out);
  

• kfree(tc->con_dev_name);
  

• list_del(&tc->node);
  

• kfree(tc);
  

• }

+}

+/*

• • Free up CTI specific resources
• • • called from coresight_device_release on coresight_unregister.
• */

+void cti_device_release(struct device *dev) +{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct ect_node *ect_item, *ect_tmp;
• /* free up resources associated with the cti connections */
• if (drvdata->ctidev.cpu >= 0)

• cti_cpu_drv[drvdata->ctidev.cpu] = 0;
  

Since cti_cpu_drv[] is global it needs to be protected by ect_mutex.

• /* clear the connection list items */
• cti_free_conn_info(drvdata);
• /* remove from the list */
• mutex_lock(&ect_mutex);
• list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, next) {

• if (ect_item->cti_drv == drvdata) {
  

• 	list_del(&ect_item->next);
  

• 	kfree(ect_item);
  

• 	goto ect_list_item_removed;
  

• }
  

• }

+ect_list_item_removed:

• mutex_unlock(&ect_mutex);
• kfree(drvdata);

+} +EXPORT_SYMBOL_GPL(cti_device_release);

+static struct amba_cs_uci_id uci_id_cti[] = {

• {

• /*  CTI UCI data */
  

• .devarch	= 0x47701a14, /* devarch value for CTI v2 */
  

• .devarch_mask	= 0xfff0ffff,
  

• .devtype	= 0x00000014, /* maj(0x4-debug) min(0x1-ECT) */
  

• }

+};

+static const struct amba_id cti_ids[] = {

• CS_AMBA_ID(0x000bb906), /* Coresight CTI (SoC 400), C-A72, C-A57 */
• CS_AMBA_ID(0x000bb922), /* CTI - C-A8 */
• CS_AMBA_ID(0x000bb9a8), /* CTI - C-A53 */
• CS_AMBA_ID(0x000bb9aa), /* CTI - C-A73 */
• CS_AMBA_UCI_ID(0x000bb9da, uci_id_cti), /* CTI - C-A35 */
• CS_AMBA_UCI_ID(0x000bb9ed, uci_id_cti), /* Coresight CTI (SoC 600) */
• { 0, 0},

+};

+static struct amba_driver cti_driver = {

• .drv = {

• .name	= "coresight-cti",
  

• .owner = THIS_MODULE,
  

• .suppress_bind_attrs = true,
  

• },
• .probe = cti_probe,
• .id_table = cti_ids,

+}; +builtin_amba_driver(cti_driver); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h new file mode 100644 index 000000000000..c1af6cf9c2fe --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (c) 2018 Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#ifndef _CORESIGHT_CORESIGHT_CTI_H +#define _CORESIGHT_CORESIGHT_CTI_H

+#include <asm/local.h> +#include <linux/spinlock.h> +#include "coresight-priv.h"

+/*

• • Device registers
• • 0x000 - 0x144: CTI programming and status
• • 0xEDC - 0xEF8: CTI integration test.
• • 0xF00 - 0xFFC: Coresight management registers.
• */

+/* CTI programming registers */ +#define CTICONTROL 0x000 +#define CTIINTACK 0x010 +#define CTIAPPSET 0x014 +#define CTIAPPCLEAR 0x018 +#define CTIAPPPULSE 0x01C +#define CTIINEN(n) (0x020 + (4 * n)) +#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTITRIGINSTATUS 0x130 +#define CTITRIGOUTSTATUS 0x134 +#define CTICHINSTATUS 0x138 +#define CTICHOUTSTATUS 0x13C +#define CTIGATE 0x140 +#define ASICCTL 0x144 +/* Integration test registers */ +#define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/ +#define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/ +#define ITCHOUT 0xEE4 /* WO RW-600 */ +#define ITTRIGOUT 0xEE8 /* WO RW-600 */ +#define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/ +#define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/ +#define ITCHIN 0xEF4 /* RO */ +#define ITTRIGIN 0xEF8 /* RO */ +/* management registers */ +#define CTIDEVAFF0 0xFA8 +#define CTIDEVAFF1 0xFAC

On my side some of the defines above are misaligned - is it the same on your side?

+/*

• • CTI CSSoc 600 has a max of 32 trigger signals per direction.
• • CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
• • Max of in and out defined in the DEVID register.
• • • pick up actual number used from .dts parameters if present.
• */

+#define CTIINOUTEN_MAX 32

+/*

• • CTI Trigger signal type definitions.
• • Labels for certain trigger interconnections between the CTI
• • and standard CS components.
• • Must match values in ./include/dt-bindings/arm/coresight-cti.h
• */

+#define CTITRIG_GEN_IO 0 +#define CTITRIG_GEN_INTREQ 1 +#define CTITRIG_GEN_INTACK 2 +#define CTITRIG_GEN_HALTREQ 3 +#define CTITRIG_GEN_RESTARTREQ 4 +#define CTITRIG_PE_EDBGREQ 5 +#define CTITRIG_PE_DBGRESTART 6 +#define CTITRIG_PE_CTIIRQ 7 +#define CTITRIG_PE_PMUIRQ 8 +#define CTITRIG_PE_DBGTRIGGER 9 +#define CTITRIG_ETM_EXTOUT 10 +#define CTITRIG_ETM_EXTIN 11 +#define CTITRIG_SNK_FULL 12 +#define CTITRIG_SNK_ACQCOMP 13 +#define CTITRIG_SNK_FLUSHCOMP 14 +#define CTITRIG_SNK_FLUSHIN 15 +#define CTITRIG_SNK_TRIGIN 16 +#define CTITRIG_STM_ASYNCOUT 17 +#define CTITRIG_STM_TOUT_SPTE 18 +#define CTITRIG_STM_TOUT_SW 19 +#define CTITRIG_STM_TOUT_HETE 20 +#define CTITRIG_STM_HWEVENT 21 +#define CTITRIG_ELA_TSTART 22 +#define CTITRIG_ELA_TSTOP 23 +#define CTITRIG_ELA_DBGREQ 24

+/**

• • Group of related trigger signals
• • @nr_sigs: number of signals in the group.
• • @used_mask: bitmask representing the signal indexes in the group.
• • @sig_types: array of types for the signals, length nr_sigs.
• */

+struct cti_trig_grp {

• int nr_sigs;
• u32 used_mask;
• int *sig_types;

+};

+/**

• • Trigger connection - connection between a CTI and other (coresight) device
• • lists input and output trigger signals for the device
• • @con_in: connected CTIIN signals for the device.
• • @con_out: connected CTIOUT signals for the device.
• • @con_dev: coresight device connected to the CTI, NULL if not CS device
• • @con_dev_name: name of connected device (CS or CPU)
• • @node: entry node in list of connections.
• */

+struct cti_trig_con {

• struct cti_trig_grp *con_in;
• struct cti_trig_grp *con_out;
• struct coresight_device *con_dev;
• char *con_dev_name;
• struct list_head node;

+};

+/**

• • struct cti_device - description of CTI device properties.
• • @nt_trig_con: Number of external devices connected to this device.
• • @ctm_id: which CTM this device is connected to (by default it is

• •      assumed there is a single CTM per SoC, ID 0).
    

• • @trig_cons: list of connections to this device.
• • @cpu: CPU ID if associated with CPU, -1 otherwise.

One line too many.

• */

+struct cti_device {

• int nr_trig_con;
• u32 ctm_id;
• struct list_head trig_cons;
• int cpu;

+};

The structures defined above don't have a tabulation between their type and variable name - but this one (and the following) do. Though the community tends to lean toward the "no tab" format I don't think there is an enforced rule. As such I will leave it to you to choose what you prefer. On the flip side I would ask that you enact the same pattern within the file.

+/**

• • struct cti_config - configuration of the CTI device hardware
• • hardware description from RO ID regs
• • @nr_trig_max: Max number of trigger signals implemented on device.

• • (max of trig_in or trig_out)
    

• • @nr_ctm_channels: number of available CTM channels
• • cti enable control
• • @enable_req_count: CTI is enabled alongside >=1 associated devices.
• • @hw_enabled: true if hw is currently enabled.
• • @hw_powered: true if associated cpu powered on, or no cpu.
• • registered triggers and filtering
• • @trig_in_use: bitfield of in triggers registered as in use.
• • @trig_out_use: bitfield of out triggers registered as in use.
• • @trig_out_filter: bitfield of out triggers that are blocked if filter
• • enabled. Typically this would be dbgreq / restart on a core CTI.
• • @trig_filter_enable: 1 if filtering enabled.
• • cti software programmable regs:
• • @ctiappset: CTI Software application channel set.
• • @ctiinout_sel: register selector for INEN and OUTEN regs.
• • @ctiinen: enable input trigger to a channel.
• • @ctiouten: enable output trigger from a channel.
• • @ctigate: gate channel output from CTI to CTM.
• */

+struct cti_config {

• /* hardware description */
• int nr_ctm_channels;
• int nr_trig_max;
• /* cti enable control */
• atomic_t enable_req_count;
• bool hw_enabled;
• bool hw_powered;
• /* registered triggers and filtering */
• u32 trig_in_use;
• u32 trig_out_use;
• u32 trig_out_filter;
• int trig_filter_enable;
• /* cti cross trig programmable regs */
• u32 ctiappset;
• u8 ctiinout_sel;
• u32 ctiinen[CTIINOUTEN_MAX];
• u32 ctiouten[CTIINOUTEN_MAX];
• u32 ctigate;
• u32 asicctl;

+};

+/**

• • struct cti_drvdata - specifics for the CTI device
• • @base: Memory mapped base address for this component.
• • @dev: The device entity associated to this component.
• • @csdev: Standard CoreSight device information.
• • @ctidev: Extra information needed by the CTI/CTM framework.
• • @spinlock: Control data access to one at a time.
• • @config: Configuration data for this CTI device.
• */

+struct cti_drvdata {

• void __iomem *base;
• struct device *dev;
• struct coresight_device *csdev;
• struct cti_device ctidev;
• spinlock_t spinlock;
• struct cti_config config;

+};

+/* private cti driver fns & vars */ +extern const struct attribute_group *coresight_cti_groups[]; +int cti_add_default_connection(struct cti_drvdata *drvdata); +int cti_enable(struct coresight_device *csdev, void *__unused); +int cti_disable(struct coresight_device *csdev, void *__unused);

+#ifdef CONFIG_OF +extern int of_cti_get_hw_data(struct device *dev,

•       struct device_node *np,
  

•        struct cti_drvdata *drvdata);
  

+extern struct coresight_platform_data * +of_get_coresight_cti_platform_data(struct device *dev,

• 		   const struct device_node *node);
  

+#else +static inline int of_cti_get_hw_data(struct device *dev,

•       struct device_node *np,
  

•        struct cti_drvdata *drvdata)
  

+{ return 0; }; +static inline struct coresight_platform_data * +of_get_coresight_cti_platform_data(struct device *dev,

• 	   const struct device_node *node) { return NULL; }
  

+#endif

+#endif /* _CORESIGHT_CORESIGHT_CTI_H */ diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index e0684d06e9ee..8e9e5b6ad866 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -161,6 +161,13 @@ static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } #endif +#ifdef CONFIG_CORESIGHT_CTI +extern void cti_device_release(struct device *dev); +#else +static inline void cti_device_release(struct device *dev) {}; +#endif

/*

• Macros and inline functions to handle CoreSight UCI data and driver
• private data in AMBA ID table entries, and extract data values.

diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 29cef898afba..8db3d1a5314f 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -967,12 +967,20 @@ static struct device_type coresight_dev_type[] = { { .name = "helper", },

• {

• .name = "ect",
  

• },

}; static void coresight_device_release(struct device *dev) { struct coresight_device *csdev = to_coresight_device(dev);

• /* additional info to release for CTI */
• if ((csdev->type == CORESIGHT_DEV_TYPE_ECT) &&

•    (csdev->subtype.ect_subtype == CORESIGHT_DEV_SUBTYPE_ECT_CTI))
  

• cti_device_release(dev);
  

• kfree(csdev->conns); kfree(csdev->refcnt); kfree(csdev);

diff --git a/drivers/hwtracing/coresight/of_coresight-cti.c b/drivers/hwtracing/coresight/of_coresight-cti.c new file mode 100644 index 000000000000..379ca1113deb --- /dev/null +++ b/drivers/hwtracing/coresight/of_coresight-cti.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2019, The Linux Foundation. All rights reserved.
• */

+#include <linux/amba/bus.h> +#include <linux/clk.h> +#include <linux/coresight.h> +#include <linux/cpumask.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_graph.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/types.h>

+#include "coresight-cti.h"

+#ifdef CONFIG_OF

+/*

• • CTI can be bound to a CPU, or a system device.
• • Reflect this in the return value and do not default to cpu 0
• */

+static int of_cti_get_cpu(const struct device_node *node) +{

• int cpu;
• struct device_node *dn;
• dn = of_parse_phandle(node, "cpu", 0);
• /* CTI Affinity defaults to no cpu */
• if (!dn)

• return -1;
  

• cpu = of_cpu_node_to_id(dn);
• of_node_put(dn);
• /* No Affinity if no cpu nodes are found */
• return (cpu < 0) ? -1 : cpu;

+}

+/* get the hardware configuration & connection data. */ +int of_cti_get_hw_data(struct device *dev,

•       struct device_node *np,
  

•       struct cti_drvdata *drvdata)
  

+{

• int rc = 0;
• struct cti_device *cti_dev = &drvdata->ctidev;
• /* if no connections, just add a single default based on max IN-OUT */
• if (cti_dev->nr_trig_con == 0)

• rc = cti_add_default_connection(drvdata);
  

• return rc;

+}

+/*

• • Platform data for the CTI does not have the same connection info
• • as the trace path components. Implement specific function to
• • avoid warnings of missing connections.
• */

+struct coresight_platform_data * +of_get_coresight_cti_platform_data(struct device *dev,

• 		   const struct device_node *node)
  

+{

• struct coresight_platform_data *pdata;
• pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
• if (!pdata)

• return ERR_PTR(-ENOMEM);
  

• /* Use device name as sysfs handle */
• pdata->name = dev_name(dev);
• /* Look for a CPU ID at the current node level */
• pdata->cpu = of_cti_get_cpu(node);
• return pdata;

+}

+#endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7b87965f7a65..d1c1ed17d2ca 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -41,6 +41,7 @@ enum coresight_dev_type { CORESIGHT_DEV_TYPE_LINKSINK, CORESIGHT_DEV_TYPE_SOURCE, CORESIGHT_DEV_TYPE_HELPER,

• CORESIGHT_DEV_TYPE_ECT,

}; enum coresight_dev_subtype_sink { @@ -68,6 +69,12 @@ enum coresight_dev_subtype_helper { CORESIGHT_DEV_SUBTYPE_HELPER_CATU, }; +/* Embedded Cross Trigger (ECT) sub-types */ +enum coresight_dev_subtype_ect {

• CORESIGHT_DEV_SUBTYPE_ECT_NONE,
• CORESIGHT_DEV_SUBTYPE_ECT_CTI

+};

/**

• union coresight_dev_subtype - further characterisation of a type
• @sink_subtype: type of sink this component is, as defined

@@ -78,6 +85,8 @@ enum coresight_dev_subtype_helper {

• 	by @coresight_dev_subtype_source.
  

• @helper_subtype: type of helper this component is, as defined

• 	by @coresight_dev_subtype_helper.
  

• • @ect_subtype: type of cross trigger this component is, as

• • 	defined by @coresight_dev_subtype_ect
    

  */

union coresight_dev_subtype { /* We have some devices which acts as LINK and SINK */ @@ -87,6 +96,7 @@ union coresight_dev_subtype { }; enum coresight_dev_subtype_source source_subtype; enum coresight_dev_subtype_helper helper_subtype;

• enum coresight_dev_subtype_ect ect_subtype;

}; /** @@ -180,6 +190,7 @@ struct coresight_device { #define sink_ops(csdev) csdev->ops->sink_ops #define link_ops(csdev) csdev->ops->link_ops #define helper_ops(csdev) csdev->ops->helper_ops +#define ect_ops(csdev) csdev->ops->ect_ops /**

• struct coresight_ops_sink - basic operations for a sink

@@ -245,11 +256,26 @@ struct coresight_ops_helper { int (*disable)(struct coresight_device *csdev, void *data); }; +/**

• • struct coresight_ops_ect - Ops for an embedded cross trigger device
• • All operations could pass in a device specific data, which could
• • help the ect device to determine what to do.
• • @enable : Enable the device
• • @disable : Disable the device
• */

+struct coresight_ops_ect {

• int (*enable)(struct coresight_device *csdev, void *data);
• int (*disable)(struct coresight_device *csdev, void *data);

+};

struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops;

• const struct coresight_ops_ect *ect_ops;

};

#ifdef CONFIG_CORESIGHT

2.20.1

On Wed, May 01, 2019 at 09:49:34AM +0100, Mike Leach wrote:

Adds in required sysfs access for:-

• CoreSight management registers.
• CTI device specific registers.
• Channel Cross triggering API.

This provides the basic programming interface for the device.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 831 +++++++++++++++++- drivers/hwtracing/coresight/coresight-cti.c | 188 +++- drivers/hwtracing/coresight/coresight-cti.h | 42 + drivers/hwtracing/coresight/coresight-priv.h | 2 + 4 files changed, 1053 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 9b6749621dcb..ff8dad02a779 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -34,8 +34,8 @@ static ssize_t enable_show(struct device *dev, struct device_attribute *attr, char *buf) {

• int enable_req;
• bool enabled, powered, cpuid;

• int enable_req, cpuid;
• bool enabled, powered; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); ssize_t size = 0;

@@ -46,12 +46,18 @@ static ssize_t enable_show(struct device *dev, cpuid = drvdata->ctidev.cpu; spin_unlock(&drvdata->spinlock);

• if (powered) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d powered;\n",
  

• 	enabled ? "enabled" : "disabled", cpuid);
  

• } else if (cpuid >= 0) {

• size = scnprintf(buf, PAGE_SIZE, "cti %s; cpu%d unpowered;\n",
  

• 	enable_req ? "enable req" : "disable req", cpuid);
  

• if (cpuid >= 0) {

• if (powered) {
  

• 	size = scnprintf(buf, PAGE_SIZE,
  

• 			 "cti %s; cpu%d powered;\n",
  

• 			 enabled ? "enabled" : "disabled",
  

• 			 cpuid);
  

• } else {
  

• 	size = scnprintf(buf, PAGE_SIZE,
  

• 		"cti %s; cpu%d unpowered;\n",
  

• 		enable_req ? "enable req" : "disable req",
  

• 		cpuid);
  

• }
  

  } else { size = scnprintf(buf, PAGE_SIZE, "cti %s; no assoc cpu;\n", enabled ? "enabled" : "disabled");

@@ -81,17 +87,826 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable); +static ssize_t ctmid_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return scnprintf(buf, PAGE_SIZE, "0x%x\n", drvdata->ctidev.ctm_id);

+} +static DEVICE_ATTR_RO(ctmid);

/* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr,

• &dev_attr_ctmid.attr, NULL,

}; +/* register based attributes */ +#define coresight_cti_reg(name, offset) \

• coresight_simple_reg32(struct cti_drvdata, name, offset)

+/*

• • Show a simple 32 bit value. If pval is NULL then live read,
• • otherwise read from supplied pointer only.
• */

+static ssize_t cti_reg32_show(struct device *dev, char *buf,

• 	      u32 *pval, int reg_offset)
  

+{

• unsigned long val = 0;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• spin_lock(&drvdata->spinlock);
• if (pval) {

• val = (unsigned long)*pval;
  

• } else if ((reg_offset >= 0) && CTI_PWR_ENA(config)) {

• CS_UNLOCK(drvdata->base);
  

• val = readl_relaxed(drvdata->base + reg_offset);
  

• CS_LOCK(drvdata->base);
  

• }
• spin_unlock(&drvdata->spinlock);
• return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);

+}

+/*

• • Store a simple 32 bit value.
• • If pval not NULL, then copy to here too,
• • if reg_offset >= 0 then write through if enabled.
• */

+static ssize_t cti_reg32_store(struct device *dev, const char *buf,

• 	       size_t size, u32 *pval,
  

• 	       int reg_offset)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• /* local store */
• if (pval)

• *pval = (u32)val;
  

• /* write through of offset and enabled */
• if ((reg_offset >= 0) && CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, reg_offset, val);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+}

+/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);

+static struct attribute *coresight_cti_mgmt_attrs[] = {

• &dev_attr_devaff0.attr,
• &dev_attr_devaff1.attr,
• &dev_attr_authstatus.attr,
• &dev_attr_devarch.attr,
• &dev_attr_devid.attr,
• &dev_attr_devtype.attr,
• &dev_attr_pidr0.attr,
• &dev_attr_pidr1.attr,
• &dev_attr_pidr2.attr,
• &dev_attr_pidr3.attr,
• &dev_attr_pidr4.attr,
• NULL,

+};

+/* CTI low level programming registers */ +static ssize_t inout_sel_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• u32 val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• val = (u32)drvdata->config.ctiinout_sel;
• return scnprintf(buf, PAGE_SIZE, "%#x\n", val);

+}

+static ssize_t inout_sel_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• if (val > (CTIINOUTEN_MAX-1))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->config.ctiinout_sel = val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(inout_sel);

+static ssize_t inen_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• unsigned long val;
• int index;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• spin_lock(&drvdata->spinlock);
• index = drvdata->config.ctiinout_sel;
• val = drvdata->config.ctiinen[index];
• spin_unlock(&drvdata->spinlock);
• return scnprintf(buf, PAGE_SIZE, "INEN%d %#lx\n", index, val);

+}

+static ssize_t inen_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val;
• int index;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• index = config->ctiinout_sel;
• config->ctiinen[index] = val;
• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, CTIINEN(index), val);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(inen);

+static ssize_t outen_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• unsigned long val;
• int index;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• spin_lock(&drvdata->spinlock);
• index = drvdata->config.ctiinout_sel;
• val = drvdata->config.ctiouten[index];
• spin_unlock(&drvdata->spinlock);
• return scnprintf(buf, PAGE_SIZE, "OUTEN%d %#lx\n", index, val);

+}

+static ssize_t outen_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val;
• int index;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• index = config->ctiinout_sel;
• config->ctiouten[index] = val;
• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, CTIOUTEN(index), val);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(outen);

+static ssize_t gate_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_show(dev, buf, &drvdata->config.ctigate, -1);

+}

+static ssize_t gate_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_store(dev, buf, size,

• 	       &drvdata->config.ctigate, CTIGATE);
  

+} +static DEVICE_ATTR_RW(gate);

+static ssize_t asicctl_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_show(dev, buf, &drvdata->config.asicctl, -1);

+}

+static ssize_t asicctl_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_store(dev, buf, size,

• 	       &drvdata->config.asicctl, ASICCTL);
  

+} +static DEVICE_ATTR_RW(asicctl);

+static ssize_t intack_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• cti_write_intack(dev, val);
• return size;

+} +static DEVICE_ATTR_WO(intack);

+static ssize_t appset_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_show(dev, buf, &drvdata->config.ctiappset, -1);

+}

+static ssize_t appset_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return cti_reg32_store(dev, buf, size,

• 	       &drvdata->config.ctiappset, CTIAPPSET);
  

+} +static DEVICE_ATTR_RW(appset);

+static ssize_t appclear_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val, mask;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• /* a 1'b1 in appclr clears down the same bit in appset*/
• mask = ~val;
• config->ctiappset &= mask;
• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, CTIAPPCLEAR, val);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(appclear);

+static ssize_t apppulse_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val, mask;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• /*

• * a 1'b1 in apppulse sets then clears the bit,
  

• * effectively clears down the same bit in appset
  

• */
  

• mask = ~val;
• config->ctiappset &= mask;
• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, CTIAPPPULSE, val);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(apppulse);

+static ssize_t itchout_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• return cti_reg32_show(dev, buf, NULL, ITCHOUT);

+}

+static ssize_t itchout_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• return cti_reg32_store(dev, buf, size, NULL, ITCHOUT);

+} +static DEVICE_ATTR_RW(itchout);

+static ssize_t ittrigout_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• return cti_reg32_show(dev, buf, NULL, ITTRIGOUT);

+}

+static ssize_t ittrigout_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• return cti_reg32_store(dev, buf, size, NULL, ITTRIGOUT);

+} +static DEVICE_ATTR_RW(ittrigout);

+static ssize_t itchinack_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• return cti_reg32_store(dev, buf, size, NULL, ITCHINACK);

+} +static DEVICE_ATTR_WO(itchinack);

+static ssize_t ittriginack_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• return cti_reg32_store(dev, buf, size, NULL, ITTRIGINACK);

+} +static DEVICE_ATTR_WO(ittriginack);

+static ssize_t itctrl_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• return cti_reg32_show(dev, buf, NULL, CORESIGHT_ITCTRL);

+}

+static ssize_t itctrl_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• return cti_reg32_store(dev, buf, size, NULL, CORESIGHT_ITCTRL);

+} +static DEVICE_ATTR_RW(itctrl);

+coresight_cti_reg(triginstatus, CTITRIGINSTATUS); +coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS); +coresight_cti_reg(chinstatus, CTICHINSTATUS); +coresight_cti_reg(choutstatus, CTICHOUTSTATUS); +coresight_cti_reg(ittrigin, ITTRIGIN); +coresight_cti_reg(itchin, ITCHIN); +coresight_cti_reg(itchoutack, ITCHOUTACK); +coresight_cti_reg(ittrigoutack, ITTRIGOUTACK);

+static struct attribute *coresight_cti_regs_attrs[] = {

• &dev_attr_inout_sel.attr,
• &dev_attr_inen.attr,
• &dev_attr_outen.attr,
• &dev_attr_gate.attr,
• &dev_attr_asicctl.attr,
• &dev_attr_intack.attr,
• &dev_attr_appset.attr,
• &dev_attr_appclear.attr,
• &dev_attr_apppulse.attr,
• &dev_attr_triginstatus.attr,
• &dev_attr_trigoutstatus.attr,
• &dev_attr_chinstatus.attr,
• &dev_attr_choutstatus.attr,
• &dev_attr_itctrl.attr,
• &dev_attr_ittrigin.attr,
• &dev_attr_itchin.attr,
• &dev_attr_ittrigout.attr,
• &dev_attr_itchout.attr,
• &dev_attr_itchoutack.attr,
• &dev_attr_ittrigoutack.attr,
• &dev_attr_ittriginack.attr,
• &dev_attr_itchinack.attr,
• NULL,

+};

+/* CTI channel x-trigger programming */ +static int +cti_trig_op_parse(struct device *dev, enum cti_chan_op op,

•   enum cti_trig_dir dir, const char *buf, size_t size)
  

+{

• u32 chan_idx;
• u32 trig_idx;
• int items, err = size;
• /* extract chan idx and trigger idx */
• items = sscanf(buf, "%d %d", &chan_idx, &trig_idx);
• if (items) {

• err = cti_channel_trig_op(dev, op, dir, chan_idx, trig_idx);
  

• if (!err)
  

• 	err = size;
  

• } else

• err = -EINVAL;
  

• return err;

+}

+static ssize_t trigin_attach_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_IN,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigin_attach);

+static ssize_t trigin_detach_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_IN,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigin_detach);

+static ssize_t trigout_attach_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_ATTACH, CTI_TRIG_OUT,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigout_attach);

+static ssize_t trigout_detach_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• return cti_trig_op_parse(dev, CTI_CHAN_DETACH, CTI_TRIG_OUT,

• 		 buf, size);
  

+} +static DEVICE_ATTR_WO(trigout_detach);

+static ssize_t gate_enable_store(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE_ALL, 0);
  

• } else {

• if (kstrtoint(buf, 0, &channel))
  

• 	return -EINVAL;
  

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_ENABLE, channel);
  

• }
• return err ? err : size;

+} +static DEVICE_ATTR_WO(gate_enable);

+static ssize_t gate_disable_store(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 const char *buf, size_t size)
  

+{

• int err = 0, channel = 0;
• if ((size >= 3) && (strncmp(buf, "all", 3) == 0)) {

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE_ALL, 0);
  

• } else {

• if (kstrtoint(buf, 0, &channel))
  

• 	return -EINVAL;
  

• err = cti_channel_gate_op(dev, CTI_GATE_CHAN_DISABLE, channel);
  

• }
• return err ? err : size;

+} +static DEVICE_ATTR_WO(gate_disable);

+static int +chan_op_parse(struct device *dev, enum cti_chan_set_op op, const char *buf) +{

• int err = 0, channel = 0;
• if (kstrtoint(buf, 0, &channel))

• return -EINVAL;
  

• err = cti_channel_setop(dev, op, channel);
• return err;

+}

+static ssize_t chan_set_store(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_SET, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_set);

+static ssize_t chan_clear_store(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_CLR, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_clear);

+static ssize_t chan_pulse_store(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 const char *buf, size_t size)
  

+{

• int err = chan_op_parse(dev, CTI_CHAN_PULSE, buf);
• return err ? err : size;

+} +static DEVICE_ATTR_WO(chan_pulse);

+static ssize_t trig_filter_enable_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• spin_lock(&drvdata->spinlock);
• val = drvdata->config.trig_filter_enable;
• spin_unlock(&drvdata->spinlock);
• return scnprintf(buf, PAGE_SIZE, "%ld (%s)\n", val,

• 	 val ? "enabled" : "disabled");
  

+}

+static ssize_t trig_filter_enable_store(struct device *dev,

• 	  struct device_attribute *attr,
  

• 	  const char *buf, size_t size)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (kstrtoul(buf, 16, &val))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->config.trig_filter_enable = val ? 1 : 0;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(trig_filter_enable);

+/* clear all xtrigger / channel programming */ +static ssize_t reset_xtrigs_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• int i;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• spin_lock(&drvdata->spinlock);
• /* clear the CTI trigger / channel programming registers */
• for (i = 0; i < config->nr_trig_max; i++) {

• config->ctiinen[i] = 0;
  

• config->ctiouten[i] = 0;
  

• }
• /* clear the other regs */
• config->ctigate = (0x1 << config->nr_ctm_channels) - 1;
• config->asicctl = 0;
• config->ctiappset = 0;
• config->ctiinout_sel = 0;

confit->xtrig_rchan_sel = 0;

• /* if enabled then write through */
• if (CTI_PWR_ENA(config))

• cti_write_all_hw_regs(drvdata);
  

• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_WO(reset_xtrigs);

+static ssize_t show_chan_sel_show(struct device *dev,

• 	      struct device_attribute *attr,
  

• 	      char *buf)
  

+{

• u32 val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• val = (u32)drvdata->config.xtrig_rchan_sel;
• return scnprintf(buf, PAGE_SIZE, "%d\n", val);

+}

+/* select a channel for the show_chan_xtrig function */ +static ssize_t show_chan_sel_store(struct device *dev,

• 	       struct device_attribute *attr,
  

• 	       const char *buf, size_t size)
  

+{

• unsigned long val;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (kstrtoul(buf, 16, &val))

I think this should be base 10.

• return -EINVAL;
  

• if (val > (drvdata->config.nr_ctm_channels-1))

• return -EINVAL;
  

• spin_lock(&drvdata->spinlock);
• drvdata->config.xtrig_rchan_sel = val;
• spin_unlock(&drvdata->spinlock);
• return size;

+} +static DEVICE_ATTR_RW(show_chan_sel);

+/* for the selected channel - show the signals attached. */ +static ssize_t show_chan_xtrigs_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• int used = 0, reg_idx;
• int buf_sz = PAGE_SIZE;
• u32 chan_mask = 0x1 << cfg->xtrig_rchan_sel;
• used += scnprintf(buf, buf_sz, "IN: ");
• for (reg_idx = 0;

•     reg_idx < drvdata->config.nr_trig_max;
  

•     reg_idx++) {
  

• if (chan_mask & cfg->ctiinen[reg_idx]) {
  

• 	used += scnprintf(buf+used, buf_sz-used, "%d ",
  

• 			 reg_idx);
  

• }
  

• }
• used += scnprintf(buf+used, buf_sz-used, " OUT: ");
• for (reg_idx = 0;

•     reg_idx < drvdata->config.nr_trig_max;
  

•     reg_idx++) {
  

• if (chan_mask & cfg->ctiouten[reg_idx]) {
  

• 	used += scnprintf(buf+used, buf_sz-used, "%d ",
  

• 			 reg_idx);
  

• }
  

• }
• used += scnprintf(buf+used, buf_sz-used, "\n");
• return used;

+} +static DEVICE_ATTR_RO(show_chan_xtrigs);

+static ssize_t print_chan_list(struct device *dev,

• 	       char *buf, bool inuse)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• int used = 0, i;
• u32 inuse_bits = 0, chan_mask, chan_bit_mask;
• /* scan regs to get bitmap of channels in use. */
• spin_lock(&drvdata->spinlock);
• for (i = 0; i < config->nr_trig_max; i++) {

• inuse_bits |= config->ctiinen[i];
  

• inuse_bits |= config->ctiouten[i];
  

• }
• spin_unlock(&drvdata->spinlock);
• /* inverse bits if printing free channels */
• if (!inuse)

• inuse_bits = ~inuse_bits;
  

• /* list of channels, or 'none' */
• chan_mask = ((u32)(0x1 << config->nr_ctm_channels)) - 1;
• if (inuse_bits & chan_mask) {

• for (i = 0; i < config->nr_ctm_channels; i++) {
  

• 	chan_bit_mask = 0x1 << i;
  

• 	if (chan_bit_mask & inuse_bits) {
  

• 		used += scnprintf(buf+used, PAGE_SIZE-used,
  

• 				  "%d ", i);
  

• 	}
  

• }
  

• used += scnprintf(buf+used, PAGE_SIZE-used, "\n");
  

• } else {

• used = scnprintf(buf, PAGE_SIZE, "none\n");
  

• }
• return used;

+}

+static ssize_t list_inuse_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• return print_chan_list(dev, buf, true);

+} +static DEVICE_ATTR_RO(list_inuse);

+static ssize_t list_free_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• return print_chan_list(dev, buf, false);

+} +static DEVICE_ATTR_RO(list_free);

+static ssize_t list_gate_ena_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• int b_sz = PAGE_SIZE;
• u32 chan_mask;
• int chan, used = 0;
• if (cfg->ctigate == 0) {

• used += scnprintf(buf, b_sz, "none\n");
  

• } else {

• for (chan = 0; chan < cfg->nr_ctm_channels; chan++) {
  

• 	chan_mask = 0x1 << chan;
  

• 	if (chan_mask & cfg->ctigate) {
  

• 		used += scnprintf(buf+used, b_sz-used, "%d ",
  

• 				  chan);
  

• 	}
  

• }
  

• used += scnprintf(buf+used, b_sz-used, "\n");
  

• }
• return used;

+} +static DEVICE_ATTR_RO(list_gate_ena);

+static struct attribute *coresight_cti_channel_attrs[] = {

• &dev_attr_trigin_attach.attr,
• &dev_attr_trigin_detach.attr,
• &dev_attr_trigout_attach.attr,
• &dev_attr_trigout_detach.attr,
• &dev_attr_gate_enable.attr,
• &dev_attr_gate_disable.attr,
• &dev_attr_chan_set.attr,
• &dev_attr_chan_clear.attr,
• &dev_attr_chan_pulse.attr,
• &dev_attr_trig_filter_enable.attr,
• &dev_attr_reset_xtrigs.attr,
• &dev_attr_show_chan_sel.attr,
• &dev_attr_show_chan_xtrigs.attr,
• &dev_attr_list_inuse.attr,
• &dev_attr_list_free.attr,
• &dev_attr_list_gate_ena.attr,
• NULL,

+};

+/* attribute and group sysfs tables. */ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, }; +static const struct attribute_group coresight_cti_mgmt_group = {

• .attrs = coresight_cti_mgmt_attrs,
• .name = "mgmt",

+};

+static const struct attribute_group coresight_cti_regs_group = {

• .attrs = coresight_cti_regs_attrs,
• .name = "regs",

+};

+static const struct attribute_group coresight_cti_channels_group = {

• .attrs = coresight_cti_channel_attrs,
• .name = "channels",

+};

const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group,

• &coresight_cti_mgmt_group,
• &coresight_cti_regs_group,
• &coresight_cti_channels_group, NULL,

}; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 0a0fb6d48237..06b1f84795a4 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -69,7 +69,7 @@ static int cti_cpu_count; dev_get_drvdata(csdev->dev.parent) /* write set of regs to hardware - call with spinlock claimed */ -static void cti_write_all_hw_regs(struct cti_drvdata *drvdata) +void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; int i; @@ -173,6 +173,13 @@ static int cti_disable_hw(void *info) return 0; } +void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) +{

• CS_UNLOCK(drvdata->base);
• writel_relaxed(value, drvdata->base+offset);
• CS_LOCK(drvdata->base);

+}

static void cti_set_default_config(struct cti_config *config) { /* Most regs default to 0 as zalloc'ed except...*/ @@ -285,6 +292,178 @@ int cti_add_default_connection(struct cti_drvdata *drvdata) return ret; } +/** cti channel api **/ +/* attach/detach channel from trigger - write through if enabled. */ +int cti_channel_trig_op(struct device *dev,

• 	enum cti_chan_op op,
  

• 	enum cti_trig_dir direction,
  

• 	u32 channel_idx,
  

• 	u32 trigger_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 trig_bitmask;
• u32 chan_bitmask;
• u32 reg_value;
• int reg_offset;
• dev_info(dev, "chan_trig_op: op %d, dir %d, chan %d, trig %d\n",

•  op, direction, channel_idx, trigger_idx);
  

• /* ensure indexes in range */
• if ((channel_idx >= config->nr_ctm_channels) ||

•   (trigger_idx >= config->nr_trig_max))
  

• return -EINVAL;
  

• trig_bitmask = 0x1 << trigger_idx;
• /* ensure registered triggers and not out filtered */
• if (direction == CTI_TRIG_IN) {

• if (!(trig_bitmask & config->trig_in_use))
  

• 	return -EINVAL;
  

• } else {

• if (!(trig_bitmask & config->trig_out_use))
  

• 	return -EINVAL;
  

• if ((config->trig_filter_enable) &&
  

Do we need ->trig_filter_enable?

•     (config->trig_out_filter & trig_bitmask))
  

Wouldn't it be sufficient to check ->trig_out_filter like you're doing here?

• 	return -EINVAL;
  

• }
• /* update the local register values */
• chan_bitmask = 0x1 << channel_idx;
• reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :

•       CTIOUTEN(trigger_idx));
  

• spin_lock(&drvdata->spinlock);
• /* read - modify write - the trigger / channel enable value */
• reg_value = (direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] :

•      config->ctiouten[trigger_idx]);
  

• reg_value = (op == CTI_CHAN_ATTACH) ? reg_value | chan_bitmask :

• reg_value & (~chan_bitmask);
  

• /* write local copy */
• if (direction == CTI_TRIG_IN)

• config->ctiinen[trigger_idx] = reg_value;
  

• else

• config->ctiouten[trigger_idx] = reg_value;
  

• /* write through if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, reg_offset, reg_value);
  

• spin_unlock(&drvdata->spinlock);
• return 0;

+}

+int cti_channel_gate_op(struct device *dev,

• 	enum cti_chan_gate_op op,
  

• 	u32 channel_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 chan_bitmask;
• u32 reg_value;
• int err = 0;
• if (channel_idx >= config->nr_ctm_channels)

• return -EINVAL;
  

• chan_bitmask = 0x1 << channel_idx;
• spin_lock(&drvdata->spinlock);
• reg_value = config->ctigate;
• switch (op) {
• case CTI_GATE_CHAN_ENABLE:

• reg_value |= chan_bitmask;
  

• break;
  

• case CTI_GATE_CHAN_DISABLE:

• reg_value &= ~chan_bitmask;
  

• break;
  

• case CTI_GATE_CHAN_ENABLE_ALL:

• reg_value = (0x1 << config->nr_ctm_channels) - 1;
  

• break;
  

• case CTI_GATE_CHAN_DISABLE_ALL:

• reg_value = 0x0;
  

• break;
  

• default:

• err = -EINVAL;
  

• break;
  

• }
• if (err == 0) {

• config->ctigate = reg_value;
  

• if (CTI_PWR_ENA(config))
  

• 	cti_write_single_reg(drvdata, CTIGATE, reg_value);
  

• }
• spin_unlock(&drvdata->spinlock);
• return err;

+}

+int cti_channel_setop(struct device *dev,

•      enum cti_chan_set_op op,
  

•      u32 channel_idx)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• u32 chan_bitmask;
• u32 reg_value;
• u32 reg_offset;
• int err = 0;
• if (channel_idx >= config->nr_ctm_channels)

• return -EINVAL;
  

• chan_bitmask = 0x1 << channel_idx;
• spin_lock(&drvdata->spinlock);
• reg_value = config->ctiappset;
• switch (op) {
• case CTI_CHAN_SET:

• config->ctiappset |= chan_bitmask;
  

• reg_value  = config->ctiappset;
  

• reg_offset = CTIAPPSET;
  

• break;
  

• case CTI_CHAN_CLR:

• config->ctiappset &= ~chan_bitmask;
  

• reg_value = chan_bitmask;
  

• reg_offset = CTIAPPCLEAR;
  

• break;
  

• case CTI_CHAN_PULSE:

• config->ctiappset &= ~chan_bitmask;
  

Should this be "|= chan_bitmask" ?

• reg_value = chan_bitmask;
  

• reg_offset = CTIAPPPULSE;
  

• break;
  

• default:

• err = -EINVAL;
  

• break;
  

• }
• if ((err == 0) && CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, reg_offset, reg_value);
  

• spin_unlock(&drvdata->spinlock);
• return err;

+}

+void cti_write_intack(struct device *dev, u32 ackval) +{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *config = &drvdata->config;
• spin_lock(&drvdata->spinlock);
• /* write if enabled */
• if (CTI_PWR_ENA(config))

• cti_write_single_reg(drvdata, CTIINTACK, ackval);
  

• spin_unlock(&drvdata->spinlock);

+}

/** cti ect operations **/ int cti_enable(struct coresight_device *csdev, void *__unused) { @@ -432,7 +611,12 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* all done - dec pm refcount */ pm_runtime_put(&adev->dev);

• dev_info(dev, "%s: initialized\n", pdata->name);

• if (drvdata->ctidev.cpu >= 0) {

• dev_info(dev, "%s: cti-CPU%d initialized\n", pdata->name,
  

• 	 drvdata->ctidev.cpu);
  

• } else {

• dev_info(dev, "%s: cti-system initialized\n", pdata->name);
  

• } cti_count++; return 0;

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index c1af6cf9c2fe..a5bf59155f62 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -153,6 +153,7 @@ struct cti_device {

• @trig_out_filter: bitfield of out triggers that are blocked if filter
• enabled. Typically this would be dbgreq / restart on a core CTI.
• @trig_filter_enable: 1 if filtering enabled.

• • @xtrig_rchan_sel: channel ID when reading set xtrig info
  • cti software programmable regs:
  • @ctiappset: CTI Software application channel set.

@@ -174,6 +175,7 @@ struct cti_config { u32 trig_out_use; u32 trig_out_filter; int trig_filter_enable;

• u8 xtrig_rchan_sel; /* cti cross trig programmable regs */ u32 ctiappset; u8 ctiinout_sel;

@@ -202,11 +204,51 @@ struct cti_drvdata { struct cti_config config; }; +/*

• • Channel operation types.
• */

+enum cti_chan_op {

• CTI_CHAN_ATTACH,
• CTI_CHAN_DETACH,

+};

+enum cti_trig_dir {

• CTI_TRIG_IN,
• CTI_TRIG_OUT,

+};

+enum cti_chan_gate_op {

• CTI_GATE_CHAN_ENABLE,
• CTI_GATE_CHAN_DISABLE,
• CTI_GATE_CHAN_ENABLE_ALL,
• CTI_GATE_CHAN_DISABLE_ALL,

+};

+enum cti_chan_set_op {

• CTI_CHAN_SET,
• CTI_CHAN_CLR,
• CTI_CHAN_PULSE,

+};

/* private cti driver fns & vars */ extern const struct attribute_group *coresight_cti_groups[];

int cti_add_default_connection(struct cti_drvdata *drvdata); int cti_enable(struct coresight_device *csdev, void *__unused); int cti_disable(struct coresight_device *csdev, void *__unused); +void cti_write_all_hw_regs(struct cti_drvdata *drvdata); +void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); +int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,

• 	enum cti_trig_dir direction, u32 channel_idx,
  

• 	u32 trigger_idx);
  

+int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op,

• 	u32 channel_idx);
  

+int cti_channel_setop(struct device *dev, enum cti_chan_set_op op,

•       u32 channel_idx);
  

+void cti_write_intack(struct device *dev, u32 ackval);

+/* cti powered and enabled */ +#define CTI_PWR_ENA(p_cfg) (p_cfg->hw_enabled && p_cfg->hw_powered) #ifdef CONFIG_OF extern int of_cti_get_hw_data(struct device *dev, diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 8e9e5b6ad866..9b497e2f8725 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -23,10 +23,12 @@ #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 #define CORESIGHT_AUTHSTATUS 0xfb8 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_DEVID 0xfc8 #define CORESIGHT_DEVTYPE 0xfcc

/*

• Coresight device CLAIM protocol.
• See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.

-- 2.20.1

For the patch subject line in this set you can drop "drivers".

On Wed, May 01, 2019 at 09:49:36AM +0100, Mike Leach wrote:

Adds support for CTIs that are implementation defined at design time, and not constrained by v8 architecture.

Changelog descriptions needs to be line wrapped at 75 characters.

These CTIs have no standard connection setup, all the settings have to be defined in the device tree files. The patch creates a set of connections and trigger signals based on the information provided,

Signed-off-by: Mike Leach mike.leach@linaro.org

drivers/hwtracing/coresight/coresight-cti.h | 1 + .../hwtracing/coresight/of_coresight-cti.c | 191 +++++++++++++++++- 2 files changed, 191 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index df40ca2d9548..7342f998f4c5 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -239,6 +239,7 @@ int cti_add_connection_entry(struct cti_drvdata *drvdata, struct cti_trig_grp *out_info, struct coresight_device *csdev, const char *assoc_dev_name); +void cti_free_conn_info(struct cti_drvdata *drvdata); int cti_enable(struct coresight_device *csdev, void *__unused); int cti_disable(struct coresight_device *csdev, void *__unused); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/of_coresight-cti.c b/drivers/hwtracing/coresight/of_coresight-cti.c index ee9a5906dc37..486fa99813ae 100644 --- a/drivers/hwtracing/coresight/of_coresight-cti.c +++ b/drivers/hwtracing/coresight/of_coresight-cti.c @@ -23,10 +23,19 @@ #define NR_V8PE_OUT_SIGS 3 #define NR_V8ETM_INOUT_SIGS 4 +/* CTI device tree trigger connection node keyword */ +#define CTI_DT_CONNS "trig-conns"

/* CTI device tree connection property keywords */ #define CTI_DT_V8ARCH "arm,cti-v8-arch" #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc" #define CTI_DT_CTM_ID "arm,cti-ctm-id" +#define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs" +#define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs" +#define CTI_DT_TRIGIN_TYPES "arm,trig-in-types" +#define CTI_DT_TRIGOUT_TYPES "arm,trig-out-types" +#define CTI_DT_FILTER_OUT_SIGS "arm,trig-filters" +#define CTI_DT_CONN_NAME "arm,trig-conn-name"

I will skip this patch while we don't have a firm idea of how we will represent CTI connections. It may be that we expand the graph binding for data component or come up with a whole new set, like this set does. There are pros and cons with both approach and I want the group to have a dicussion before moving forward.

#ifdef CONFIG_OF @@ -210,6 +219,181 @@ static int of_cti_create_v8_connections(struct cti_drvdata *drvdata, return -ENOMEM; } +static int of_cti_read_trig_group(struct cti_trig_grp **trig_grp_ptr,

• 		  struct device_node *np,
  

• 		  const char *grp_name,
  

• 		  int max_trigs)
  

+{

• int items, err = 0;
• u32 value, pidx;
• struct cti_trig_grp *grp;
• grp = kzalloc(sizeof(struct cti_trig_grp), GFP_KERNEL);
• if (!grp)

• return -ENOMEM;
  

• *trig_grp_ptr = grp;
• items = of_property_count_elems_of_size(np, grp_name, 4);
• /* if the property doesn't exist or has no values, then return

• * an empty connection group
  

• */
  

• if (items < 0)

• return 0;
  

• if (items > max_trigs)

• return -EINVAL;
  

• /* set the number of signals and usage mask */
• for (pidx = 0; pidx < items; pidx++) {

• err = of_property_read_u32_index(np, grp_name, pidx, &value);
  

• if (err)
  

• 	return err;
  

• grp->nr_sigs++;
  

• grp->used_mask |= (0x1 << value);
  

• }
• return 0;

+}

+static int of_cti_read_trig_types(struct cti_trig_grp *trig_grp_ptr,

• 		  struct device_node *np,
  

• 		   const char *type_name)
  

+{

• int items, used = 0, err = 0, nr_sigs;
• u32 value, i;
• /* allocate an array according to number of signals in connection */
• nr_sigs = trig_grp_ptr->nr_sigs;
• if (!nr_sigs)

• return 0;
  

• trig_grp_ptr->sig_types = kzalloc(sizeof(int) * nr_sigs, GFP_KERNEL);
• if (!trig_grp_ptr->sig_types)

• return -ENOMEM;
  

• /* see if any types have been included in the device description */
• items = of_property_count_elems_of_size(np, type_name, 4);
• /*

• * Match type id to signal index,
  

• * too few - default to genio,
  

• * too many - ignore excess.
  

• */
  

• for (i = 0; i < nr_sigs; i++) {

• if (used < items) {
  

• 	err = of_property_read_u32_index(np, type_name,
  

• 					 i, &value);
  

• 	if (!err)
  

• 		trig_grp_ptr->sig_types[i] = value;
  

• 	else
  

• 		trig_grp_ptr->sig_types[i] = CTITRIG_GEN_IO;
  

• 	used++;
  

• }
  

• else
  

• 	trig_grp_ptr->sig_types[i] = CTITRIG_GEN_IO;
  

• }
• return 0;

+}

+static void of_cti_free_trig_grp(struct cti_trig_grp *grp) +{

• if (grp) {

• kfree(grp->sig_types);
  

• kfree(grp);
  

• }

+}

+static int of_cti_create_connection(struct device *dev,

• 		    struct device_node *np,
  

• 		    struct cti_drvdata *drvdata)
  

+{

• struct cti_trig_grp *in = 0, *out = 0, *filter = 0;
• int cpuid = -1, err = 0, trig_max = drvdata->config.nr_trig_max;
• struct device_node *cs_np;
• struct coresight_device *csdev = NULL;
• const char *assoc_name = "unknown";
• char cpu_name_str[16];
• /* look for the signals properties. */
• err = of_cti_read_trig_group(&in, np, CTI_DT_TRIGIN_SIGS, trig_max);
• if (err)

• goto of_create_con_err;
  

• err = of_cti_read_trig_types(in, np, CTI_DT_TRIGIN_TYPES);
• if (err)

• goto of_create_con_err;
  

• err = of_cti_read_trig_group(&out, np, CTI_DT_TRIGOUT_SIGS, trig_max);
• if (err)

• goto of_create_con_err;
  

• err = of_cti_read_trig_types(out, np, CTI_DT_TRIGOUT_TYPES);
• if (err)

• goto of_create_con_err;
  

• err = of_cti_read_trig_group(&filter, np, CTI_DT_FILTER_OUT_SIGS,

• 		     trig_max);
  

• if (err)

• goto of_create_con_err;
  

• /* read the connection name if set - may be overridden by later */
• of_property_read_string(np, CTI_DT_CONN_NAME, &assoc_name);
• /* associated cpu ? */
• cpuid = of_cti_get_cpu(np);
• if (cpuid >= 0) {

• drvdata->ctidev.cpu = cpuid;
  

• scnprintf(cpu_name_str, 16, "cpu%d", cpuid);
  

• assoc_name = cpu_name_str;
  

• } else {

• /* associated device ? */
  

• cs_np = of_parse_phandle(np,  CTI_DT_CSDEV_ASSOC, 0);
  

• if (cs_np) {
  

• 	csdev = of_cti_get_assoc_cs_dev_by_node(cs_np);
  

• 	if (csdev) /* use device name if csdev found */
  

• 		assoc_name = dev_name(&csdev->dev);
  

• 	else  /* otherwise node name for later association */
  

• 		assoc_name = cs_np->full_name;
  

• 	of_node_put(cs_np);
  

• }
  

• }
• /* set up a connection */
• err = cti_add_connection_entry(drvdata, in, out, csdev, assoc_name);
• if (err)

• goto of_create_con_err;
  

• /* note any filter info */
• drvdata->config.trig_out_filter |= filter->used_mask;
• kfree(filter);
• return err;

+of_create_con_err:

• of_cti_free_trig_grp(in);
• of_cti_free_trig_grp(out);
• of_cti_free_trig_grp(filter);
• return err;

+}

+static int of_cti_create_impdef_connections(struct device *dev,

•       struct device_node *np,
  

•       struct cti_drvdata *drvdata)
  

+{

• int rc = 0;
• struct device_node *nc = NULL;
• for_each_child_of_node(np, nc) {

• if (of_node_cmp(nc->name, CTI_DT_CONNS) != 0)
  

• 	continue;
  

• rc = of_cti_create_connection(dev, nc, drvdata);
  

• if (rc != 0)
  

• 	goto of_cti_impdef_create_err;
  

• }
• return rc;

+of_cti_impdef_create_err:

• /* last create should have freed its mem - unpick previous */
• cti_free_conn_info(drvdata);
• return rc;

+}

/* get the hardware configuration & connection data. */ int of_cti_get_hw_data(struct device *dev, struct device_node *np, @@ -221,9 +405,14 @@ int of_cti_get_hw_data(struct device *dev, /* get any CTM ID - defaults to 0 */ of_property_read_u32(np, CTI_DT_CTM_ID, &cti_dev->ctm_id);

• /* check for a v8 architectural CTI device */

• /*

• * Check for a v8 architectural CTI device,
  

• * otherwise implementation defined.
  

• */
  

  if (of_property_read_bool(np, CTI_DT_V8ARCH)) rc = of_cti_create_v8_connections(drvdata, np);
• else

• rc = of_cti_create_impdef_connections(dev, np, drvdata);
  

/* if no connections, just add a single default based on max IN-OUT */ if (!rc && (cti_dev->nr_trig_con == 0)) -- 2.20.1

On Wed, May 01, 2019 at 09:49:38AM +0100, Mike Leach wrote:

Dynamically adds sysfs attributes for all connections defined in the CTI.

Each connection has _name, _trgin_type, _trgout_type, _trgin_sig and _trgout_sig, preceded by a connection index (e.g. 0_name is the name of connection 0).

Additionally each device has a nr_cons and trigout_filtered parameter. This allows clients to explore the connection and trigger signal details without needing to refer to device tree or specification of the device.

Standardised type information is provided for certain common functions - e.g. snk_full for a trigger from a sink indicating full. Otherwise type defaults to genio.

I will skip this patch until we find a way to uniformally represent connection information for signal and data components.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-cti-sysfs.c | 338 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-cti.c | 11 + drivers/hwtracing/coresight/coresight-cti.h | 4 + 3 files changed, 353 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index ff8dad02a779..e4b23e291114 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -883,6 +883,343 @@ static struct attribute *coresight_cti_channel_attrs[] = { NULL, }; +/* Create the connections group attrs dynamically */

+/* group is static - .attrs will be built dynamically */ +static struct attribute_group coresight_cti_conns_group = {

• .name = "connections",

+};

+/*

• *Each connection has dynamic name, trigin/out sigs/types attrs,
• • • each device has static nr conns + filter attr
• */

+static ssize_t trigout_filtered_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• int b_sz = PAGE_SIZE;
• u32 sig_mask;
• int sig_idx, used = 0, nr_trig_max = cfg->nr_trig_max;
• if (cfg->trig_out_filter) {

• sig_mask = 0x1;
  

• for (sig_idx = 0; sig_idx < nr_trig_max; sig_idx++) {
  

• 	if (sig_mask & cfg->trig_out_filter) {
  

• 		used += scnprintf(buf+used, b_sz-used, "%d ",
  

• 				 sig_idx);
  

• 	}
  

• 	sig_mask <<= 1;
  

• }
  

• used += scnprintf(buf+used, b_sz-used, "\n");
  

• } else

• used += scnprintf(buf, b_sz, "none\n");
  

• return used;

+} +static DEVICE_ATTR_RO(trigout_filtered);

+static ssize_t nr_cons_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.nr_trig_con);

+} +static DEVICE_ATTR_RO(nr_cons);

+/* static attrs - 2 + null terminator */ +#define CTI_SYSFS_CONS_ST_ATTR 3 +/* dynamic attr - per connection */ +#define CTI_SYSFS_CONS_DYN_ATTR 5

+static ssize_t con_name_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr;
• struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
• return scnprintf(buf, PAGE_SIZE, "%s\n", con->con_dev_name);

+}

+static ssize_t trigin_sig_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr;
• struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• u32 sig_mask;
• int sig_idx, used = 0, b_sz = PAGE_SIZE;
• sig_mask = 0x1;
• for (sig_idx = 0; sig_idx < cfg->nr_trig_max; sig_idx++) {

• if (sig_mask & con->con_in->used_mask) {
  

• 	used += scnprintf(buf+used, b_sz-used, "%d ",
  

• 			  sig_idx);
  

• }
  

• sig_mask <<= 1;
  

• }
• used += scnprintf(buf+used, b_sz-used, "\n");
• return used;

+}

+static ssize_t trigout_sig_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr;
• struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
• struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
• struct cti_config *cfg = &drvdata->config;
• u32 sig_mask;
• int sig_idx, used = 0, b_sz = PAGE_SIZE;
• sig_mask = 0x1;
• for (sig_idx = 0; sig_idx < cfg->nr_trig_max; sig_idx++) {

• if (sig_mask & con->con_out->used_mask) {
  

• 	used += scnprintf(buf+used, b_sz-used, "%d ",
  

• 			  sig_idx);
  

• }
  

• sig_mask <<= 1;
  

• }
• used += scnprintf(buf+used, b_sz-used, "\n");
• return used;

+}

+/* convert a sig type id to a name */ +static const char * +cti_sig_type_name(struct cti_trig_con *con, int used_count, bool in) +{

• static const char * const sig_type_names[] = {

• "genio", "intreq", "intack", "haltreq", "restartreq",
  

• "pe_edbgreq", "pe_dbgrestart", "pe_ctiirq", "pe_pmuirq",
  

• "pe_dbgtrigger", "etm_extout",  "etm_extin", "snk_full",
  

• "snk_acqcomp", "snk_flushcomp", "snk_flushin", "snk_trigin",
  

• "stm_asyncout", "stm_tout_spte", "stm_tout_sw", "stm_tout_hete",
  

• "stm_hwevent", "ela_tstart", "ela_tstop", "ela_dbgreq",
  

• };
• int idx = 0;
• struct cti_trig_grp *grp = in ? con->con_in : con->con_out;
• if (grp->sig_types) {

• if (used_count < grp->nr_sigs)
  

• 	idx = grp->sig_types[used_count];
  

• }
• return sig_type_names[idx];

+}

+static ssize_t trigin_type_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr;
• struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
• int sig_idx, used = 0, b_sz = PAGE_SIZE;
• const char *name;
• for (sig_idx = 0; sig_idx < con->con_in->nr_sigs; sig_idx++) {

• name = cti_sig_type_name(con, sig_idx, true);
  

• used += scnprintf(buf+used, b_sz-used, "%s ", name);
  

• }
• used += scnprintf(buf+used, b_sz-used, "\n");
• return used;

+}

+static ssize_t trigout_type_show(struct device *dev,

• 	 struct device_attribute *attr,
  

• 	 char *buf)
  

+{

• struct dev_ext_attribute *ext_attr = (struct dev_ext_attribute *)attr;
• struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
• int sig_idx, used = 0, b_sz = PAGE_SIZE;
• const char *name;
• for (sig_idx = 0; sig_idx < con->con_out->nr_sigs; sig_idx++) {

• name = cti_sig_type_name(con, sig_idx, false);
  

• used += scnprintf(buf+used, b_sz-used, "%s ", name);
  

• }
• used += scnprintf(buf+used, b_sz-used, "\n");
• return used;

+}

+typedef ssize_t (*p_show_fn)(struct device *dev, struct device_attribute *attr,

• 	     char *buf);
  

+enum cti_conn_attr_type {

• CTI_CON_ATTR_NAME,
• CTI_CON_ATTR_TRIGIN_SIG,
• CTI_CON_ATTR_TRIGOUT_SIG,
• CTI_CON_ATTR_TRIGIN_TYPES,
• CTI_CON_ATTR_TRIGOUT_TYPES

+};

+static p_show_fn show_fns[] = {

• con_name_show,
• trigin_sig_show,
• trigout_sig_show,
• trigin_type_show,
• trigout_type_show,

+};

+static const char * const base_names[] = {

• "_name",
• "_trgin_sig",
• "_trgout_sig",
• "_trgin_type",
• "_trgout_type",

+};

+struct dev_ext_attribute * +cti_create_con_sysfs_attr(int con_idx, enum cti_conn_attr_type attr_type) +{

• struct dev_ext_attribute *dev_ext_attr = 0;
• char *name = 0;
• dev_ext_attr = kzalloc(sizeof(struct dev_ext_attribute), GFP_KERNEL);
• if (dev_ext_attr) {

• name = kzalloc(sizeof(char) * 16, GFP_KERNEL);
  

• if (name) {
  

• 	/* fill out the underlying attribute struct */
  

• 	sprintf(name, "%d%s", con_idx, base_names[attr_type]);
  

• 	dev_ext_attr->attr.attr.name = name;
  

• 	dev_ext_attr->attr.attr.mode = 0444;
  

• 	/* now the device_attribute struct */
  

• 	dev_ext_attr->attr.show = show_fns[attr_type];
  

• } else {
  

• 	kfree(dev_ext_attr);
  

• 	dev_ext_attr = 0;
  

• }
  

• }
• return dev_ext_attr;

+}

+int cti_create_con_attr_set(int con_idx, int *next_attr_idx,

• 	    struct cti_device *ctidev,
  

• 	    struct cti_trig_con *con)
  

+{

• struct dev_ext_attribute *dev_ext_attr;
• int attr_idx = *next_attr_idx;
• dev_ext_attr = cti_create_con_sysfs_attr(con_idx, CTI_CON_ATTR_NAME);
• if (!dev_ext_attr)

• goto create_con_attr_err;
  

• dev_ext_attr->var = con;
• ctidev->con_attrs[attr_idx++] = dev_ext_attr;
• if (con->con_in->nr_sigs > 0) {

• dev_ext_attr =
  

• 	cti_create_con_sysfs_attr(con_idx,
  

• 				  CTI_CON_ATTR_TRIGIN_SIG);
  

• if (!dev_ext_attr)
  

• 	goto create_con_attr_err;
  

• dev_ext_attr->var = con;
  

• ctidev->con_attrs[attr_idx++] = dev_ext_attr;
  

• dev_ext_attr =
  

• 	cti_create_con_sysfs_attr(con_idx,
  

• 				  CTI_CON_ATTR_TRIGIN_TYPES);
  

• if (!dev_ext_attr)
  

• 	goto create_con_attr_err;
  

• dev_ext_attr->var = con;
  

• ctidev->con_attrs[attr_idx++] = dev_ext_attr;
  

• }
• if (con->con_in->nr_sigs > 0) {

• dev_ext_attr =
  

• 	cti_create_con_sysfs_attr(con_idx,
  

• 				  CTI_CON_ATTR_TRIGOUT_SIG);
  

• if (!dev_ext_attr)
  

• 	goto create_con_attr_err;
  

• dev_ext_attr->var = con;
  

• ctidev->con_attrs[attr_idx++] = dev_ext_attr;
  

• dev_ext_attr =
  

• 	cti_create_con_sysfs_attr(con_idx,
  

• 				  CTI_CON_ATTR_TRIGOUT_TYPES);
  

• if (!dev_ext_attr)
  

• 	goto create_con_attr_err;
  

• dev_ext_attr->var = con;
  

• ctidev->con_attrs[attr_idx++] = dev_ext_attr;
  

• }
• *next_attr_idx = attr_idx;
• return 0;

+create_con_attr_err:

• cti_destroy_cons_sysfs(ctidev);
• return -ENOMEM;

+}

+int cti_create_cons_sysfs(struct cti_drvdata *drvdata) +{

• struct cti_device *ctidev = &drvdata->ctidev;
• int err = 0, n_attrs = 0, con_idx = 0;
• int next_attr_idx = CTI_SYSFS_CONS_ST_ATTR - 1;
• struct cti_trig_con *tc;
• n_attrs = CTI_SYSFS_CONS_ST_ATTR +

• (CTI_SYSFS_CONS_DYN_ATTR * ctidev->nr_trig_con);
  

• ctidev->con_attrs =

• kcalloc(n_attrs, sizeof(struct dev_ext_attribute *),
  

• 	GFP_KERNEL);
  

• if (ctidev->con_attrs != 0) {

• ctidev->con_attrs[0] =	(struct dev_ext_attribute *)
  

• 	&dev_attr_trigout_filtered.attr;
  

• ctidev->con_attrs[1] = (struct dev_ext_attribute *)
  

• 	&dev_attr_nr_cons.attr;
  

• /* add dynamic set for each connection */
  

• list_for_each_entry(tc,  &ctidev->trig_cons, node) {
  

• 	err = cti_create_con_attr_set(con_idx++,
  

• 				      &next_attr_idx,
  

• 				      ctidev,
  

• 				      tc);
  

• 	/* if create con fails it will free all prior cons */
  

• 	if (err)
  

• 		return err;
  

• }
  

• coresight_cti_conns_group.attrs =
  

• 	(struct attribute **)ctidev->con_attrs;
  

• } else

• err = -ENOMEM;
  

• return err;

+}

+void cti_destroy_cons_sysfs(struct cti_device *ctidev) +{

• int n_attrs = CTI_SYSFS_CONS_ST_ATTR +

• (CTI_SYSFS_CONS_DYN_ATTR * ctidev->nr_trig_con);
  

• int dyn_idx = CTI_SYSFS_CONS_ST_ATTR - 1;
• bool eol = false;
• struct dev_ext_attribute *dev_ext_attr = 0;
• if (ctidev->con_attrs) {

• while (!eol && (dyn_idx < n_attrs)) {
  

• 	dev_ext_attr = ctidev->con_attrs[dyn_idx];
  

• 	if (dev_ext_attr) {
  

• 		kfree(dev_ext_attr->attr.attr.name);
  

• 		kfree(dev_ext_attr);
  

• 	} else
  

• 		eol = true;
  

• 	dyn_idx++;
  

• }
  

• kfree(ctidev->con_attrs);
  

• ctidev->con_attrs = 0;
  

• }

+}

/* attribute and group sysfs tables. */ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, @@ -908,5 +1245,6 @@ const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_mgmt_group, &coresight_cti_regs_group, &coresight_cti_channels_group,

• &coresight_cti_conns_group, NULL,

}; diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 6d452ca3725c..e0192fd50804 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -671,6 +671,14 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) /* setup cpu related CTI devices, otherwise assume powered */ drvdata->config.hw_powered = true;

• /* create dynamic attributes for connections */
• ret = cti_create_cons_sysfs(drvdata);
• if (ret) {

• pr_err("%s: create dynamic sysfs entries failed\n",
  

•        pdata->name);
  

• goto err_out;
  

• }
• /* set up coresight component description */ cti_desc.pdata = pdata; cti_desc.type = CORESIGHT_DEV_TYPE_ECT;

@@ -746,6 +754,9 @@ void cti_device_release(struct device *dev) if (drvdata->ctidev.cpu >= 0) cti_cpu_drv[drvdata->ctidev.cpu] = 0;

• /* clear the dynamic sysfs associate with connections */
• cti_destroy_cons_sysfs(&drvdata->ctidev);
• /* clear the connection list items */ cti_free_conn_info(drvdata);

diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 7342f998f4c5..2a3557bfcd16 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -125,6 +125,7 @@ struct cti_trig_con {

•      assumed there is a single CTM per SoC, ID 0).
  

• @trig_cons: list of connections to this device.
• @cpu: CPU ID if associated with CPU, -1 otherwise.

• • @con_attrs: Dymanic sysfs attributes created to display connection info.
  */

struct cti_device { @@ -132,6 +133,7 @@ struct cti_device { u32 ctm_id; struct list_head trig_cons; int cpu;

• struct dev_ext_attribute **con_attrs;

}; /** @@ -252,6 +254,8 @@ int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op, int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, u32 channel_idx); void cti_write_intack(struct device *dev, u32 ackval); +int cti_create_cons_sysfs(struct cti_drvdata *drvdata); +void cti_destroy_cons_sysfs(struct cti_device *ctidev); /* cti powered and enabled */

#define CTI_PWR_ENA(p_cfg) (p_cfg->hw_enabled && p_cfg->hw_powered)

2.20.1