Decoder provides last instruction related information, these information can be used for trace analysis; specifically we can get to know what kind of branch instruction has been executed, mainly the information are contained in three element fields:

last_i_type: this is significant type for waypoint calculation, it indicates the last instruction is one of immediate branch instruction, indirect branch instruction, instruction barrier (ISB), or data barrier (DSB/DMB).

last_i_subtype: this is used for instruction sub type, it can be branch with link, ARMv8 return instruction, ARMv8 eret instruction (return from exception), or ARMv7 instruction which could imply return (e.g. MOV PC, LR; POP { ,PC}).

last_instr_cond: it indicates if the last instruction was conditional.

But these three fields are not saved into cs_etm_packet struct, thus cs-etm layer don't know related information and cannot generate sample flags for branch instructions.

This patch add corresponding three new fields in cs_etm_packet struct and save related value into the packet structure, it is preparation for supporting sample flags.

Signed-off-by: Leo Yan leo.yan@linaro.org --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 +++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 3 +++ 2 files changed, 12 insertions(+)

diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 8c155575c6c5..8a19310500d9 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -290,6 +290,9 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder) decoder->packet_buffer[i].instr_count = 0; decoder->packet_buffer[i].last_instr_taken_branch = false; decoder->packet_buffer[i].last_instr_size = 0; + decoder->packet_buffer[i].last_instr_type = 0; + decoder->packet_buffer[i].last_instr_subtype = 0; + decoder->packet_buffer[i].last_instr_cond = 0; decoder->packet_buffer[i].cpu = INT_MIN; } } @@ -323,6 +326,9 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_buffer[et].instr_count = 0; decoder->packet_buffer[et].last_instr_taken_branch = false; decoder->packet_buffer[et].last_instr_size = 0; + decoder->packet_buffer[et].last_instr_type = 0; + decoder->packet_buffer[et].last_instr_subtype = 0; + decoder->packet_buffer[et].last_instr_cond = 0;

if (decoder->packet_count == MAX_BUFFER - 1) return OCSD_RESP_WAIT; @@ -366,6 +372,9 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder, packet->start_addr = elem->st_addr; packet->end_addr = elem->en_addr; packet->instr_count = elem->num_instr_range; + packet->last_instr_type = elem->last_i_type; + packet->last_instr_subtype = elem->last_i_subtype; + packet->last_instr_cond = elem->last_instr_cond;

switch (elem->last_i_type) { case OCSD_INSTR_BR: diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index a6407d41598f..7cdd6a9c68a7 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -43,6 +43,9 @@ struct cs_etm_packet { u64 start_addr; u64 end_addr; u32 instr_count; + u32 last_instr_type; + u32 last_instr_subtype; + u8 last_instr_cond; u8 last_instr_taken_branch; u8 last_instr_size; int cpu;

In the middle of trace stream, it might be interrupted thus the trace data is not continuous, the trace stream firstly is ended for previous trace block and restarted for next block.

To display related information for showing trace is restarted, this patch set sample flags for trace discontinuity:

- If one discontinuity packet is coming, append flag PERF_IP_FLAG_TRACE_END to the previous packet to indicate the trace has been ended; - If one instruction packet is following discontinuity packet, this instruction packet is the first one packet to restarting trace. So set flag PERF_IP_FLAG_TRACE_START to discontinuity packet, this flag will be used to generate sample when connect with the sequential instruction packet.

Signed-off-by: Leo Yan leo.yan@linaro.org --- tools/perf/util/cs-etm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index d05cac5295f1..1aa29633ce77 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1111,6 +1111,7 @@ static int cs_etm__end_block(struct cs_etm_queue *etmq) static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) { struct cs_etm_packet *packet = etmq->packet; + struct cs_etm_packet *prev_packet = etmq->prev_packet;

switch (packet->sample_type) { case CS_ETM_RANGE: @@ -1170,8 +1171,26 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) packet->last_instr_subtype == OCSD_S_INSTR_V8_RET) packet->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_RETURN; + + /* + * Decoder might insert a discontinuity in the middle of + * instruction packets, fixup prev_packet with flag + * PERF_IP_FLAG_TRACE_BEGIN to indicate restarting trace. + */ + if (prev_packet->sample_type == CS_ETM_DISCONTINUITY) + prev_packet->flags |= PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_TRACE_BEGIN; break; case CS_ETM_DISCONTINUITY: + /* + * The trace is discontinuous, if the previous packet is + * instruction packet, set flag PERF_IP_FLAG_TRACE_END + * for previous packet. + */ + if (prev_packet->sample_type == CS_ETM_RANGE) + prev_packet->flags |= PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_TRACE_END; + break; case CS_ETM_EXCEPTION: case CS_ETM_EXCEPTION_RET: case CS_ETM_EMPTY:

If packet processing wants to know the packet is bound with which ETM version, it needs to access metadata to decide that based on metadata magic number; but we cannot simply to use CPU logic ID number as index to access metadata sequential array, especially when system have hotplugged off CPUs, the metadata array are only allocated for online CPUs but not offline CPUs, so the CPU logic number doesn't match with its index in the array.

For this reason, a reliable way for accessing metadata array is to use traceID to find associated metadata; by accessing metadata content we can know not only the CPU number but also for ETM version, which can be used for sequential change for setting sample flags for exception packets.

This patch is to change tuple from traceID-CPU# to traceID-metadata, thus it can use the tuple to retrieve metadata pointer according to traceID.

For safe accessing metadata fields, this patch provides helper function cs_etm__get_cpu() which is used to return CPU number according to traceID; cs_etm_decoder__buffer_packet() is the first consumer for this helper function.

Signed-off-by: Leo Yan leo.yan@linaro.org --- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 8 ++-- tools/perf/util/cs-etm.c | 37 ++++++++++++++++--- tools/perf/util/cs-etm.h | 4 +- 3 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 294efa76c9e3..cdd38ffd10d2 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -305,14 +305,12 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, enum cs_etm_sample_type sample_type) { u32 et = 0; - struct int_node *inode = NULL; + int cpu;

if (decoder->packet_count >= MAX_BUFFER - 1) return OCSD_RESP_FATAL_SYS_ERR;

- /* Search the RB tree for the cpu associated with this traceID */ - inode = intlist__find(traceid_list, trace_chan_id); - if (!inode) + if (cs_etm__get_cpu(trace_chan_id, &cpu) < 0) return OCSD_RESP_FATAL_SYS_ERR;

et = decoder->tail; @@ -322,7 +320,7 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder,

decoder->packet_buffer[et].sample_type = sample_type; decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN; - decoder->packet_buffer[et].cpu = *((int *)inode->priv); + decoder->packet_buffer[et].cpu = cpu; decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[et].instr_count = 0; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 1aa29633ce77..e89989fe0a5c 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -97,6 +97,20 @@ static u32 cs_etm__get_v7_protocol_version(u32 etmidr) return CS_ETM_PROTO_ETMV3; }

+int cs_etm__get_cpu(u8 trace_chan_id, int *cpu) +{ + struct int_node *inode; + u64 *metadata; + + inode = intlist__find(traceid_list, trace_chan_id); + if (!inode) + return -EINVAL; + + metadata = inode->priv; + *cpu = (int)metadata[CS_ETM_CPU]; + return 0; +} + static void cs_etm__packet_dump(const char *pkt_string) { const char *color = PERF_COLOR_BLUE; @@ -252,7 +266,7 @@ static void cs_etm__free(struct perf_session *session) cs_etm__free_events(session); session->auxtrace = NULL;

- /* First remove all traceID/CPU# nodes for the RB tree */ + /* First remove all traceID/metadata nodes for the RB tree */ intlist__for_each_entry_safe(inode, tmp, traceid_list) intlist__remove(traceid_list, inode); /* Then the RB tree itself */ @@ -1519,9 +1533,20 @@ int cs_etm__process_auxtrace_info(union perf_event *event, 0xffffffff);

/* - * Create an RB tree for traceID-CPU# tuple. Since the conversion has - * to be made for each packet that gets decoded, optimizing access in - * anything other than a sequential array is worth doing. + * Create an RB tree for traceID-metadata tuple. + * + * The conversion between traceID and CPU logic ID number has to + * be made for each packet that gets decoded: firstly retrieve + * metadata pointer from trace ID by using traceID-metadata tuple, + * then read CPU logic ID number in metadata. + * + * It's not safe to directly use CPU logic ID number as index to + * access metadata sequential array, e.g. when system have + * hotplugged out CPUs, the metadata array are only allocated for + * online CPUs but not offline CPUs, thus the CPU logic number is + * not consistent with its index in the arrary. For this reason, + * we need to fallback to use TraceID-metadata tuple as a reliable + * method to access metadata. */ traceid_list = intlist__new(NULL); if (!traceid_list) { @@ -1587,8 +1612,8 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = -EINVAL; goto err_free_metadata; } - /* All good, associate the traceID with the CPU# */ - inode->priv = &metadata[j][CS_ETM_CPU]; + /* All good, associate the traceID with the metadata pointer */ + inode->priv = metadata[j]; }

/* diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 37f8d48179ca..5d70d10f3907 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -53,7 +53,7 @@ enum { CS_ETMV4_PRIV_MAX, };

-/* RB tree for quick conversion between traceID and CPUs */ +/* RB tree for quick conversion between traceID and metadata pointers */ struct intlist *traceid_list;

#define KiB(x) ((x) * 1024) @@ -78,4 +78,6 @@ cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, } #endif

+int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); + #endif

The exception taken and returning are typical flow for instruction jump but it needs to be handled with exception packets. This patch is to set sample flags for exception packet.

Since the exception packet contains the exception number, according to the exception number this patch makes decision for belonging to which exception types.

The decoder have defined different exception number for ETMv3 and ETMv4 separately, hence this patch needs firstly decide the ETM version by using the metadata magic number, and this patch adds helper function cs_etm__get_magic() for easily getting magic number.

Based on different ETM version, the exception packet contains the exception number, according to the exception number this patch makes decision for the exception belonging to which exception types.

In this patch, it introduces helper function cs_etm__is_svc_instr(); for ETMv4 CS_ETMV4_EXC_CALL covers SVC, SMC and HVC cases in the single exception number, thus need to use cs_etm__is_svc_instr() to decide an exception taken for system call.

Reviewed-by: Robert Walker robert.walker@arm.com Signed-off-by: Leo Yan leo.yan@linaro.org --- tools/perf/util/cs-etm.c | 215 +++++++++++++++++++++++++++++++++++++++ tools/perf/util/cs-etm.h | 44 ++++++++ 2 files changed, 259 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index e89989fe0a5c..052805de6513 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -97,6 +97,20 @@ static u32 cs_etm__get_v7_protocol_version(u32 etmidr) return CS_ETM_PROTO_ETMV3; }

+static int cs_etm__get_magic(u8 trace_chan_id, u64 *magic) +{ + struct int_node *inode; + u64 *metadata; + + inode = intlist__find(traceid_list, trace_chan_id); + if (!inode) + return -EINVAL; + + metadata = inode->priv; + *magic = metadata[CS_ETM_MAGIC]; + return 0; +} + int cs_etm__get_cpu(u8 trace_chan_id, int *cpu) { struct int_node *inode; @@ -1122,10 +1136,174 @@ static int cs_etm__end_block(struct cs_etm_queue *etmq) return 0; }

+static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq, + struct cs_etm_packet *packet, + u64 end_addr) +{ + u16 instr16; + u32 instr32; + u64 addr; + + switch (packet->isa) { + case CS_ETM_ISA_T32: + /* + * The SVC of T32 is defined in ARM DDI 0487D.a, F5.1.247: + * + * b'15 b'8 + * +-----------------+--------+ + * | 1 1 0 1 1 1 1 1 | imm8 | + * +-----------------+--------+ + * + * According to the specifiction, it only defines SVC for T32 + * with 16 bits instruction and has no definition for 32bits; + * so below only read 2 bytes as instruction size for T32. + */ + addr = end_addr - 2; + cs_etm__mem_access(etmq, addr, sizeof(instr16), (u8 *)&instr16); + if ((instr16 & 0xFF00) == 0xDF00) + return true; + + break; + case CS_ETM_ISA_A32: + /* + * The SVC of A32 is defined in ARM DDI 0487D.a, F5.1.247: + * + * b'31 b'28 b'27 b'24 + * +---------+---------+-------------------------+ + * | !1111 | 1 1 1 1 | imm24 | + * +---------+---------+-------------------------+ + */ + addr = end_addr - 4; + cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32); + if ((instr32 & 0x0F000000) == 0x0F000000 && + (instr32 & 0xF0000000) != 0xF0000000) + return true; + + break; + case CS_ETM_ISA_A64: + /* + * The SVC of A64 is defined in ARM DDI 0487D.a, C6.2.294: + * + * b'31 b'21 b'4 b'0 + * +-----------------------+---------+-----------+ + * | 1 1 0 1 0 1 0 0 0 0 0 | imm16 | 0 0 0 0 1 | + * +-----------------------+---------+-----------+ + */ + addr = end_addr - 4; + cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32); + if ((instr32 & 0xFFE0001F) == 0xd4000001) + return true; + + break; + case CS_ETM_ISA_UNKNOWN: + default: + break; + } + + return false; +} + +static bool cs_etm__is_syscall(struct cs_etm_queue *etmq, u64 magic) +{ + struct cs_etm_packet *packet = etmq->packet; + struct cs_etm_packet *prev_packet = etmq->prev_packet; + + if (magic == __perf_cs_etmv3_magic) + if (packet->exception_number == CS_ETMV3_EXC_SVC) + return true; + + /* + * ETMv4 exception type CS_ETMV4_EXC_CALL covers SVC, SMC and + * HVC cases; need to check if it's SVC instruction based on + * packet address. + */ + if (magic == __perf_cs_etmv4_magic) { + if (packet->exception_number == CS_ETMV4_EXC_CALL && + cs_etm__is_svc_instr(etmq, prev_packet, + prev_packet->end_addr)) + return true; + } + + return false; +} + +static bool cs_etm__is_async_exception(struct cs_etm_queue *etmq, u64 magic) +{ + struct cs_etm_packet *packet = etmq->packet; + + if (magic == __perf_cs_etmv3_magic) + if (packet->exception_number == CS_ETMV3_EXC_DEBUG_HALT || + packet->exception_number == CS_ETMV3_EXC_ASYNC_DATA_ABORT || + packet->exception_number == CS_ETMV3_EXC_PE_RESET || + packet->exception_number == CS_ETMV3_EXC_IRQ || + packet->exception_number == CS_ETMV3_EXC_FIQ) + return true; + + if (magic == __perf_cs_etmv4_magic) + if (packet->exception_number == CS_ETMV4_EXC_RESET || + packet->exception_number == CS_ETMV4_EXC_DEBUG_HALT || + packet->exception_number == CS_ETMV4_EXC_SYSTEM_ERROR || + packet->exception_number == CS_ETMV4_EXC_INST_DEBUG || + packet->exception_number == CS_ETMV4_EXC_DATA_DEBUG || + packet->exception_number == CS_ETMV4_EXC_IRQ || + packet->exception_number == CS_ETMV4_EXC_FIQ) + return true; + + return false; +} + +static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq, u64 magic) +{ + struct cs_etm_packet *packet = etmq->packet; + struct cs_etm_packet *prev_packet = etmq->prev_packet; + + if (magic == __perf_cs_etmv3_magic) + if (packet->exception_number == CS_ETMV3_EXC_SMC || + packet->exception_number == CS_ETMV3_EXC_HYP || + packet->exception_number == CS_ETMV3_EXC_JAZELLE_THUMBEE || + packet->exception_number == CS_ETMV3_EXC_UNDEFINED_INSTR || + packet->exception_number == CS_ETMV3_EXC_PREFETCH_ABORT || + packet->exception_number == CS_ETMV3_EXC_DATA_FAULT || + packet->exception_number == CS_ETMV3_EXC_GENERIC) + return true; + + if (magic == __perf_cs_etmv4_magic) { + if (packet->exception_number == CS_ETMV4_EXC_TRAP || + packet->exception_number == CS_ETMV4_EXC_ALIGNMENT || + packet->exception_number == CS_ETMV4_EXC_INST_FAULT || + packet->exception_number == CS_ETMV4_EXC_DATA_FAULT) + return true; + + /* + * For CS_ETMV4_EXC_CALL, except SVC other instructions + * (SMC, HVC) are taken as sync exceptions. + */ + if (packet->exception_number == CS_ETMV4_EXC_CALL && + !cs_etm__is_svc_instr(etmq, prev_packet, + prev_packet->end_addr)) + return true; + + /* + * ETMv4 has 5 bits for exception number; if the numbers + * are in the range ( CS_ETMV4_EXC_FIQ, CS_ETMV4_EXC_END ] + * they are implementation defined exceptions. + * + * For this case, simply take it as sync exception. + */ + if (packet->exception_number > CS_ETMV4_EXC_FIQ && + packet->exception_number <= CS_ETMV4_EXC_END) + return true; + } + + return false; +} + static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) { struct cs_etm_packet *packet = etmq->packet; struct cs_etm_packet *prev_packet = etmq->prev_packet; + u64 magic; + int ret;

switch (packet->sample_type) { case CS_ETM_RANGE: @@ -1206,6 +1384,43 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) PERF_IP_FLAG_TRACE_END; break; case CS_ETM_EXCEPTION: + ret = cs_etm__get_magic(packet->trace_chan_id, &magic); + if (ret) + return ret; + + /* The exception is for system call. */ + if (cs_etm__is_syscall(etmq, magic)) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_SYSCALLRET; + /* + * The exceptions are triggered by external signals from bus, + * interrupt controller, debug module, PE reset or halt. + */ + else if (cs_etm__is_async_exception(etmq, magic)) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_ASYNC | + PERF_IP_FLAG_INTERRUPT; + /* + * Otherwise, exception is caused by trap, instruction & + * data fault, or alignment errors. + */ + else if (cs_etm__is_sync_exception(etmq, magic)) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_INTERRUPT; + + /* + * When the exception packet is inserted, since exception + * packet is not used standalone for generating samples + * and it's affiliation to the previous instruction range + * packet; so set previous range packet flags to tell perf + * it is an exception taken branch. + */ + if (prev_packet->sample_type == CS_ETM_RANGE) + prev_packet->flags = packet->flags; + break; case CS_ETM_EXCEPTION_RET: case CS_ETM_EMPTY: default: diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 5d70d10f3907..7bd16ea8a62d 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -53,6 +53,50 @@ enum { CS_ETMV4_PRIV_MAX, };

+/* + * ETMv3 exception encoding number: + * See Embedded Trace Macrocell spcification (ARM IHI 0014Q) + * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors. + */ +enum { + CS_ETMV3_EXC_NONE = 0, + CS_ETMV3_EXC_DEBUG_HALT = 1, + CS_ETMV3_EXC_SMC = 2, + CS_ETMV3_EXC_HYP = 3, + CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, + CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, + CS_ETMV3_EXC_PE_RESET = 8, + CS_ETMV3_EXC_UNDEFINED_INSTR = 9, + CS_ETMV3_EXC_SVC = 10, + CS_ETMV3_EXC_PREFETCH_ABORT = 11, + CS_ETMV3_EXC_DATA_FAULT = 12, + CS_ETMV3_EXC_GENERIC = 13, + CS_ETMV3_EXC_IRQ = 14, + CS_ETMV3_EXC_FIQ = 15, +}; + +/* + * ETMv4 exception encoding number: + * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D) + * table 6-12 Possible values for the TYPE field in an Exception instruction + * trace packet, for ARMv7-A/R and ARMv8-A/R PEs. + */ +enum { + CS_ETMV4_EXC_RESET = 0, + CS_ETMV4_EXC_DEBUG_HALT = 1, + CS_ETMV4_EXC_CALL = 2, + CS_ETMV4_EXC_TRAP = 3, + CS_ETMV4_EXC_SYSTEM_ERROR = 4, + CS_ETMV4_EXC_INST_DEBUG = 6, + CS_ETMV4_EXC_DATA_DEBUG = 7, + CS_ETMV4_EXC_ALIGNMENT = 10, + CS_ETMV4_EXC_INST_FAULT = 11, + CS_ETMV4_EXC_DATA_FAULT = 12, + CS_ETMV4_EXC_IRQ = 14, + CS_ETMV4_EXC_FIQ = 15, + CS_ETMV4_EXC_END = 31, +}; + /* RB tree for quick conversion between traceID and metadata pointers */ struct intlist *traceid_list;

On Sat, Jan 19, 2019 at 09:43:40AM +0800, Leo Yan wrote:

Decoder provides last instruction related information, these information can be used for trace analysis; specifically we can get to know what kind of branch instruction has been executed, mainly the information are contained in three element fields:

last_i_type: this is significant type for waypoint calculation, it indicates the last instruction is one of immediate branch instruction, indirect branch instruction, instruction barrier (ISB), or data barrier (DSB/DMB).

last_i_subtype: this is used for instruction sub type, it can be branch with link, ARMv8 return instruction, ARMv8 eret instruction (return from exception), or ARMv7 instruction which could imply return (e.g. MOV PC, LR; POP { ,PC}).

last_instr_cond: it indicates if the last instruction was conditional.

But these three fields are not saved into cs_etm_packet struct, thus cs-etm layer don't know related information and cannot generate sample flags for branch instructions.

This patch add corresponding three new fields in cs_etm_packet struct and save related value into the packet structure, it is preparation for supporting sample flags.

Signed-off-by: Leo Yan leo.yan@linaro.org

tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 9 +++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 3 +++ 2 files changed, 12 insertions(+)

diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 8c155575c6c5..8a19310500d9 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -290,6 +290,9 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder) decoder->packet_buffer[i].instr_count = 0; decoder->packet_buffer[i].last_instr_taken_branch = false; decoder->packet_buffer[i].last_instr_size = 0;

• decoder->packet_buffer[i].last_instr_type = 0;
  

• decoder->packet_buffer[i].last_instr_subtype = 0;
  

• decoder->packet_buffer[i].last_instr_cond = 0;
  

  decoder->packet_buffer[i].cpu = INT_MIN; }

} @@ -323,6 +326,9 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_buffer[et].instr_count = 0; decoder->packet_buffer[et].last_instr_taken_branch = false; decoder->packet_buffer[et].last_instr_size = 0;

• decoder->packet_buffer[et].last_instr_type = 0;
• decoder->packet_buffer[et].last_instr_subtype = 0;
• decoder->packet_buffer[et].last_instr_cond = 0;

if (decoder->packet_count == MAX_BUFFER - 1) return OCSD_RESP_WAIT; @@ -366,6 +372,9 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder, packet->start_addr = elem->st_addr; packet->end_addr = elem->en_addr; packet->instr_count = elem->num_instr_range;

• packet->last_instr_type = elem->last_i_type;
• packet->last_instr_subtype = elem->last_i_subtype;
• packet->last_instr_cond = elem->last_instr_cond;

switch (elem->last_i_type) { case OCSD_INSTR_BR: diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index a6407d41598f..7cdd6a9c68a7 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -43,6 +43,9 @@ struct cs_etm_packet { u64 start_addr; u64 end_addr; u32 instr_count;

• u32 last_instr_type;
• u32 last_instr_subtype;
• u8 last_instr_cond; u8 last_instr_taken_branch; u8 last_instr_size; int cpu;

Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org

-- 2.17.1

On Sat, Jan 19, 2019 at 09:43:42AM +0800, Leo Yan wrote:

In the middle of trace stream, it might be interrupted thus the trace data is not continuous, the trace stream firstly is ended for previous trace block and restarted for next block.

To display related information for showing trace is restarted, this patch set sample flags for trace discontinuity:

• If one discontinuity packet is coming, append flag PERF_IP_FLAG_TRACE_END to the previous packet to indicate the trace has been ended;
• If one instruction packet is following discontinuity packet, this instruction packet is the first one packet to restarting trace. So set flag PERF_IP_FLAG_TRACE_START to discontinuity packet, this flag will be used to generate sample when connect with the sequential instruction packet.

Signed-off-by: Leo Yan leo.yan@linaro.org

tools/perf/util/cs-etm.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index d05cac5295f1..1aa29633ce77 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1111,6 +1111,7 @@ static int cs_etm__end_block(struct cs_etm_queue *etmq) static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) { struct cs_etm_packet *packet = etmq->packet;

• struct cs_etm_packet *prev_packet = etmq->prev_packet;

switch (packet->sample_type) { case CS_ETM_RANGE: @@ -1170,8 +1171,26 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) packet->last_instr_subtype == OCSD_S_INSTR_V8_RET) packet->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_RETURN;

• /*
  

•  * Decoder might insert a discontinuity in the middle of
  

•  * instruction packets, fixup prev_packet with flag
  

•  * PERF_IP_FLAG_TRACE_BEGIN to indicate restarting trace.
  

•  */
  

• if (prev_packet->sample_type == CS_ETM_DISCONTINUITY)
  

• 	prev_packet->flags |= PERF_IP_FLAG_BRANCH |
  

• 			      PERF_IP_FLAG_TRACE_BEGIN;
  

  break; case CS_ETM_DISCONTINUITY:

• /*
  

•  * The trace is discontinuous, if the previous packet is
  

•  * instruction packet, set flag PERF_IP_FLAG_TRACE_END
  

•  * for previous packet.
  

•  */
  

• if (prev_packet->sample_type == CS_ETM_RANGE)
  

• 	prev_packet->flags |= PERF_IP_FLAG_BRANCH |
  

• 			      PERF_IP_FLAG_TRACE_END;
  

• break;
  

  case CS_ETM_EXCEPTION: case CS_ETM_EXCEPTION_RET: case CS_ETM_EMPTY:

Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org

-- 2.17.1

On Sat, Jan 19, 2019 at 09:43:44AM +0800, Leo Yan wrote:

If packet processing wants to know the packet is bound with which ETM version, it needs to access metadata to decide that based on metadata magic number; but we cannot simply to use CPU logic ID number as index to access metadata sequential array, especially when system have hotplugged off CPUs, the metadata array are only allocated for online CPUs but not offline CPUs, so the CPU logic number doesn't match with its index in the array.

For this reason, a reliable way for accessing metadata array is to use traceID to find associated metadata; by accessing metadata content we can know not only the CPU number but also for ETM version, which can be used for sequential change for setting sample flags for exception packets.

This paragraph is not needed to understand why this patch is needed. Please remove.

This patch is to change tuple from traceID-CPU# to traceID-metadata, thus it can use the tuple to retrieve metadata pointer according to traceID.

For safe accessing metadata fields, this patch provides helper function cs_etm__get_cpu() which is used to return CPU number according to traceID; cs_etm_decoder__buffer_packet() is the first consumer for this helper function.

Signed-off-by: Leo Yan leo.yan@linaro.org

.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 8 ++-- tools/perf/util/cs-etm.c | 37 ++++++++++++++++--- tools/perf/util/cs-etm.h | 4 +- 3 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 294efa76c9e3..cdd38ffd10d2 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -305,14 +305,12 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, enum cs_etm_sample_type sample_type) { u32 et = 0;

• struct int_node *inode = NULL;

• int cpu;

if (decoder->packet_count >= MAX_BUFFER - 1) return OCSD_RESP_FATAL_SYS_ERR;

• /* Search the RB tree for the cpu associated with this traceID */
• inode = intlist__find(traceid_list, trace_chan_id);
• if (!inode)

• if (cs_etm__get_cpu(trace_chan_id, &cpu) < 0) return OCSD_RESP_FATAL_SYS_ERR;

et = decoder->tail; @@ -322,7 +320,7 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder, decoder->packet_buffer[et].sample_type = sample_type; decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN;

• decoder->packet_buffer[et].cpu = *((int *)inode->priv);

• decoder->packet_buffer[et].cpu = cpu; decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR; decoder->packet_buffer[et].instr_count = 0;

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 1aa29633ce77..e89989fe0a5c 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -97,6 +97,20 @@ static u32 cs_etm__get_v7_protocol_version(u32 etmidr) return CS_ETM_PROTO_ETMV3; } +int cs_etm__get_cpu(u8 trace_chan_id, int *cpu) +{

• struct int_node *inode;
• u64 *metadata;
• inode = intlist__find(traceid_list, trace_chan_id);
• if (!inode)

• return -EINVAL;
  

• metadata = inode->priv;
• *cpu = (int)metadata[CS_ETM_CPU];
• return 0;

+}

static void cs_etm__packet_dump(const char *pkt_string) { const char *color = PERF_COLOR_BLUE; @@ -252,7 +266,7 @@ static void cs_etm__free(struct perf_session *session) cs_etm__free_events(session); session->auxtrace = NULL;

• /* First remove all traceID/CPU# nodes for the RB tree */

• /* First remove all traceID/metadata nodes for the RB tree */ intlist__for_each_entry_safe(inode, tmp, traceid_list) intlist__remove(traceid_list, inode); /* Then the RB tree itself */

@@ -1519,9 +1533,20 @@ int cs_etm__process_auxtrace_info(union perf_event *event, 0xffffffff); /*

• * Create an RB tree for traceID-CPU# tuple. Since the conversion has
  

• * to be made for each packet that gets decoded, optimizing access in
  

• * anything other than a sequential array is worth doing.
  

• * Create an RB tree for traceID-metadata tuple.
  

• *
  

• * The conversion between traceID and CPU logic ID number has to
  

• * be made for each packet that gets decoded: firstly retrieve
  

• * metadata pointer from trace ID by using traceID-metadata tuple,
  

• * then read CPU logic ID number in metadata.
  

• *
  

• * It's not safe to directly use CPU logic ID number as index to
  

• * access metadata sequential array, e.g. when system have
  

• * hotplugged out CPUs, the metadata array are only allocated for
  

• * online CPUs but not offline CPUs, thus the CPU logic number is
  

• * not consistent with its index in the arrary.  For this reason,
  

• * we need to fallback to use TraceID-metadata tuple as a reliable
  

• * method to access metadata.
  

Why adding this long comment? To me all that is needed is s/traceID-CPU#/traceID-metadata .

*/

traceid_list = intlist__new(NULL); if (!traceid_list) { @@ -1587,8 +1612,8 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = -EINVAL; goto err_free_metadata; }

• /* All good, associate the traceID with the CPU# */
  

• inode->priv = &metadata[j][CS_ETM_CPU];
  

• /* All good, associate the traceID with the metadata pointer */
  

• inode->priv = metadata[j];
  

  }

/* diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 37f8d48179ca..5d70d10f3907 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -53,7 +53,7 @@ enum { CS_ETMV4_PRIV_MAX, }; -/* RB tree for quick conversion between traceID and CPUs */ +/* RB tree for quick conversion between traceID and metadata pointers */ struct intlist *traceid_list; #define KiB(x) ((x) * 1024) @@ -78,4 +78,6 @@ cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused, } #endif +int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);

This function is part of a public header that can theoretically be included by any other file. As such it has to be defined within the HAVE_CSTRACE_SUPPORT define.

#endif

2.17.1

On Sat, Jan 19, 2019 at 09:43:46AM +0800, Leo Yan wrote:

The exception taken and returning are typical flow for instruction jump but it needs to be handled with exception packets. This patch is to set sample flags for exception packet.

Since the exception packet contains the exception number, according to the exception number this patch makes decision for belonging to which exception types.

The decoder have defined different exception number for ETMv3 and ETMv4 separately, hence this patch needs firstly decide the ETM version by using the metadata magic number, and this patch adds helper function cs_etm__get_magic() for easily getting magic number.

Based on different ETM version, the exception packet contains the exception number, according to the exception number this patch makes decision for the exception belonging to which exception types.

In this patch, it introduces helper function cs_etm__is_svc_instr(); for ETMv4 CS_ETMV4_EXC_CALL covers SVC, SMC and HVC cases in the single exception number, thus need to use cs_etm__is_svc_instr() to decide an exception taken for system call.

Reviewed-by: Robert Walker robert.walker@arm.com Signed-off-by: Leo Yan leo.yan@linaro.org

This is the other way around, i.e you wrote the code and then Robert reviewed it. With this change:

Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org

---

tools/perf/util/cs-etm.c | 215 +++++++++++++++++++++++++++++++++++++++ tools/perf/util/cs-etm.h | 44 ++++++++ 2 files changed, 259 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index e89989fe0a5c..052805de6513 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -97,6 +97,20 @@ static u32 cs_etm__get_v7_protocol_version(u32 etmidr) return CS_ETM_PROTO_ETMV3; } +static int cs_etm__get_magic(u8 trace_chan_id, u64 *magic) +{

• struct int_node *inode;
• u64 *metadata;
• inode = intlist__find(traceid_list, trace_chan_id);
• if (!inode)

• return -EINVAL;
  

• metadata = inode->priv;
• *magic = metadata[CS_ETM_MAGIC];
• return 0;

+}

int cs_etm__get_cpu(u8 trace_chan_id, int *cpu) { struct int_node *inode; @@ -1122,10 +1136,174 @@ static int cs_etm__end_block(struct cs_etm_queue *etmq) return 0; } +static bool cs_etm__is_svc_instr(struct cs_etm_queue *etmq,

• 		 struct cs_etm_packet *packet,
  

• 		 u64 end_addr)
  

+{

• u16 instr16;
• u32 instr32;
• u64 addr;
• switch (packet->isa) {
• case CS_ETM_ISA_T32:

• /*
  

•  * The SVC of T32 is defined in ARM DDI 0487D.a, F5.1.247:
  

•  *
  

•  *  b'15         b'8
  

•  * +-----------------+--------+
  

•  * | 1 1 0 1 1 1 1 1 |  imm8  |
  

•  * +-----------------+--------+
  

•  *
  

•  * According to the specifiction, it only defines SVC for T32
  

•  * with 16 bits instruction and has no definition for 32bits;
  

•  * so below only read 2 bytes as instruction size for T32.
  

•  */
  

• addr = end_addr - 2;
  

• cs_etm__mem_access(etmq, addr, sizeof(instr16), (u8 *)&instr16);
  

• if ((instr16 & 0xFF00) == 0xDF00)
  

• 	return true;
  

• break;
  

• case CS_ETM_ISA_A32:

• /*
  

•  * The SVC of A32 is defined in ARM DDI 0487D.a, F5.1.247:
  

•  *
  

•  *  b'31 b'28 b'27 b'24
  

•  * +---------+---------+-------------------------+
  

•  * |  !1111  | 1 1 1 1 |        imm24            |
  

•  * +---------+---------+-------------------------+
  

•  */
  

• addr = end_addr - 4;
  

• cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32);
  

• if ((instr32 & 0x0F000000) == 0x0F000000 &&
  

•     (instr32 & 0xF0000000) != 0xF0000000)
  

• 	return true;
  

• break;
  

• case CS_ETM_ISA_A64:

• /*
  

•  * The SVC of A64 is defined in ARM DDI 0487D.a, C6.2.294:
  

•  *
  

•  *  b'31               b'21           b'4     b'0
  

•  * +-----------------------+---------+-----------+
  

•  * | 1 1 0 1 0 1 0 0 0 0 0 |  imm16  | 0 0 0 0 1 |
  

•  * +-----------------------+---------+-----------+
  

•  */
  

• addr = end_addr - 4;
  

• cs_etm__mem_access(etmq, addr, sizeof(instr32), (u8 *)&instr32);
  

• if ((instr32 & 0xFFE0001F) == 0xd4000001)
  

• 	return true;
  

• break;
  

• case CS_ETM_ISA_UNKNOWN:
• default:

• break;
  

• }
• return false;

+}

+static bool cs_etm__is_syscall(struct cs_etm_queue *etmq, u64 magic) +{

• struct cs_etm_packet *packet = etmq->packet;
• struct cs_etm_packet *prev_packet = etmq->prev_packet;
• if (magic == __perf_cs_etmv3_magic)

• if (packet->exception_number == CS_ETMV3_EXC_SVC)
  

• 	return true;
  

• /*

• * ETMv4 exception type CS_ETMV4_EXC_CALL covers SVC, SMC and
  

• * HVC cases; need to check if it's SVC instruction based on
  

• * packet address.
  

• */
  

• if (magic == __perf_cs_etmv4_magic) {

• if (packet->exception_number == CS_ETMV4_EXC_CALL &&
  

•     cs_etm__is_svc_instr(etmq, prev_packet,
  

• 			 prev_packet->end_addr))
  

• 	return true;
  

• }
• return false;

+}

+static bool cs_etm__is_async_exception(struct cs_etm_queue *etmq, u64 magic) +{

• struct cs_etm_packet *packet = etmq->packet;
• if (magic == __perf_cs_etmv3_magic)

• if (packet->exception_number == CS_ETMV3_EXC_DEBUG_HALT ||
  

•     packet->exception_number == CS_ETMV3_EXC_ASYNC_DATA_ABORT ||
  

•     packet->exception_number == CS_ETMV3_EXC_PE_RESET ||
  

•     packet->exception_number == CS_ETMV3_EXC_IRQ ||
  

•     packet->exception_number == CS_ETMV3_EXC_FIQ)
  

• 	return true;
  

• if (magic == __perf_cs_etmv4_magic)

• if (packet->exception_number == CS_ETMV4_EXC_RESET ||
  

•     packet->exception_number == CS_ETMV4_EXC_DEBUG_HALT ||
  

•     packet->exception_number == CS_ETMV4_EXC_SYSTEM_ERROR ||
  

•     packet->exception_number == CS_ETMV4_EXC_INST_DEBUG ||
  

•     packet->exception_number == CS_ETMV4_EXC_DATA_DEBUG ||
  

•     packet->exception_number == CS_ETMV4_EXC_IRQ ||
  

•     packet->exception_number == CS_ETMV4_EXC_FIQ)
  

• 	return true;
  

• return false;

+}

+static bool cs_etm__is_sync_exception(struct cs_etm_queue *etmq, u64 magic) +{

• struct cs_etm_packet *packet = etmq->packet;
• struct cs_etm_packet *prev_packet = etmq->prev_packet;
• if (magic == __perf_cs_etmv3_magic)

• if (packet->exception_number == CS_ETMV3_EXC_SMC ||
  

•     packet->exception_number == CS_ETMV3_EXC_HYP ||
  

•     packet->exception_number == CS_ETMV3_EXC_JAZELLE_THUMBEE ||
  

•     packet->exception_number == CS_ETMV3_EXC_UNDEFINED_INSTR ||
  

•     packet->exception_number == CS_ETMV3_EXC_PREFETCH_ABORT ||
  

•     packet->exception_number == CS_ETMV3_EXC_DATA_FAULT ||
  

•     packet->exception_number == CS_ETMV3_EXC_GENERIC)
  

• 	return true;
  

• if (magic == __perf_cs_etmv4_magic) {

• if (packet->exception_number == CS_ETMV4_EXC_TRAP ||
  

•     packet->exception_number == CS_ETMV4_EXC_ALIGNMENT ||
  

•     packet->exception_number == CS_ETMV4_EXC_INST_FAULT ||
  

•     packet->exception_number == CS_ETMV4_EXC_DATA_FAULT)
  

• 	return true;
  

• /*
  

•  * For CS_ETMV4_EXC_CALL, except SVC other instructions
  

•  * (SMC, HVC) are taken as sync exceptions.
  

•  */
  

• if (packet->exception_number == CS_ETMV4_EXC_CALL &&
  

•     !cs_etm__is_svc_instr(etmq, prev_packet,
  

• 			  prev_packet->end_addr))
  

• 	return true;
  

• /*
  

•  * ETMv4 has 5 bits for exception number; if the numbers
  

•  * are in the range ( CS_ETMV4_EXC_FIQ, CS_ETMV4_EXC_END ]
  

•  * they are implementation defined exceptions.
  

•  *
  

•  * For this case, simply take it as sync exception.
  

•  */
  

• if (packet->exception_number > CS_ETMV4_EXC_FIQ &&
  

•     packet->exception_number <= CS_ETMV4_EXC_END)
  

• 	return true;
  

• }
• return false;

+}

static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) { struct cs_etm_packet *packet = etmq->packet; struct cs_etm_packet *prev_packet = etmq->prev_packet;

• u64 magic;
• int ret;

switch (packet->sample_type) { case CS_ETM_RANGE: @@ -1206,6 +1384,43 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) PERF_IP_FLAG_TRACE_END; break; case CS_ETM_EXCEPTION:

• ret = cs_etm__get_magic(packet->trace_chan_id, &magic);
  

• if (ret)
  

• 	return ret;
  

• /* The exception is for system call. */
  

• if (cs_etm__is_syscall(etmq, magic))
  

• 	packet->flags = PERF_IP_FLAG_BRANCH |
  

• 			PERF_IP_FLAG_CALL |
  

• 			PERF_IP_FLAG_SYSCALLRET;
  

• /*
  

•  * The exceptions are triggered by external signals from bus,
  

•  * interrupt controller, debug module, PE reset or halt.
  

•  */
  

• else if (cs_etm__is_async_exception(etmq, magic))
  

• 	packet->flags = PERF_IP_FLAG_BRANCH |
  

• 			PERF_IP_FLAG_CALL |
  

• 			PERF_IP_FLAG_ASYNC |
  

• 			PERF_IP_FLAG_INTERRUPT;
  

• /*
  

•  * Otherwise, exception is caused by trap, instruction &
  

•  * data fault, or alignment errors.
  

•  */
  

• else if (cs_etm__is_sync_exception(etmq, magic))
  

• 	packet->flags = PERF_IP_FLAG_BRANCH |
  

• 			PERF_IP_FLAG_CALL |
  

• 			PERF_IP_FLAG_INTERRUPT;
  

• /*
  

•  * When the exception packet is inserted, since exception
  

•  * packet is not used standalone for generating samples
  

•  * and it's affiliation to the previous instruction range
  

•  * packet; so set previous range packet flags to tell perf
  

•  * it is an exception taken branch.
  

•  */
  

• if (prev_packet->sample_type == CS_ETM_RANGE)
  

• 	prev_packet->flags = packet->flags;
  

• break;
  

  case CS_ETM_EXCEPTION_RET: case CS_ETM_EMPTY: default:

diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 5d70d10f3907..7bd16ea8a62d 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -53,6 +53,50 @@ enum { CS_ETMV4_PRIV_MAX, }; +/*

• • ETMv3 exception encoding number:
• • See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
• • table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
• */

+enum {

• CS_ETMV3_EXC_NONE = 0,
• CS_ETMV3_EXC_DEBUG_HALT = 1,
• CS_ETMV3_EXC_SMC = 2,
• CS_ETMV3_EXC_HYP = 3,
• CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
• CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
• CS_ETMV3_EXC_PE_RESET = 8,
• CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
• CS_ETMV3_EXC_SVC = 10,
• CS_ETMV3_EXC_PREFETCH_ABORT = 11,
• CS_ETMV3_EXC_DATA_FAULT = 12,
• CS_ETMV3_EXC_GENERIC = 13,
• CS_ETMV3_EXC_IRQ = 14,
• CS_ETMV3_EXC_FIQ = 15,

+};

+/*

• • ETMv4 exception encoding number:
• • See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
• • table 6-12 Possible values for the TYPE field in an Exception instruction
• • trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
• */

+enum {

• CS_ETMV4_EXC_RESET = 0,
• CS_ETMV4_EXC_DEBUG_HALT = 1,
• CS_ETMV4_EXC_CALL = 2,
• CS_ETMV4_EXC_TRAP = 3,
• CS_ETMV4_EXC_SYSTEM_ERROR = 4,
• CS_ETMV4_EXC_INST_DEBUG = 6,
• CS_ETMV4_EXC_DATA_DEBUG = 7,
• CS_ETMV4_EXC_ALIGNMENT = 10,
• CS_ETMV4_EXC_INST_FAULT = 11,
• CS_ETMV4_EXC_DATA_FAULT = 12,
• CS_ETMV4_EXC_IRQ = 14,
• CS_ETMV4_EXC_FIQ = 15,
• CS_ETMV4_EXC_END = 31,

+};

/* RB tree for quick conversion between traceID and metadata pointers */ struct intlist *traceid_list; -- 2.17.1

Hi Mathieu,

On Wed, Jan 23, 2019 at 02:51:14PM -0700, Mathieu Poirier wrote:

On Sat, Jan 19, 2019 at 09:43:47AM +0800, Leo Yan wrote:

...

When return from exception, we need to distinguish if it's system call return or for other type exceptions for setting sample flags. Due to the exception return packet doesn't contain exception number, so we cannot decide sample flags based on exception number.

On the other hand, the exception return packet is followed by an instruction range packet; this range packet deliveries the start address after exception handling, we can check if it is a SVC instruction just before the start address. If there has one SVC instruction is found ahead the return address, this means it's an exception return for system call; otherwise it is an normal return for other exceptions.

This patch is to set sample flags for exception return packet, firstly it simply set sample flags as PERF_IP_FLAG_INTERRUPT for all exception returns since at this point it doesn't know what's exactly the exception type. We will defer to decide if it's an exception return for system call when the next instruction range packet comes, it checks if there has one SVC instruction prior to the start address and if so we will change sample flags to PERF_IP_FLAG_SYSCALLRET for system call return.

Signed-off-by: Leo Yan leo.yan@linaro.org

tools/perf/util/cs-etm.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 052805de6513..7547a7178f46 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1372,6 +1372,20 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) if (prev_packet->sample_type == CS_ETM_DISCONTINUITY) prev_packet->flags |= PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TRACE_BEGIN;

• /*
  

•  * If the previous packet is an exception return packet
  

•  * and the return address just follows SVC instuction,
  

•  * it needs to calibrate the previous packet sample flags
  

•  * as PERF_IP_FLAG_SYSCALLRET.
  

•  */
  

• if (prev_packet->flags == (PERF_IP_FLAG_BRANCH |
  

• 			   PERF_IP_FLAG_RETURN |
  

• 			   PERF_IP_FLAG_INTERRUPT) &&
  

Would it make more sense to just look for prev-packet->sample_type == CS_ETM_EXCEPTION_RET ?

We cannot check 'prev-packet->sample_type == CS_ETM_EXCEPTION_RET', since CS_ETM_EXCEPTION_RET is associated to its previous instruction range packet but not a standalone instruction range packet, we don't swap for exception and exception return packets, 'prev_packet' is pointed to the previous instruction range packet at here.

This is why we need to use 'prev_packet->flags' but not 'prev_packet->sample_type' as checking condition.

Thanks, Leo Yan

...

•     cs_etm__is_svc_instr(etmq, packet, packet->start_addr))
  

• 	prev_packet->flags = PERF_IP_FLAG_BRANCH |
  

• 			     PERF_IP_FLAG_RETURN |
  

• 			     PERF_IP_FLAG_SYSCALLRET;
  

  break; case CS_ETM_DISCONTINUITY: /*

@@ -1422,6 +1436,36 @@ static int cs_etm__set_sample_flags(struct cs_etm_queue *etmq) prev_packet->flags = packet->flags; break; case CS_ETM_EXCEPTION_RET:

• /*
  

•  * When the exception return packet is inserted, since
  

•  * exception return packet is not used standalone for
  

•  * generating samples and it's affiliation to the previous
  

•  * instruction range packet; so set previous range packet
  

•  * flags to tell perf it is an exception return branch.
  

•  *
  

•  * The exception return can be for either system call or
  

•  * other exception types; unfortunately the packet doesn't
  

•  * contain exception type related info so we cannot decide
  

•  * the exception type purely based on exception return packet.
  

•  * If we record the exception number from exception packet and
  

•  * reuse it for excpetion return packet, this is not reliable
  

•  * due the trace can be discontinuity or the interrupt can
  

•  * be nested, thus the recorded exception number cannot be
  

•  * used for exception return packet for these two cases.
  

•  *
  

•  * For exception return packet, we only need to distinguish the
  

•  * packet is for system call or for other types.  Thus the
  

•  * decision can be deferred when receive the next packet which
  

•  * contains the return address, based on the return address we
  

•  * can read out the previous instruction and check if it's a
  

•  * system call instruction and then calibrate the sample flag
  

•  * as needed.
  

•  */
  

• if (prev_packet->sample_type == CS_ETM_RANGE)
  

• 	prev_packet->flags = PERF_IP_FLAG_BRANCH |
  

• 			     PERF_IP_FLAG_RETURN |
  

• 			     PERF_IP_FLAG_INTERRUPT;
  

• break;
  

  case CS_ETM_EMPTY: default: break;

-- 2.17.1