Hi
Thanks for the report. I have fixed all of them.
Suzuki
On 12/10/2021 16:31, Randy Dunlap wrote:
Hi,
On 10/12/21 6:17 AM, Suzuki K Poulose wrote:
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 077f2ec4eeb2..404f56e87e93 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -666,6 +666,47 @@ config ARM64_ERRATUM_1508412 If unsure, say Y. +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE + bool
+config ARM64_ERRATUM_2119858 + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" + default y + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in + depends on CORESIGHT_TRBE + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE + help + This option adds the workaround for ARM Cortex-A710 erratum 2119858.
+ Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace
up to
+ data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in
pointed to by
+ the event of a WRAP event.
+ Work around the issue by always making sure we move the TRBPTR_EL1 by + 256bytes before enabling the buffer and filling the first 256bytes of
256 bytes 256 bytes
+ the buffer with ETM ignore packets upon disabling.
+ If unsure, say Y.
+config ARM64_ERRATUM_2139208 + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" + default y + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in + depends on CORESIGHT_TRBE + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE + help + This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
+ Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace
up to
+ data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in
pointed to by
+ the event of a WRAP event.
+ Work around the issue by always making sure we move the TRBPTR_EL1 by + 256bytes before enabling the buffer and filling the first 256bytes of
256 bytes 256 bytes
+ the buffer with ETM ignore packets upon disabling.
+ If unsure, say Y.
-
Suzuki K Poulose